2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 15
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
48 struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
54 #include "nouveau_drm.h"
55 #include "nouveau_reg.h"
56 #include "nouveau_bios.h"
59 #define MAX_NUM_DCB_ENTRIES 16
61 #define NOUVEAU_MAX_CHANNEL_NR 128
63 #define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
64 #define NV50_VM_BLOCK (512*1024*1024ULL)
65 #define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
68 struct ttm_buffer_object bo;
69 struct ttm_placement placement;
71 struct ttm_bo_kmap_obj kmap;
72 struct list_head head;
74 /* protected by ttm_bo_reserve() */
75 struct drm_file *reserved_by;
76 struct list_head entry;
79 struct nouveau_channel *channel;
87 struct drm_gem_object *gem;
88 struct drm_file *cpu_filp;
92 static inline struct nouveau_bo *
93 nouveau_bo(struct ttm_buffer_object *bo)
95 return container_of(bo, struct nouveau_bo, bo);
98 static inline struct nouveau_bo *
99 nouveau_gem_object(struct drm_gem_object *gem)
101 return gem ? gem->driver_private : NULL;
104 /* TODO: submit equivalent to TTM generic API upstream? */
105 static inline void __iomem *
106 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
109 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
110 &nvbo->kmap, &is_iomem);
111 WARN_ON_ONCE(ioptr && !is_iomem);
116 struct mem_block *next;
117 struct mem_block *prev;
120 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
124 NV_NFORCE = 0x10000000,
125 NV_NFORCE2 = 0x20000000
128 #define NVOBJ_ENGINE_SW 0
129 #define NVOBJ_ENGINE_GR 1
130 #define NVOBJ_ENGINE_DISPLAY 2
131 #define NVOBJ_ENGINE_INT 0xdeadbeef
133 #define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
134 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
135 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
136 #define NVOBJ_FLAG_FAKE (1 << 3)
137 struct nouveau_gpuobj {
138 struct list_head list;
140 struct nouveau_channel *im_channel;
141 struct mem_block *im_pramin;
142 struct nouveau_bo *im_backing;
143 uint32_t im_backing_start;
144 uint32_t *im_backing_suspend;
153 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
157 struct nouveau_gpuobj_ref {
158 struct list_head list;
160 struct nouveau_gpuobj *gpuobj;
163 struct nouveau_channel *channel;
167 struct nouveau_channel {
168 struct drm_device *dev;
171 /* owner of this fifo */
172 struct drm_file *file_priv;
173 /* mapping of the fifo itself */
174 struct drm_local_map *map;
176 /* mapping of the regs controling the fifo */
183 /* lock protects the pending list only */
185 struct list_head pending;
187 uint32_t sequence_ack;
188 uint32_t last_sequence_irq;
191 /* DMA push buffer */
192 struct nouveau_gpuobj_ref *pushbuf;
193 struct nouveau_bo *pushbuf_bo;
194 uint32_t pushbuf_base;
196 /* Notifier memory */
197 struct nouveau_bo *notifier_bo;
198 struct mem_block *notifier_heap;
201 struct nouveau_gpuobj_ref *ramfc;
202 struct nouveau_gpuobj_ref *cache;
205 /* XXX may be merge 2 pointers as private data ??? */
206 struct nouveau_gpuobj_ref *ramin_grctx;
210 struct nouveau_gpuobj *vm_pd;
211 struct nouveau_gpuobj_ref *vm_gart_pt;
212 struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR];
215 struct nouveau_gpuobj_ref *ramin; /* Private instmem */
216 struct mem_block *ramin_heap; /* Private PRAMIN heap */
217 struct nouveau_gpuobj_ref *ramht; /* Hash table */
218 struct list_head ramht_refs; /* Objects referenced by RAMHT */
220 /* GPU object info for stuff used in-kernel (mm_enabled) */
222 uint32_t vram_handle;
223 uint32_t gart_handle;
226 /* Push buffer state (only for drm's channel on !mm_enabled) */
232 /* access via pushbuf_bo */
235 uint32_t sw_subchannel[8];
238 struct nouveau_gpuobj *vblsem;
239 uint32_t vblsem_offset;
240 uint32_t vblsem_rval;
241 struct list_head vbl_wait;
247 struct drm_info_list info;
251 struct nouveau_instmem_engine {
254 int (*init)(struct drm_device *dev);
255 void (*takedown)(struct drm_device *dev);
256 int (*suspend)(struct drm_device *dev);
257 void (*resume)(struct drm_device *dev);
259 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
261 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
262 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
263 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
264 void (*prepare_access)(struct drm_device *, bool write);
265 void (*finish_access)(struct drm_device *);
268 struct nouveau_mc_engine {
269 int (*init)(struct drm_device *dev);
270 void (*takedown)(struct drm_device *dev);
273 struct nouveau_timer_engine {
274 int (*init)(struct drm_device *dev);
275 void (*takedown)(struct drm_device *dev);
276 uint64_t (*read)(struct drm_device *dev);
279 struct nouveau_fb_engine {
280 int (*init)(struct drm_device *dev);
281 void (*takedown)(struct drm_device *dev);
284 struct nouveau_fifo_engine {
289 int (*init)(struct drm_device *);
290 void (*takedown)(struct drm_device *);
292 void (*disable)(struct drm_device *);
293 void (*enable)(struct drm_device *);
294 bool (*reassign)(struct drm_device *, bool enable);
295 bool (*cache_flush)(struct drm_device *dev);
296 bool (*cache_pull)(struct drm_device *dev, bool enable);
298 int (*channel_id)(struct drm_device *);
300 int (*create_context)(struct nouveau_channel *);
301 void (*destroy_context)(struct nouveau_channel *);
302 int (*load_context)(struct nouveau_channel *);
303 int (*unload_context)(struct drm_device *);
306 struct nouveau_pgraph_object_method {
308 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
312 struct nouveau_pgraph_object_class {
315 struct nouveau_pgraph_object_method *methods;
318 struct nouveau_pgraph_engine {
319 struct nouveau_pgraph_object_class *grclass;
325 int (*init)(struct drm_device *);
326 void (*takedown)(struct drm_device *);
328 void (*fifo_access)(struct drm_device *, bool);
330 struct nouveau_channel *(*channel)(struct drm_device *);
331 int (*create_context)(struct nouveau_channel *);
332 void (*destroy_context)(struct nouveau_channel *);
333 int (*load_context)(struct nouveau_channel *);
334 int (*unload_context)(struct drm_device *);
337 struct nouveau_engine {
338 struct nouveau_instmem_engine instmem;
339 struct nouveau_mc_engine mc;
340 struct nouveau_timer_engine timer;
341 struct nouveau_fb_engine fb;
342 struct nouveau_pgraph_engine graph;
343 struct nouveau_fifo_engine fifo;
346 struct nouveau_pll_vals {
350 uint8_t N1, M1, N2, M2;
352 uint8_t M1, N1, M2, N2;
357 } __attribute__((packed));
364 enum nv04_fp_display_regs {
374 struct nv04_crtc_reg {
375 unsigned char MiscOutReg; /* */
378 uint8_t Sequencer[5];
380 uint8_t Attribute[21];
381 unsigned char DAC[768]; /* Internal Colorlookuptable */
391 uint32_t crtc_eng_ctrl;
394 uint32_t nv10_cursync;
395 struct nouveau_pll_vals pllvals;
396 uint32_t ramdac_gen_ctrl;
402 uint32_t tv_vsync_delay;
405 uint32_t tv_hsync_delay;
406 uint32_t tv_hsync_delay2;
407 uint32_t fp_horiz_regs[7];
408 uint32_t fp_vert_regs[7];
411 uint32_t dither_regs[6];
415 uint32_t fp_margin_color;
420 uint32_t ctv_regs[38];
423 struct nv04_output_reg {
428 struct nv04_mode_state {
456 uint32_t cursorConfig;
465 struct nv04_crtc_reg crtc_reg[2];
468 enum nouveau_card_type {
477 struct drm_nouveau_private {
478 struct drm_device *dev;
480 NOUVEAU_CARD_INIT_DOWN,
481 NOUVEAU_CARD_INIT_DONE,
482 NOUVEAU_CARD_INIT_FAILED
485 /* the card type, takes NV_* as values */
486 enum nouveau_card_type card_type;
487 /* exact chipset, derived from NV_PMC_BOOT_0 */
495 struct workqueue_struct *wq;
496 struct work_struct irq_work;
498 struct list_head vbl_waiting;
501 struct ttm_global_reference mem_global_ref;
502 struct ttm_bo_global_ref bo_global_ref;
503 struct ttm_bo_device bdev;
504 spinlock_t bo_list_lock;
505 struct list_head bo_list;
506 atomic_t validate_sequence;
509 struct fb_info *fbdev_info;
511 int fifo_alloc_count;
512 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
514 struct nouveau_engine engine;
515 struct nouveau_channel *channel;
517 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
518 struct nouveau_gpuobj *ramht;
519 uint32_t ramin_rsvd_vram;
520 uint32_t ramht_offset;
523 uint32_t ramfc_offset;
525 uint32_t ramro_offset;
528 /* base physical adresses */
530 uint64_t fb_available_size;
531 uint64_t fb_mappable_pages;
532 uint64_t fb_aper_free;
536 NOUVEAU_GART_NONE = 0,
544 struct nouveau_gpuobj *sg_ctxdma;
545 struct page *sg_dummy_page;
546 dma_addr_t sg_dummy_bus;
549 struct drm_ttm_backend *sg_be;
550 unsigned long sg_handle;
553 /* G8x/G9x virtual address space */
554 uint64_t vm_gart_base;
555 uint64_t vm_gart_size;
556 uint64_t vm_vram_base;
557 uint64_t vm_vram_size;
559 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
562 /* the mtrr covering the FB */
565 struct mem_block *ramin_heap;
567 /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
568 uint32_t ctx_table_size;
569 struct nouveau_gpuobj_ref *ctx_table;
571 struct list_head gpuobj_list;
574 struct nouveau_bios_info *vbios;
576 struct nv04_mode_state mode_reg;
577 struct nv04_mode_state saved_reg;
578 uint32_t saved_vga_font[4][16384];
580 uint32_t dac_users[4];
582 struct nouveau_suspend_resume {
584 uint32_t graph_ctx_control;
585 uint32_t graph_state;
586 uint32_t *ramin_copy;
590 struct backlight_device *backlight;
593 struct nouveau_channel *evo;
596 struct dentry *channel_root;
600 static inline struct drm_nouveau_private *
601 nouveau_bdev(struct ttm_bo_device *bd)
603 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
607 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
609 struct nouveau_bo *prev;
615 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
617 struct ttm_buffer_object *bo = &prev->bo;
625 #define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \
626 struct drm_nouveau_private *nv = dev->dev_private; \
627 if (nv->init_state != NOUVEAU_CARD_INIT_DONE) { \
628 NV_ERROR(dev, "called without init\n"); \
633 #define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
634 struct drm_nouveau_private *nv = dev->dev_private; \
635 if (!nouveau_channel_owner(dev, (cl), (id))) { \
636 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
637 DRM_CURRENTPID, (id)); \
640 (ch) = nv->fifos[(id)]; \
644 extern int nouveau_noagp;
645 extern int nouveau_duallink;
646 extern int nouveau_uscript_lvds;
647 extern int nouveau_uscript_tmds;
648 extern int nouveau_vram_pushbuf;
649 extern int nouveau_vram_notify;
650 extern int nouveau_fbpercrtc;
651 extern char *nouveau_tv_norm;
652 extern int nouveau_reg_debug;
653 extern char *nouveau_vbios;
654 extern int nouveau_ctxfw;
656 /* nouveau_state.c */
657 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
658 extern int nouveau_load(struct drm_device *, unsigned long flags);
659 extern int nouveau_firstopen(struct drm_device *);
660 extern void nouveau_lastclose(struct drm_device *);
661 extern int nouveau_unload(struct drm_device *);
662 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
664 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
666 extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
667 uint32_t reg, uint32_t mask, uint32_t val);
668 extern bool nouveau_wait_for_idle(struct drm_device *);
669 extern int nouveau_card_init(struct drm_device *);
670 extern int nouveau_ioctl_card_init(struct drm_device *, void *data,
672 extern int nouveau_ioctl_suspend(struct drm_device *, void *data,
674 extern int nouveau_ioctl_resume(struct drm_device *, void *data,
678 extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start,
680 extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *,
681 uint64_t size, int align2,
682 struct drm_file *, int tail);
683 extern void nouveau_mem_takedown(struct mem_block **heap);
684 extern void nouveau_mem_free_block(struct mem_block *);
685 extern uint64_t nouveau_mem_fb_amount(struct drm_device *);
686 extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
687 extern int nouveau_mem_init(struct drm_device *);
688 extern int nouveau_mem_init_agp(struct drm_device *);
689 extern void nouveau_mem_close(struct drm_device *);
690 extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
691 uint32_t size, uint32_t flags,
693 extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
696 /* nouveau_notifier.c */
697 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
698 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
699 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
700 int cout, uint32_t *offset);
701 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
702 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
704 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
707 /* nouveau_channel.c */
708 extern struct drm_ioctl_desc nouveau_ioctls[];
709 extern int nouveau_max_ioctl;
710 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
711 extern int nouveau_channel_owner(struct drm_device *, struct drm_file *,
713 extern int nouveau_channel_alloc(struct drm_device *dev,
714 struct nouveau_channel **chan,
715 struct drm_file *file_priv,
716 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
717 extern void nouveau_channel_free(struct nouveau_channel *);
718 extern int nouveau_channel_idle(struct nouveau_channel *chan);
720 /* nouveau_object.c */
721 extern int nouveau_gpuobj_early_init(struct drm_device *);
722 extern int nouveau_gpuobj_init(struct drm_device *);
723 extern void nouveau_gpuobj_takedown(struct drm_device *);
724 extern void nouveau_gpuobj_late_takedown(struct drm_device *);
725 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
726 extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
727 extern void nouveau_gpuobj_resume(struct drm_device *dev);
728 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
729 uint32_t vram_h, uint32_t tt_h);
730 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
731 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
732 uint32_t size, int align, uint32_t flags,
733 struct nouveau_gpuobj **);
734 extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
735 extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
736 uint32_t handle, struct nouveau_gpuobj *,
737 struct nouveau_gpuobj_ref **);
738 extern int nouveau_gpuobj_ref_del(struct drm_device *,
739 struct nouveau_gpuobj_ref **);
740 extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle,
741 struct nouveau_gpuobj_ref **ref_ret);
742 extern int nouveau_gpuobj_new_ref(struct drm_device *,
743 struct nouveau_channel *alloc_chan,
744 struct nouveau_channel *ref_chan,
745 uint32_t handle, uint32_t size, int align,
746 uint32_t flags, struct nouveau_gpuobj_ref **);
747 extern int nouveau_gpuobj_new_fake(struct drm_device *,
748 uint32_t p_offset, uint32_t b_offset,
749 uint32_t size, uint32_t flags,
750 struct nouveau_gpuobj **,
751 struct nouveau_gpuobj_ref**);
752 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
753 uint64_t offset, uint64_t size, int access,
754 int target, struct nouveau_gpuobj **);
755 extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
756 uint64_t offset, uint64_t size,
757 int access, struct nouveau_gpuobj **,
759 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
760 struct nouveau_gpuobj **);
761 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
763 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
767 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
768 extern void nouveau_irq_preinstall(struct drm_device *);
769 extern int nouveau_irq_postinstall(struct drm_device *);
770 extern void nouveau_irq_uninstall(struct drm_device *);
772 /* nouveau_sgdma.c */
773 extern int nouveau_sgdma_init(struct drm_device *);
774 extern void nouveau_sgdma_takedown(struct drm_device *);
775 extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
777 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
779 /* nouveau_debugfs.c */
780 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
781 extern int nouveau_debugfs_init(struct drm_minor *);
782 extern void nouveau_debugfs_takedown(struct drm_minor *);
783 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
784 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
787 nouveau_debugfs_init(struct drm_minor *minor)
792 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
797 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
803 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
809 extern int nouveau_dma_init(struct nouveau_channel *);
810 extern int nouveau_dma_wait(struct nouveau_channel *, int size);
814 extern int nouveau_hybrid_setup(struct drm_device *dev);
815 extern bool nouveau_dsm_probe(struct drm_device *dev);
817 static inline int nouveau_hybrid_setup(struct drm_device *dev)
821 static inline bool nouveau_dsm_probe(struct drm_device *dev)
827 /* nouveau_backlight.c */
828 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
829 extern int nouveau_backlight_init(struct drm_device *);
830 extern void nouveau_backlight_exit(struct drm_device *);
832 static inline int nouveau_backlight_init(struct drm_device *dev)
837 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
841 extern int nouveau_bios_init(struct drm_device *);
842 extern void nouveau_bios_takedown(struct drm_device *dev);
843 extern int nouveau_run_vbios_init(struct drm_device *);
844 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
846 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
848 extern struct dcb_connector_table_entry *
849 nouveau_bios_connector_entry(struct drm_device *, int index);
850 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
852 extern int nouveau_bios_run_display_table(struct drm_device *,
854 uint32_t script, int pxclk);
855 extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
857 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
858 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
859 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
860 bool *dl, bool *if_is_24bit);
861 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
862 int head, int pxclk);
863 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
864 enum LVDS_script, int pxclk);
867 int nouveau_ttm_global_init(struct drm_nouveau_private *);
868 void nouveau_ttm_global_release(struct drm_nouveau_private *);
869 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
872 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
873 uint8_t *data, int data_nr);
874 bool nouveau_dp_detect(struct drm_encoder *);
875 bool nouveau_dp_link_train(struct drm_encoder *);
878 extern int nv04_fb_init(struct drm_device *);
879 extern void nv04_fb_takedown(struct drm_device *);
882 extern int nv10_fb_init(struct drm_device *);
883 extern void nv10_fb_takedown(struct drm_device *);
886 extern int nv40_fb_init(struct drm_device *);
887 extern void nv40_fb_takedown(struct drm_device *);
890 extern int nv04_fifo_init(struct drm_device *);
891 extern void nv04_fifo_disable(struct drm_device *);
892 extern void nv04_fifo_enable(struct drm_device *);
893 extern bool nv04_fifo_reassign(struct drm_device *, bool);
894 extern bool nv04_fifo_cache_flush(struct drm_device *);
895 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
896 extern int nv04_fifo_channel_id(struct drm_device *);
897 extern int nv04_fifo_create_context(struct nouveau_channel *);
898 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
899 extern int nv04_fifo_load_context(struct nouveau_channel *);
900 extern int nv04_fifo_unload_context(struct drm_device *);
903 extern int nv10_fifo_init(struct drm_device *);
904 extern int nv10_fifo_channel_id(struct drm_device *);
905 extern int nv10_fifo_create_context(struct nouveau_channel *);
906 extern void nv10_fifo_destroy_context(struct nouveau_channel *);
907 extern int nv10_fifo_load_context(struct nouveau_channel *);
908 extern int nv10_fifo_unload_context(struct drm_device *);
911 extern int nv40_fifo_init(struct drm_device *);
912 extern int nv40_fifo_create_context(struct nouveau_channel *);
913 extern void nv40_fifo_destroy_context(struct nouveau_channel *);
914 extern int nv40_fifo_load_context(struct nouveau_channel *);
915 extern int nv40_fifo_unload_context(struct drm_device *);
918 extern int nv50_fifo_init(struct drm_device *);
919 extern void nv50_fifo_takedown(struct drm_device *);
920 extern int nv50_fifo_channel_id(struct drm_device *);
921 extern int nv50_fifo_create_context(struct nouveau_channel *);
922 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
923 extern int nv50_fifo_load_context(struct nouveau_channel *);
924 extern int nv50_fifo_unload_context(struct drm_device *);
927 extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
928 extern int nv04_graph_init(struct drm_device *);
929 extern void nv04_graph_takedown(struct drm_device *);
930 extern void nv04_graph_fifo_access(struct drm_device *, bool);
931 extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
932 extern int nv04_graph_create_context(struct nouveau_channel *);
933 extern void nv04_graph_destroy_context(struct nouveau_channel *);
934 extern int nv04_graph_load_context(struct nouveau_channel *);
935 extern int nv04_graph_unload_context(struct drm_device *);
936 extern void nv04_graph_context_switch(struct drm_device *);
939 extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
940 extern int nv10_graph_init(struct drm_device *);
941 extern void nv10_graph_takedown(struct drm_device *);
942 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
943 extern int nv10_graph_create_context(struct nouveau_channel *);
944 extern void nv10_graph_destroy_context(struct nouveau_channel *);
945 extern int nv10_graph_load_context(struct nouveau_channel *);
946 extern int nv10_graph_unload_context(struct drm_device *);
947 extern void nv10_graph_context_switch(struct drm_device *);
950 extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
951 extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
952 extern int nv20_graph_create_context(struct nouveau_channel *);
953 extern void nv20_graph_destroy_context(struct nouveau_channel *);
954 extern int nv20_graph_load_context(struct nouveau_channel *);
955 extern int nv20_graph_unload_context(struct drm_device *);
956 extern int nv20_graph_init(struct drm_device *);
957 extern void nv20_graph_takedown(struct drm_device *);
958 extern int nv30_graph_init(struct drm_device *);
961 extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
962 extern int nv40_graph_init(struct drm_device *);
963 extern void nv40_graph_takedown(struct drm_device *);
964 extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
965 extern int nv40_graph_create_context(struct nouveau_channel *);
966 extern void nv40_graph_destroy_context(struct nouveau_channel *);
967 extern int nv40_graph_load_context(struct nouveau_channel *);
968 extern int nv40_graph_unload_context(struct drm_device *);
969 extern void nv40_grctx_init(struct nouveau_grctx *);
972 extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
973 extern int nv50_graph_init(struct drm_device *);
974 extern void nv50_graph_takedown(struct drm_device *);
975 extern void nv50_graph_fifo_access(struct drm_device *, bool);
976 extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
977 extern int nv50_graph_create_context(struct nouveau_channel *);
978 extern void nv50_graph_destroy_context(struct nouveau_channel *);
979 extern int nv50_graph_load_context(struct nouveau_channel *);
980 extern int nv50_graph_unload_context(struct drm_device *);
981 extern void nv50_graph_context_switch(struct drm_device *);
983 /* nouveau_grctx.c */
984 extern int nouveau_grctx_prog_load(struct drm_device *);
985 extern void nouveau_grctx_vals_load(struct drm_device *,
986 struct nouveau_gpuobj *);
987 extern void nouveau_grctx_fini(struct drm_device *);
990 extern int nv04_instmem_init(struct drm_device *);
991 extern void nv04_instmem_takedown(struct drm_device *);
992 extern int nv04_instmem_suspend(struct drm_device *);
993 extern void nv04_instmem_resume(struct drm_device *);
994 extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
996 extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
997 extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
998 extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
999 extern void nv04_instmem_prepare_access(struct drm_device *, bool write);
1000 extern void nv04_instmem_finish_access(struct drm_device *);
1002 /* nv50_instmem.c */
1003 extern int nv50_instmem_init(struct drm_device *);
1004 extern void nv50_instmem_takedown(struct drm_device *);
1005 extern int nv50_instmem_suspend(struct drm_device *);
1006 extern void nv50_instmem_resume(struct drm_device *);
1007 extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1009 extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1010 extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1011 extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1012 extern void nv50_instmem_prepare_access(struct drm_device *, bool write);
1013 extern void nv50_instmem_finish_access(struct drm_device *);
1016 extern int nv04_mc_init(struct drm_device *);
1017 extern void nv04_mc_takedown(struct drm_device *);
1020 extern int nv40_mc_init(struct drm_device *);
1021 extern void nv40_mc_takedown(struct drm_device *);
1024 extern int nv50_mc_init(struct drm_device *);
1025 extern void nv50_mc_takedown(struct drm_device *);
1028 extern int nv04_timer_init(struct drm_device *);
1029 extern uint64_t nv04_timer_read(struct drm_device *);
1030 extern void nv04_timer_takedown(struct drm_device *);
1032 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1036 extern int nv04_dac_create(struct drm_device *dev, struct dcb_entry *entry);
1037 extern enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder,
1038 struct drm_connector *connector);
1039 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1040 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1043 extern int nv04_dfp_create(struct drm_device *dev, struct dcb_entry *entry);
1044 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1045 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1047 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1048 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1051 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1052 extern int nv04_tv_create(struct drm_device *dev, struct dcb_entry *entry);
1055 extern int nv17_tv_create(struct drm_device *dev, struct dcb_entry *entry);
1056 extern enum drm_connector_status nv17_tv_detect(struct drm_encoder *encoder,
1057 struct drm_connector *connector,
1060 /* nv04_display.c */
1061 extern int nv04_display_create(struct drm_device *);
1062 extern void nv04_display_destroy(struct drm_device *);
1063 extern void nv04_display_restore(struct drm_device *);
1066 extern int nv04_crtc_create(struct drm_device *, int index);
1069 extern struct ttm_bo_driver nouveau_bo_driver;
1070 extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1071 int size, int align, uint32_t flags,
1072 uint32_t tile_mode, uint32_t tile_flags,
1073 bool no_vm, bool mappable, struct nouveau_bo **);
1074 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1075 extern int nouveau_bo_unpin(struct nouveau_bo *);
1076 extern int nouveau_bo_map(struct nouveau_bo *);
1077 extern void nouveau_bo_unmap(struct nouveau_bo *);
1078 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t memtype);
1079 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1080 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1081 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1082 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1084 /* nouveau_fence.c */
1085 struct nouveau_fence;
1086 extern int nouveau_fence_init(struct nouveau_channel *);
1087 extern void nouveau_fence_fini(struct nouveau_channel *);
1088 extern void nouveau_fence_update(struct nouveau_channel *);
1089 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1091 extern int nouveau_fence_emit(struct nouveau_fence *);
1092 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1093 extern bool nouveau_fence_signalled(void *obj, void *arg);
1094 extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1095 extern int nouveau_fence_flush(void *obj, void *arg);
1096 extern void nouveau_fence_unref(void **obj);
1097 extern void *nouveau_fence_ref(void *obj);
1098 extern void nouveau_fence_handler(struct drm_device *dev, int channel);
1101 extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1102 int size, int align, uint32_t flags,
1103 uint32_t tile_mode, uint32_t tile_flags,
1104 bool no_vm, bool mappable, struct nouveau_bo **);
1105 extern int nouveau_gem_object_new(struct drm_gem_object *);
1106 extern void nouveau_gem_object_del(struct drm_gem_object *);
1107 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1109 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1111 extern int nouveau_gem_ioctl_pushbuf_call(struct drm_device *, void *,
1113 extern int nouveau_gem_ioctl_pushbuf_call2(struct drm_device *, void *,
1115 extern int nouveau_gem_ioctl_pin(struct drm_device *, void *,
1117 extern int nouveau_gem_ioctl_unpin(struct drm_device *, void *,
1119 extern int nouveau_gem_ioctl_tile(struct drm_device *, void *,
1121 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1123 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1125 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1129 int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1130 int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1132 #ifndef ioread32_native
1134 #define ioread16_native ioread16be
1135 #define iowrite16_native iowrite16be
1136 #define ioread32_native ioread32be
1137 #define iowrite32_native iowrite32be
1138 #else /* def __BIG_ENDIAN */
1139 #define ioread16_native ioread16
1140 #define iowrite16_native iowrite16
1141 #define ioread32_native ioread32
1142 #define iowrite32_native iowrite32
1143 #endif /* def __BIG_ENDIAN else */
1144 #endif /* !ioread32_native */
1146 /* channel control reg access */
1147 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1149 return ioread32_native(chan->user + reg);
1152 static inline void nvchan_wr32(struct nouveau_channel *chan,
1153 unsigned reg, u32 val)
1155 iowrite32_native(val, chan->user + reg);
1158 /* register access */
1159 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1161 struct drm_nouveau_private *dev_priv = dev->dev_private;
1162 return ioread32_native(dev_priv->mmio + reg);
1165 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1167 struct drm_nouveau_private *dev_priv = dev->dev_private;
1168 iowrite32_native(val, dev_priv->mmio + reg);
1171 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1173 struct drm_nouveau_private *dev_priv = dev->dev_private;
1174 return ioread8(dev_priv->mmio + reg);
1177 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1179 struct drm_nouveau_private *dev_priv = dev->dev_private;
1180 iowrite8(val, dev_priv->mmio + reg);
1183 #define nv_wait(reg, mask, val) \
1184 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1187 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1189 struct drm_nouveau_private *dev_priv = dev->dev_private;
1190 return ioread32_native(dev_priv->ramin + offset);
1193 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1195 struct drm_nouveau_private *dev_priv = dev->dev_private;
1196 iowrite32_native(val, dev_priv->ramin + offset);
1200 static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1203 return nv_ri32(dev, obj->im_pramin->start + index * 4);
1206 static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1207 unsigned index, u32 val)
1209 nv_wi32(dev, obj->im_pramin->start + index * 4, val);
1214 * Argument d is (struct drm_device *).
1216 #define NV_PRINTK(level, d, fmt, arg...) \
1217 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1218 pci_name(d->pdev), ##arg)
1219 #ifndef NV_DEBUG_NOTRACE
1220 #define NV_DEBUG(d, fmt, arg...) do { \
1221 if (drm_debug & DRM_UT_DRIVER) { \
1222 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1226 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1227 if (drm_debug & DRM_UT_KMS) { \
1228 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1233 #define NV_DEBUG(d, fmt, arg...) do { \
1234 if (drm_debug & DRM_UT_DRIVER) \
1235 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1237 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1238 if (drm_debug & DRM_UT_KMS) \
1239 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1242 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1243 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1244 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1245 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1246 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1248 /* nouveau_reg_debug bitmask */
1250 NOUVEAU_REG_DEBUG_MC = 0x1,
1251 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1252 NOUVEAU_REG_DEBUG_FB = 0x4,
1253 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1254 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1255 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1256 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1257 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1258 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1259 NOUVEAU_REG_DEBUG_EVO = 0x200,
1262 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1263 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1264 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1268 nv_two_heads(struct drm_device *dev)
1270 struct drm_nouveau_private *dev_priv = dev->dev_private;
1271 const int impl = dev->pci_device & 0x0ff0;
1273 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1274 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1281 nv_gf4_disp_arch(struct drm_device *dev)
1283 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1287 nv_two_reg_pll(struct drm_device *dev)
1289 struct drm_nouveau_private *dev_priv = dev->dev_private;
1290 const int impl = dev->pci_device & 0x0ff0;
1292 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1297 #define NV50_NVSW 0x0000506e
1298 #define NV50_NVSW_DMA_SEMAPHORE 0x00000060
1299 #define NV50_NVSW_SEMAPHORE_OFFSET 0x00000064
1300 #define NV50_NVSW_SEMAPHORE_ACQUIRE 0x00000068
1301 #define NV50_NVSW_SEMAPHORE_RELEASE 0x0000006c
1302 #define NV50_NVSW_DMA_VBLSEM 0x0000018c
1303 #define NV50_NVSW_VBLSEM_OFFSET 0x00000400
1304 #define NV50_NVSW_VBLSEM_RELEASE_VALUE 0x00000404
1305 #define NV50_NVSW_VBLSEM_RELEASE 0x00000408
1307 #endif /* __NOUVEAU_DRV_H__ */