2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
48 struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
54 #include "nouveau_drm.h"
55 #include "nouveau_reg.h"
56 #include "nouveau_bios.h"
59 #define MAX_NUM_DCB_ENTRIES 16
61 #define NOUVEAU_MAX_CHANNEL_NR 128
62 #define NOUVEAU_MAX_TILE_NR 15
64 #define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65 #define NV50_VM_BLOCK (512*1024*1024ULL)
66 #define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
68 struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
79 u32 busy_placements[3];
80 struct ttm_bo_kmap_obj kmap;
81 struct list_head head;
83 /* protected by ttm_bo_reserve() */
84 struct drm_file *reserved_by;
85 struct list_head entry;
89 struct nouveau_channel *channel;
96 struct nouveau_tile_reg *tile;
98 struct drm_gem_object *gem;
99 struct drm_file *cpu_filp;
103 static inline struct nouveau_bo *
104 nouveau_bo(struct ttm_buffer_object *bo)
106 return container_of(bo, struct nouveau_bo, bo);
109 static inline struct nouveau_bo *
110 nouveau_gem_object(struct drm_gem_object *gem)
112 return gem ? gem->driver_private : NULL;
115 /* TODO: submit equivalent to TTM generic API upstream? */
116 static inline void __iomem *
117 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
120 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
121 &nvbo->kmap, &is_iomem);
122 WARN_ON_ONCE(ioptr && !is_iomem);
127 struct mem_block *next;
128 struct mem_block *prev;
131 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
135 NV_NFORCE = 0x10000000,
136 NV_NFORCE2 = 0x20000000
139 #define NVOBJ_ENGINE_SW 0
140 #define NVOBJ_ENGINE_GR 1
141 #define NVOBJ_ENGINE_DISPLAY 2
142 #define NVOBJ_ENGINE_INT 0xdeadbeef
144 #define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
145 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
146 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
147 #define NVOBJ_FLAG_FAKE (1 << 3)
148 struct nouveau_gpuobj {
149 struct list_head list;
151 struct nouveau_channel *im_channel;
152 struct mem_block *im_pramin;
153 struct nouveau_bo *im_backing;
154 uint32_t im_backing_start;
155 uint32_t *im_backing_suspend;
164 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
168 struct nouveau_gpuobj_ref {
169 struct list_head list;
171 struct nouveau_gpuobj *gpuobj;
174 struct nouveau_channel *channel;
178 struct nouveau_channel {
179 struct drm_device *dev;
182 /* owner of this fifo */
183 struct drm_file *file_priv;
184 /* mapping of the fifo itself */
185 struct drm_local_map *map;
187 /* mapping of the regs controling the fifo */
194 /* lock protects the pending list only */
196 struct list_head pending;
198 uint32_t sequence_ack;
199 uint32_t last_sequence_irq;
202 /* DMA push buffer */
203 struct nouveau_gpuobj_ref *pushbuf;
204 struct nouveau_bo *pushbuf_bo;
205 uint32_t pushbuf_base;
207 /* Notifier memory */
208 struct nouveau_bo *notifier_bo;
209 struct mem_block *notifier_heap;
212 struct nouveau_gpuobj_ref *ramfc;
213 struct nouveau_gpuobj_ref *cache;
216 /* XXX may be merge 2 pointers as private data ??? */
217 struct nouveau_gpuobj_ref *ramin_grctx;
221 struct nouveau_gpuobj *vm_pd;
222 struct nouveau_gpuobj_ref *vm_gart_pt;
223 struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR];
226 struct nouveau_gpuobj_ref *ramin; /* Private instmem */
227 struct mem_block *ramin_heap; /* Private PRAMIN heap */
228 struct nouveau_gpuobj_ref *ramht; /* Hash table */
229 struct list_head ramht_refs; /* Objects referenced by RAMHT */
231 /* GPU object info for stuff used in-kernel (mm_enabled) */
233 uint32_t vram_handle;
234 uint32_t gart_handle;
237 /* Push buffer state (only for drm's channel on !mm_enabled) */
243 /* access via pushbuf_bo */
251 uint32_t sw_subchannel[8];
254 struct nouveau_gpuobj *vblsem;
255 uint32_t vblsem_offset;
256 uint32_t vblsem_rval;
257 struct list_head vbl_wait;
263 struct drm_info_list info;
267 struct nouveau_instmem_engine {
270 int (*init)(struct drm_device *dev);
271 void (*takedown)(struct drm_device *dev);
272 int (*suspend)(struct drm_device *dev);
273 void (*resume)(struct drm_device *dev);
275 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
277 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
278 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
279 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
280 void (*prepare_access)(struct drm_device *, bool write);
281 void (*finish_access)(struct drm_device *);
284 struct nouveau_mc_engine {
285 int (*init)(struct drm_device *dev);
286 void (*takedown)(struct drm_device *dev);
289 struct nouveau_timer_engine {
290 int (*init)(struct drm_device *dev);
291 void (*takedown)(struct drm_device *dev);
292 uint64_t (*read)(struct drm_device *dev);
295 struct nouveau_fb_engine {
298 int (*init)(struct drm_device *dev);
299 void (*takedown)(struct drm_device *dev);
301 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
302 uint32_t size, uint32_t pitch);
305 struct nouveau_fifo_engine {
310 int (*init)(struct drm_device *);
311 void (*takedown)(struct drm_device *);
313 void (*disable)(struct drm_device *);
314 void (*enable)(struct drm_device *);
315 bool (*reassign)(struct drm_device *, bool enable);
316 bool (*cache_flush)(struct drm_device *dev);
317 bool (*cache_pull)(struct drm_device *dev, bool enable);
319 int (*channel_id)(struct drm_device *);
321 int (*create_context)(struct nouveau_channel *);
322 void (*destroy_context)(struct nouveau_channel *);
323 int (*load_context)(struct nouveau_channel *);
324 int (*unload_context)(struct drm_device *);
327 struct nouveau_pgraph_object_method {
329 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
333 struct nouveau_pgraph_object_class {
336 struct nouveau_pgraph_object_method *methods;
339 struct nouveau_pgraph_engine {
340 struct nouveau_pgraph_object_class *grclass;
346 int (*init)(struct drm_device *);
347 void (*takedown)(struct drm_device *);
349 void (*fifo_access)(struct drm_device *, bool);
351 struct nouveau_channel *(*channel)(struct drm_device *);
352 int (*create_context)(struct nouveau_channel *);
353 void (*destroy_context)(struct nouveau_channel *);
354 int (*load_context)(struct nouveau_channel *);
355 int (*unload_context)(struct drm_device *);
357 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
358 uint32_t size, uint32_t pitch);
361 struct nouveau_engine {
362 struct nouveau_instmem_engine instmem;
363 struct nouveau_mc_engine mc;
364 struct nouveau_timer_engine timer;
365 struct nouveau_fb_engine fb;
366 struct nouveau_pgraph_engine graph;
367 struct nouveau_fifo_engine fifo;
370 struct nouveau_pll_vals {
374 uint8_t N1, M1, N2, M2;
376 uint8_t M1, N1, M2, N2;
381 } __attribute__((packed));
388 enum nv04_fp_display_regs {
398 struct nv04_crtc_reg {
399 unsigned char MiscOutReg; /* */
402 uint8_t Sequencer[5];
404 uint8_t Attribute[21];
405 unsigned char DAC[768]; /* Internal Colorlookuptable */
415 uint32_t crtc_eng_ctrl;
418 uint32_t nv10_cursync;
419 struct nouveau_pll_vals pllvals;
420 uint32_t ramdac_gen_ctrl;
426 uint32_t tv_vsync_delay;
429 uint32_t tv_hsync_delay;
430 uint32_t tv_hsync_delay2;
431 uint32_t fp_horiz_regs[7];
432 uint32_t fp_vert_regs[7];
435 uint32_t dither_regs[6];
439 uint32_t fp_margin_color;
444 uint32_t ctv_regs[38];
447 struct nv04_output_reg {
452 struct nv04_mode_state {
480 uint32_t cursorConfig;
489 struct nv04_crtc_reg crtc_reg[2];
492 enum nouveau_card_type {
501 struct drm_nouveau_private {
502 struct drm_device *dev;
504 NOUVEAU_CARD_INIT_DOWN,
505 NOUVEAU_CARD_INIT_DONE,
506 NOUVEAU_CARD_INIT_FAILED
509 /* the card type, takes NV_* as values */
510 enum nouveau_card_type card_type;
511 /* exact chipset, derived from NV_PMC_BOOT_0 */
519 struct nouveau_bo *vga_ram;
521 struct workqueue_struct *wq;
522 struct work_struct irq_work;
524 struct list_head vbl_waiting;
527 struct ttm_global_reference mem_global_ref;
528 struct ttm_bo_global_ref bo_global_ref;
529 struct ttm_bo_device bdev;
530 spinlock_t bo_list_lock;
531 struct list_head bo_list;
532 atomic_t validate_sequence;
535 struct fb_info *fbdev_info;
537 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
539 struct nouveau_engine engine;
540 struct nouveau_channel *channel;
542 /* For PFIFO and PGRAPH. */
543 spinlock_t context_switch_lock;
545 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
546 struct nouveau_gpuobj *ramht;
547 uint32_t ramin_rsvd_vram;
548 uint32_t ramht_offset;
551 uint32_t ramfc_offset;
553 uint32_t ramro_offset;
556 /* base physical addresses */
558 uint64_t fb_available_size;
559 uint64_t fb_mappable_pages;
560 uint64_t fb_aper_free;
564 NOUVEAU_GART_NONE = 0,
572 struct nouveau_gpuobj *sg_ctxdma;
573 struct page *sg_dummy_page;
574 dma_addr_t sg_dummy_bus;
577 /* nv10-nv40 tiling regions */
579 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
583 /* G8x/G9x virtual address space */
584 uint64_t vm_gart_base;
585 uint64_t vm_gart_size;
586 uint64_t vm_vram_base;
587 uint64_t vm_vram_size;
589 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
591 uint64_t vram_sys_base;
593 /* the mtrr covering the FB */
596 struct mem_block *ramin_heap;
598 /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
599 uint32_t ctx_table_size;
600 struct nouveau_gpuobj_ref *ctx_table;
602 struct list_head gpuobj_list;
606 struct nv04_mode_state mode_reg;
607 struct nv04_mode_state saved_reg;
608 uint32_t saved_vga_font[4][16384];
610 uint32_t dac_users[4];
612 struct nouveau_suspend_resume {
613 uint32_t *ramin_copy;
616 struct backlight_device *backlight;
618 struct nouveau_channel *evo;
621 struct dentry *channel_root;
625 static inline struct drm_nouveau_private *
626 nouveau_bdev(struct ttm_bo_device *bd)
628 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
632 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
634 struct nouveau_bo *prev;
640 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
642 struct ttm_buffer_object *bo = &prev->bo;
650 #define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \
651 struct drm_nouveau_private *nv = dev->dev_private; \
652 if (nv->init_state != NOUVEAU_CARD_INIT_DONE) { \
653 NV_ERROR(dev, "called without init\n"); \
658 #define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
659 struct drm_nouveau_private *nv = dev->dev_private; \
660 if (!nouveau_channel_owner(dev, (cl), (id))) { \
661 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
662 DRM_CURRENTPID, (id)); \
665 (ch) = nv->fifos[(id)]; \
669 extern int nouveau_noagp;
670 extern int nouveau_duallink;
671 extern int nouveau_uscript_lvds;
672 extern int nouveau_uscript_tmds;
673 extern int nouveau_vram_pushbuf;
674 extern int nouveau_vram_notify;
675 extern int nouveau_fbpercrtc;
676 extern int nouveau_tv_disable;
677 extern char *nouveau_tv_norm;
678 extern int nouveau_reg_debug;
679 extern char *nouveau_vbios;
680 extern int nouveau_ctxfw;
681 extern int nouveau_ignorelid;
682 extern int nouveau_nofbaccel;
683 extern int nouveau_noaccel;
684 extern int nouveau_override_conntype;
686 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
687 extern int nouveau_pci_resume(struct pci_dev *pdev);
689 /* nouveau_state.c */
690 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
691 extern int nouveau_load(struct drm_device *, unsigned long flags);
692 extern int nouveau_firstopen(struct drm_device *);
693 extern void nouveau_lastclose(struct drm_device *);
694 extern int nouveau_unload(struct drm_device *);
695 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
697 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
699 extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
700 uint32_t reg, uint32_t mask, uint32_t val);
701 extern bool nouveau_wait_for_idle(struct drm_device *);
702 extern int nouveau_card_init(struct drm_device *);
705 extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start,
707 extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *,
708 uint64_t size, int align2,
709 struct drm_file *, int tail);
710 extern void nouveau_mem_takedown(struct mem_block **heap);
711 extern void nouveau_mem_free_block(struct mem_block *);
712 extern uint64_t nouveau_mem_fb_amount(struct drm_device *);
713 extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
714 extern int nouveau_mem_init(struct drm_device *);
715 extern int nouveau_mem_init_agp(struct drm_device *);
716 extern void nouveau_mem_close(struct drm_device *);
717 extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
721 extern void nv10_mem_expire_tiling(struct drm_device *dev,
722 struct nouveau_tile_reg *tile,
723 struct nouveau_fence *fence);
724 extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
725 uint32_t size, uint32_t flags,
727 extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
730 /* nouveau_notifier.c */
731 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
732 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
733 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
734 int cout, uint32_t *offset);
735 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
736 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
738 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
741 /* nouveau_channel.c */
742 extern struct drm_ioctl_desc nouveau_ioctls[];
743 extern int nouveau_max_ioctl;
744 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
745 extern int nouveau_channel_owner(struct drm_device *, struct drm_file *,
747 extern int nouveau_channel_alloc(struct drm_device *dev,
748 struct nouveau_channel **chan,
749 struct drm_file *file_priv,
750 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
751 extern void nouveau_channel_free(struct nouveau_channel *);
753 /* nouveau_object.c */
754 extern int nouveau_gpuobj_early_init(struct drm_device *);
755 extern int nouveau_gpuobj_init(struct drm_device *);
756 extern void nouveau_gpuobj_takedown(struct drm_device *);
757 extern void nouveau_gpuobj_late_takedown(struct drm_device *);
758 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
759 extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
760 extern void nouveau_gpuobj_resume(struct drm_device *dev);
761 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
762 uint32_t vram_h, uint32_t tt_h);
763 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
764 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
765 uint32_t size, int align, uint32_t flags,
766 struct nouveau_gpuobj **);
767 extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
768 extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
769 uint32_t handle, struct nouveau_gpuobj *,
770 struct nouveau_gpuobj_ref **);
771 extern int nouveau_gpuobj_ref_del(struct drm_device *,
772 struct nouveau_gpuobj_ref **);
773 extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle,
774 struct nouveau_gpuobj_ref **ref_ret);
775 extern int nouveau_gpuobj_new_ref(struct drm_device *,
776 struct nouveau_channel *alloc_chan,
777 struct nouveau_channel *ref_chan,
778 uint32_t handle, uint32_t size, int align,
779 uint32_t flags, struct nouveau_gpuobj_ref **);
780 extern int nouveau_gpuobj_new_fake(struct drm_device *,
781 uint32_t p_offset, uint32_t b_offset,
782 uint32_t size, uint32_t flags,
783 struct nouveau_gpuobj **,
784 struct nouveau_gpuobj_ref**);
785 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
786 uint64_t offset, uint64_t size, int access,
787 int target, struct nouveau_gpuobj **);
788 extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
789 uint64_t offset, uint64_t size,
790 int access, struct nouveau_gpuobj **,
792 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
793 struct nouveau_gpuobj **);
794 extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
795 struct nouveau_gpuobj **);
796 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
798 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
802 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
803 extern void nouveau_irq_preinstall(struct drm_device *);
804 extern int nouveau_irq_postinstall(struct drm_device *);
805 extern void nouveau_irq_uninstall(struct drm_device *);
807 /* nouveau_sgdma.c */
808 extern int nouveau_sgdma_init(struct drm_device *);
809 extern void nouveau_sgdma_takedown(struct drm_device *);
810 extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
812 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
814 /* nouveau_debugfs.c */
815 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
816 extern int nouveau_debugfs_init(struct drm_minor *);
817 extern void nouveau_debugfs_takedown(struct drm_minor *);
818 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
819 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
822 nouveau_debugfs_init(struct drm_minor *minor)
827 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
832 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
838 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
844 extern void nouveau_dma_pre_init(struct nouveau_channel *);
845 extern int nouveau_dma_init(struct nouveau_channel *);
846 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
849 #if defined(CONFIG_ACPI)
850 void nouveau_register_dsm_handler(void);
851 void nouveau_unregister_dsm_handler(void);
853 static inline void nouveau_register_dsm_handler(void) {}
854 static inline void nouveau_unregister_dsm_handler(void) {}
857 /* nouveau_backlight.c */
858 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
859 extern int nouveau_backlight_init(struct drm_device *);
860 extern void nouveau_backlight_exit(struct drm_device *);
862 static inline int nouveau_backlight_init(struct drm_device *dev)
867 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
871 extern int nouveau_bios_init(struct drm_device *);
872 extern void nouveau_bios_takedown(struct drm_device *dev);
873 extern int nouveau_run_vbios_init(struct drm_device *);
874 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
876 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
878 extern struct dcb_connector_table_entry *
879 nouveau_bios_connector_entry(struct drm_device *, int index);
880 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
882 extern int nouveau_bios_run_display_table(struct drm_device *,
884 uint32_t script, int pxclk);
885 extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
887 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
888 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
889 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
890 bool *dl, bool *if_is_24bit);
891 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
892 int head, int pxclk);
893 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
894 enum LVDS_script, int pxclk);
897 int nouveau_ttm_global_init(struct drm_nouveau_private *);
898 void nouveau_ttm_global_release(struct drm_nouveau_private *);
899 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
902 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
903 uint8_t *data, int data_nr);
904 bool nouveau_dp_detect(struct drm_encoder *);
905 bool nouveau_dp_link_train(struct drm_encoder *);
908 extern int nv04_fb_init(struct drm_device *);
909 extern void nv04_fb_takedown(struct drm_device *);
912 extern int nv10_fb_init(struct drm_device *);
913 extern void nv10_fb_takedown(struct drm_device *);
914 extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
918 extern int nv40_fb_init(struct drm_device *);
919 extern void nv40_fb_takedown(struct drm_device *);
920 extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
924 extern int nv50_fb_init(struct drm_device *);
925 extern void nv50_fb_takedown(struct drm_device *);
928 extern int nv04_fifo_init(struct drm_device *);
929 extern void nv04_fifo_disable(struct drm_device *);
930 extern void nv04_fifo_enable(struct drm_device *);
931 extern bool nv04_fifo_reassign(struct drm_device *, bool);
932 extern bool nv04_fifo_cache_flush(struct drm_device *);
933 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
934 extern int nv04_fifo_channel_id(struct drm_device *);
935 extern int nv04_fifo_create_context(struct nouveau_channel *);
936 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
937 extern int nv04_fifo_load_context(struct nouveau_channel *);
938 extern int nv04_fifo_unload_context(struct drm_device *);
941 extern int nv10_fifo_init(struct drm_device *);
942 extern int nv10_fifo_channel_id(struct drm_device *);
943 extern int nv10_fifo_create_context(struct nouveau_channel *);
944 extern void nv10_fifo_destroy_context(struct nouveau_channel *);
945 extern int nv10_fifo_load_context(struct nouveau_channel *);
946 extern int nv10_fifo_unload_context(struct drm_device *);
949 extern int nv40_fifo_init(struct drm_device *);
950 extern int nv40_fifo_create_context(struct nouveau_channel *);
951 extern void nv40_fifo_destroy_context(struct nouveau_channel *);
952 extern int nv40_fifo_load_context(struct nouveau_channel *);
953 extern int nv40_fifo_unload_context(struct drm_device *);
956 extern int nv50_fifo_init(struct drm_device *);
957 extern void nv50_fifo_takedown(struct drm_device *);
958 extern int nv50_fifo_channel_id(struct drm_device *);
959 extern int nv50_fifo_create_context(struct nouveau_channel *);
960 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
961 extern int nv50_fifo_load_context(struct nouveau_channel *);
962 extern int nv50_fifo_unload_context(struct drm_device *);
965 extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
966 extern int nv04_graph_init(struct drm_device *);
967 extern void nv04_graph_takedown(struct drm_device *);
968 extern void nv04_graph_fifo_access(struct drm_device *, bool);
969 extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
970 extern int nv04_graph_create_context(struct nouveau_channel *);
971 extern void nv04_graph_destroy_context(struct nouveau_channel *);
972 extern int nv04_graph_load_context(struct nouveau_channel *);
973 extern int nv04_graph_unload_context(struct drm_device *);
974 extern void nv04_graph_context_switch(struct drm_device *);
977 extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
978 extern int nv10_graph_init(struct drm_device *);
979 extern void nv10_graph_takedown(struct drm_device *);
980 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
981 extern int nv10_graph_create_context(struct nouveau_channel *);
982 extern void nv10_graph_destroy_context(struct nouveau_channel *);
983 extern int nv10_graph_load_context(struct nouveau_channel *);
984 extern int nv10_graph_unload_context(struct drm_device *);
985 extern void nv10_graph_context_switch(struct drm_device *);
986 extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
990 extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
991 extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
992 extern int nv20_graph_create_context(struct nouveau_channel *);
993 extern void nv20_graph_destroy_context(struct nouveau_channel *);
994 extern int nv20_graph_load_context(struct nouveau_channel *);
995 extern int nv20_graph_unload_context(struct drm_device *);
996 extern int nv20_graph_init(struct drm_device *);
997 extern void nv20_graph_takedown(struct drm_device *);
998 extern int nv30_graph_init(struct drm_device *);
999 extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1000 uint32_t, uint32_t);
1003 extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
1004 extern int nv40_graph_init(struct drm_device *);
1005 extern void nv40_graph_takedown(struct drm_device *);
1006 extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1007 extern int nv40_graph_create_context(struct nouveau_channel *);
1008 extern void nv40_graph_destroy_context(struct nouveau_channel *);
1009 extern int nv40_graph_load_context(struct nouveau_channel *);
1010 extern int nv40_graph_unload_context(struct drm_device *);
1011 extern void nv40_grctx_init(struct nouveau_grctx *);
1012 extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1013 uint32_t, uint32_t);
1016 extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
1017 extern int nv50_graph_init(struct drm_device *);
1018 extern void nv50_graph_takedown(struct drm_device *);
1019 extern void nv50_graph_fifo_access(struct drm_device *, bool);
1020 extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1021 extern int nv50_graph_create_context(struct nouveau_channel *);
1022 extern void nv50_graph_destroy_context(struct nouveau_channel *);
1023 extern int nv50_graph_load_context(struct nouveau_channel *);
1024 extern int nv50_graph_unload_context(struct drm_device *);
1025 extern void nv50_graph_context_switch(struct drm_device *);
1026 extern int nv50_grctx_init(struct nouveau_grctx *);
1028 /* nouveau_grctx.c */
1029 extern int nouveau_grctx_prog_load(struct drm_device *);
1030 extern void nouveau_grctx_vals_load(struct drm_device *,
1031 struct nouveau_gpuobj *);
1032 extern void nouveau_grctx_fini(struct drm_device *);
1034 /* nv04_instmem.c */
1035 extern int nv04_instmem_init(struct drm_device *);
1036 extern void nv04_instmem_takedown(struct drm_device *);
1037 extern int nv04_instmem_suspend(struct drm_device *);
1038 extern void nv04_instmem_resume(struct drm_device *);
1039 extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1041 extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1042 extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1043 extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1044 extern void nv04_instmem_prepare_access(struct drm_device *, bool write);
1045 extern void nv04_instmem_finish_access(struct drm_device *);
1047 /* nv50_instmem.c */
1048 extern int nv50_instmem_init(struct drm_device *);
1049 extern void nv50_instmem_takedown(struct drm_device *);
1050 extern int nv50_instmem_suspend(struct drm_device *);
1051 extern void nv50_instmem_resume(struct drm_device *);
1052 extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1054 extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1055 extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1056 extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1057 extern void nv50_instmem_prepare_access(struct drm_device *, bool write);
1058 extern void nv50_instmem_finish_access(struct drm_device *);
1061 extern int nv04_mc_init(struct drm_device *);
1062 extern void nv04_mc_takedown(struct drm_device *);
1065 extern int nv40_mc_init(struct drm_device *);
1066 extern void nv40_mc_takedown(struct drm_device *);
1069 extern int nv50_mc_init(struct drm_device *);
1070 extern void nv50_mc_takedown(struct drm_device *);
1073 extern int nv04_timer_init(struct drm_device *);
1074 extern uint64_t nv04_timer_read(struct drm_device *);
1075 extern void nv04_timer_takedown(struct drm_device *);
1077 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1081 extern int nv04_dac_create(struct drm_device *dev, struct dcb_entry *entry);
1082 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1083 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1084 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1087 extern int nv04_dfp_create(struct drm_device *dev, struct dcb_entry *entry);
1088 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1089 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1091 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1092 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1095 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1096 extern int nv04_tv_create(struct drm_device *dev, struct dcb_entry *entry);
1099 extern int nv17_tv_create(struct drm_device *dev, struct dcb_entry *entry);
1101 /* nv04_display.c */
1102 extern int nv04_display_create(struct drm_device *);
1103 extern void nv04_display_destroy(struct drm_device *);
1104 extern void nv04_display_restore(struct drm_device *);
1107 extern int nv04_crtc_create(struct drm_device *, int index);
1110 extern struct ttm_bo_driver nouveau_bo_driver;
1111 extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1112 int size, int align, uint32_t flags,
1113 uint32_t tile_mode, uint32_t tile_flags,
1114 bool no_vm, bool mappable, struct nouveau_bo **);
1115 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1116 extern int nouveau_bo_unpin(struct nouveau_bo *);
1117 extern int nouveau_bo_map(struct nouveau_bo *);
1118 extern void nouveau_bo_unmap(struct nouveau_bo *);
1119 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1121 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1122 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1123 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1124 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1126 /* nouveau_fence.c */
1127 struct nouveau_fence;
1128 extern int nouveau_fence_init(struct nouveau_channel *);
1129 extern void nouveau_fence_fini(struct nouveau_channel *);
1130 extern void nouveau_fence_update(struct nouveau_channel *);
1131 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1133 extern int nouveau_fence_emit(struct nouveau_fence *);
1134 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1135 extern bool nouveau_fence_signalled(void *obj, void *arg);
1136 extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1137 extern int nouveau_fence_flush(void *obj, void *arg);
1138 extern void nouveau_fence_unref(void **obj);
1139 extern void *nouveau_fence_ref(void *obj);
1140 extern void nouveau_fence_handler(struct drm_device *dev, int channel);
1143 extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1144 int size, int align, uint32_t flags,
1145 uint32_t tile_mode, uint32_t tile_flags,
1146 bool no_vm, bool mappable, struct nouveau_bo **);
1147 extern int nouveau_gem_object_new(struct drm_gem_object *);
1148 extern void nouveau_gem_object_del(struct drm_gem_object *);
1149 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1151 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1153 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1155 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1157 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1161 int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1162 int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1164 #ifndef ioread32_native
1166 #define ioread16_native ioread16be
1167 #define iowrite16_native iowrite16be
1168 #define ioread32_native ioread32be
1169 #define iowrite32_native iowrite32be
1170 #else /* def __BIG_ENDIAN */
1171 #define ioread16_native ioread16
1172 #define iowrite16_native iowrite16
1173 #define ioread32_native ioread32
1174 #define iowrite32_native iowrite32
1175 #endif /* def __BIG_ENDIAN else */
1176 #endif /* !ioread32_native */
1178 /* channel control reg access */
1179 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1181 return ioread32_native(chan->user + reg);
1184 static inline void nvchan_wr32(struct nouveau_channel *chan,
1185 unsigned reg, u32 val)
1187 iowrite32_native(val, chan->user + reg);
1190 /* register access */
1191 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1193 struct drm_nouveau_private *dev_priv = dev->dev_private;
1194 return ioread32_native(dev_priv->mmio + reg);
1197 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1199 struct drm_nouveau_private *dev_priv = dev->dev_private;
1200 iowrite32_native(val, dev_priv->mmio + reg);
1203 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1205 struct drm_nouveau_private *dev_priv = dev->dev_private;
1206 return ioread8(dev_priv->mmio + reg);
1209 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1211 struct drm_nouveau_private *dev_priv = dev->dev_private;
1212 iowrite8(val, dev_priv->mmio + reg);
1215 #define nv_wait(reg, mask, val) \
1216 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1219 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1221 struct drm_nouveau_private *dev_priv = dev->dev_private;
1222 return ioread32_native(dev_priv->ramin + offset);
1225 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1227 struct drm_nouveau_private *dev_priv = dev->dev_private;
1228 iowrite32_native(val, dev_priv->ramin + offset);
1232 static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1235 return nv_ri32(dev, obj->im_pramin->start + index * 4);
1238 static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1239 unsigned index, u32 val)
1241 nv_wi32(dev, obj->im_pramin->start + index * 4, val);
1246 * Argument d is (struct drm_device *).
1248 #define NV_PRINTK(level, d, fmt, arg...) \
1249 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1250 pci_name(d->pdev), ##arg)
1251 #ifndef NV_DEBUG_NOTRACE
1252 #define NV_DEBUG(d, fmt, arg...) do { \
1253 if (drm_debug & DRM_UT_DRIVER) { \
1254 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1258 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1259 if (drm_debug & DRM_UT_KMS) { \
1260 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1265 #define NV_DEBUG(d, fmt, arg...) do { \
1266 if (drm_debug & DRM_UT_DRIVER) \
1267 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1269 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1270 if (drm_debug & DRM_UT_KMS) \
1271 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1274 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1275 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1276 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1277 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1278 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1280 /* nouveau_reg_debug bitmask */
1282 NOUVEAU_REG_DEBUG_MC = 0x1,
1283 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1284 NOUVEAU_REG_DEBUG_FB = 0x4,
1285 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1286 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1287 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1288 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1289 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1290 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1291 NOUVEAU_REG_DEBUG_EVO = 0x200,
1294 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1295 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1296 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1300 nv_two_heads(struct drm_device *dev)
1302 struct drm_nouveau_private *dev_priv = dev->dev_private;
1303 const int impl = dev->pci_device & 0x0ff0;
1305 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1306 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1313 nv_gf4_disp_arch(struct drm_device *dev)
1315 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1319 nv_two_reg_pll(struct drm_device *dev)
1321 struct drm_nouveau_private *dev_priv = dev->dev_private;
1322 const int impl = dev->pci_device & 0x0ff0;
1324 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1329 #define NV_SW 0x0000506e
1330 #define NV_SW_DMA_SEMAPHORE 0x00000060
1331 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1332 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1333 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1334 #define NV_SW_DMA_VBLSEM 0x0000018c
1335 #define NV_SW_VBLSEM_OFFSET 0x00000400
1336 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1337 #define NV_SW_VBLSEM_RELEASE 0x00000408
1339 #endif /* __NOUVEAU_DRV_H__ */