2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
48 struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
54 #include "nouveau_drm.h"
55 #include "nouveau_reg.h"
56 #include "nouveau_bios.h"
59 #define MAX_NUM_DCB_ENTRIES 16
61 #define NOUVEAU_MAX_CHANNEL_NR 128
62 #define NOUVEAU_MAX_TILE_NR 15
64 #define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65 #define NV50_VM_BLOCK (512*1024*1024ULL)
66 #define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
68 struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
79 u32 busy_placements[3];
80 struct ttm_bo_kmap_obj kmap;
81 struct list_head head;
83 /* protected by ttm_bo_reserve() */
84 struct drm_file *reserved_by;
85 struct list_head entry;
89 struct nouveau_channel *channel;
96 struct nouveau_tile_reg *tile;
98 struct drm_gem_object *gem;
99 struct drm_file *cpu_filp;
103 static inline struct nouveau_bo *
104 nouveau_bo(struct ttm_buffer_object *bo)
106 return container_of(bo, struct nouveau_bo, bo);
109 static inline struct nouveau_bo *
110 nouveau_gem_object(struct drm_gem_object *gem)
112 return gem ? gem->driver_private : NULL;
115 /* TODO: submit equivalent to TTM generic API upstream? */
116 static inline void __iomem *
117 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
120 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
121 &nvbo->kmap, &is_iomem);
122 WARN_ON_ONCE(ioptr && !is_iomem);
127 NV_NFORCE = 0x10000000,
128 NV_NFORCE2 = 0x20000000
131 #define NVOBJ_ENGINE_SW 0
132 #define NVOBJ_ENGINE_GR 1
133 #define NVOBJ_ENGINE_DISPLAY 2
134 #define NVOBJ_ENGINE_INT 0xdeadbeef
136 #define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
137 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
138 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
139 #define NVOBJ_FLAG_FAKE (1 << 3)
140 struct nouveau_gpuobj {
141 struct list_head list;
143 struct nouveau_channel *im_channel;
144 struct drm_mm_node *im_pramin;
145 struct nouveau_bo *im_backing;
146 uint32_t im_backing_start;
147 uint32_t *im_backing_suspend;
156 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
160 struct nouveau_gpuobj_ref {
161 struct list_head list;
163 struct nouveau_gpuobj *gpuobj;
166 struct nouveau_channel *channel;
170 struct nouveau_channel {
171 struct drm_device *dev;
174 /* owner of this fifo */
175 struct drm_file *file_priv;
176 /* mapping of the fifo itself */
177 struct drm_local_map *map;
179 /* mapping of the regs controling the fifo */
186 /* lock protects the pending list only */
188 struct list_head pending;
190 uint32_t sequence_ack;
191 atomic_t last_sequence_irq;
194 /* DMA push buffer */
195 struct nouveau_gpuobj_ref *pushbuf;
196 struct nouveau_bo *pushbuf_bo;
197 uint32_t pushbuf_base;
199 /* Notifier memory */
200 struct nouveau_bo *notifier_bo;
201 struct drm_mm notifier_heap;
204 struct nouveau_gpuobj_ref *ramfc;
205 struct nouveau_gpuobj_ref *cache;
208 /* XXX may be merge 2 pointers as private data ??? */
209 struct nouveau_gpuobj_ref *ramin_grctx;
213 struct nouveau_gpuobj *vm_pd;
214 struct nouveau_gpuobj_ref *vm_gart_pt;
215 struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR];
218 struct nouveau_gpuobj_ref *ramin; /* Private instmem */
219 struct drm_mm ramin_heap; /* Private PRAMIN heap */
220 struct nouveau_gpuobj_ref *ramht; /* Hash table */
221 struct list_head ramht_refs; /* Objects referenced by RAMHT */
223 /* GPU object info for stuff used in-kernel (mm_enabled) */
225 uint32_t vram_handle;
226 uint32_t gart_handle;
229 /* Push buffer state (only for drm's channel on !mm_enabled) */
235 /* access via pushbuf_bo */
243 uint32_t sw_subchannel[8];
246 struct nouveau_gpuobj *vblsem;
247 uint32_t vblsem_offset;
248 uint32_t vblsem_rval;
249 struct list_head vbl_wait;
255 struct drm_info_list info;
259 struct nouveau_instmem_engine {
262 int (*init)(struct drm_device *dev);
263 void (*takedown)(struct drm_device *dev);
264 int (*suspend)(struct drm_device *dev);
265 void (*resume)(struct drm_device *dev);
267 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
269 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
270 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
271 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
272 void (*flush)(struct drm_device *);
275 struct nouveau_mc_engine {
276 int (*init)(struct drm_device *dev);
277 void (*takedown)(struct drm_device *dev);
280 struct nouveau_timer_engine {
281 int (*init)(struct drm_device *dev);
282 void (*takedown)(struct drm_device *dev);
283 uint64_t (*read)(struct drm_device *dev);
286 struct nouveau_fb_engine {
289 int (*init)(struct drm_device *dev);
290 void (*takedown)(struct drm_device *dev);
292 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
293 uint32_t size, uint32_t pitch);
296 struct nouveau_fifo_engine {
299 struct nouveau_gpuobj_ref *playlist[2];
302 int (*init)(struct drm_device *);
303 void (*takedown)(struct drm_device *);
305 void (*disable)(struct drm_device *);
306 void (*enable)(struct drm_device *);
307 bool (*reassign)(struct drm_device *, bool enable);
308 bool (*cache_flush)(struct drm_device *dev);
309 bool (*cache_pull)(struct drm_device *dev, bool enable);
311 int (*channel_id)(struct drm_device *);
313 int (*create_context)(struct nouveau_channel *);
314 void (*destroy_context)(struct nouveau_channel *);
315 int (*load_context)(struct nouveau_channel *);
316 int (*unload_context)(struct drm_device *);
319 struct nouveau_pgraph_object_method {
321 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
325 struct nouveau_pgraph_object_class {
328 struct nouveau_pgraph_object_method *methods;
331 struct nouveau_pgraph_engine {
332 struct nouveau_pgraph_object_class *grclass;
336 /* NV2x/NV3x context table (0x400780) */
337 struct nouveau_gpuobj_ref *ctx_table;
339 int (*init)(struct drm_device *);
340 void (*takedown)(struct drm_device *);
342 void (*fifo_access)(struct drm_device *, bool);
344 struct nouveau_channel *(*channel)(struct drm_device *);
345 int (*create_context)(struct nouveau_channel *);
346 void (*destroy_context)(struct nouveau_channel *);
347 int (*load_context)(struct nouveau_channel *);
348 int (*unload_context)(struct drm_device *);
350 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
351 uint32_t size, uint32_t pitch);
354 struct nouveau_engine {
355 struct nouveau_instmem_engine instmem;
356 struct nouveau_mc_engine mc;
357 struct nouveau_timer_engine timer;
358 struct nouveau_fb_engine fb;
359 struct nouveau_pgraph_engine graph;
360 struct nouveau_fifo_engine fifo;
363 struct nouveau_pll_vals {
367 uint8_t N1, M1, N2, M2;
369 uint8_t M1, N1, M2, N2;
374 } __attribute__((packed));
381 enum nv04_fp_display_regs {
391 struct nv04_crtc_reg {
392 unsigned char MiscOutReg; /* */
395 uint8_t Sequencer[5];
397 uint8_t Attribute[21];
398 unsigned char DAC[768]; /* Internal Colorlookuptable */
408 uint32_t crtc_eng_ctrl;
411 uint32_t nv10_cursync;
412 struct nouveau_pll_vals pllvals;
413 uint32_t ramdac_gen_ctrl;
419 uint32_t tv_vsync_delay;
422 uint32_t tv_hsync_delay;
423 uint32_t tv_hsync_delay2;
424 uint32_t fp_horiz_regs[7];
425 uint32_t fp_vert_regs[7];
428 uint32_t dither_regs[6];
432 uint32_t fp_margin_color;
437 uint32_t ctv_regs[38];
440 struct nv04_output_reg {
445 struct nv04_mode_state {
473 uint32_t cursorConfig;
482 struct nv04_crtc_reg crtc_reg[2];
485 enum nouveau_card_type {
494 struct drm_nouveau_private {
495 struct drm_device *dev;
497 /* the card type, takes NV_* as values */
498 enum nouveau_card_type card_type;
499 /* exact chipset, derived from NV_PMC_BOOT_0 */
507 struct nouveau_bo *vga_ram;
509 struct workqueue_struct *wq;
510 struct work_struct irq_work;
511 struct work_struct hpd_work;
513 struct list_head vbl_waiting;
516 struct ttm_global_reference mem_global_ref;
517 struct ttm_bo_global_ref bo_global_ref;
518 struct ttm_bo_device bdev;
519 spinlock_t bo_list_lock;
520 struct list_head bo_list;
521 atomic_t validate_sequence;
524 int fifo_alloc_count;
525 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
527 struct nouveau_engine engine;
528 struct nouveau_channel *channel;
530 /* For PFIFO and PGRAPH. */
531 spinlock_t context_switch_lock;
533 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
534 struct nouveau_gpuobj *ramht;
535 uint32_t ramin_rsvd_vram;
536 uint32_t ramht_offset;
539 uint32_t ramfc_offset;
541 uint32_t ramro_offset;
546 NOUVEAU_GART_NONE = 0,
554 struct nouveau_gpuobj *sg_ctxdma;
555 struct page *sg_dummy_page;
556 dma_addr_t sg_dummy_bus;
559 /* nv10-nv40 tiling regions */
561 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
565 /* VRAM/fb configuration */
567 uint64_t vram_sys_base;
570 uint64_t fb_available_size;
571 uint64_t fb_mappable_pages;
572 uint64_t fb_aper_free;
575 /* G8x/G9x virtual address space */
576 uint64_t vm_gart_base;
577 uint64_t vm_gart_size;
578 uint64_t vm_vram_base;
579 uint64_t vm_vram_size;
581 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
584 struct drm_mm ramin_heap;
586 struct list_head gpuobj_list;
590 struct nv04_mode_state mode_reg;
591 struct nv04_mode_state saved_reg;
592 uint32_t saved_vga_font[4][16384];
594 uint32_t dac_users[4];
596 struct nouveau_suspend_resume {
597 uint32_t *ramin_copy;
600 struct backlight_device *backlight;
602 struct nouveau_channel *evo;
604 struct dcb_entry *dcb;
610 struct dentry *channel_root;
613 struct nouveau_fbdev *nfbdev;
614 struct apertures_struct *apertures;
617 static inline struct drm_nouveau_private *
618 nouveau_bdev(struct ttm_bo_device *bd)
620 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
624 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
626 struct nouveau_bo *prev;
632 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
634 struct ttm_buffer_object *bo = &prev->bo;
642 #define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
643 struct drm_nouveau_private *nv = dev->dev_private; \
644 if (!nouveau_channel_owner(dev, (cl), (id))) { \
645 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
646 DRM_CURRENTPID, (id)); \
649 (ch) = nv->fifos[(id)]; \
653 extern int nouveau_noagp;
654 extern int nouveau_duallink;
655 extern int nouveau_uscript_lvds;
656 extern int nouveau_uscript_tmds;
657 extern int nouveau_vram_pushbuf;
658 extern int nouveau_vram_notify;
659 extern int nouveau_fbpercrtc;
660 extern int nouveau_tv_disable;
661 extern char *nouveau_tv_norm;
662 extern int nouveau_reg_debug;
663 extern char *nouveau_vbios;
664 extern int nouveau_ignorelid;
665 extern int nouveau_nofbaccel;
666 extern int nouveau_noaccel;
667 extern int nouveau_override_conntype;
669 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
670 extern int nouveau_pci_resume(struct pci_dev *pdev);
672 /* nouveau_state.c */
673 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
674 extern int nouveau_load(struct drm_device *, unsigned long flags);
675 extern int nouveau_firstopen(struct drm_device *);
676 extern void nouveau_lastclose(struct drm_device *);
677 extern int nouveau_unload(struct drm_device *);
678 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
680 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
682 extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
683 uint32_t reg, uint32_t mask, uint32_t val);
684 extern bool nouveau_wait_for_idle(struct drm_device *);
685 extern int nouveau_card_init(struct drm_device *);
688 extern int nouveau_mem_detect(struct drm_device *dev);
689 extern int nouveau_mem_init(struct drm_device *);
690 extern int nouveau_mem_init_agp(struct drm_device *);
691 extern int nouveau_mem_reset_agp(struct drm_device *);
692 extern void nouveau_mem_close(struct drm_device *);
693 extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
697 extern void nv10_mem_expire_tiling(struct drm_device *dev,
698 struct nouveau_tile_reg *tile,
699 struct nouveau_fence *fence);
700 extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
701 uint32_t size, uint32_t flags,
703 extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
706 /* nouveau_notifier.c */
707 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
708 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
709 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
710 int cout, uint32_t *offset);
711 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
712 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
714 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
717 /* nouveau_channel.c */
718 extern struct drm_ioctl_desc nouveau_ioctls[];
719 extern int nouveau_max_ioctl;
720 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
721 extern int nouveau_channel_owner(struct drm_device *, struct drm_file *,
723 extern int nouveau_channel_alloc(struct drm_device *dev,
724 struct nouveau_channel **chan,
725 struct drm_file *file_priv,
726 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
727 extern void nouveau_channel_free(struct nouveau_channel *);
729 /* nouveau_object.c */
730 extern int nouveau_gpuobj_early_init(struct drm_device *);
731 extern int nouveau_gpuobj_init(struct drm_device *);
732 extern void nouveau_gpuobj_takedown(struct drm_device *);
733 extern void nouveau_gpuobj_late_takedown(struct drm_device *);
734 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
735 extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
736 extern void nouveau_gpuobj_resume(struct drm_device *dev);
737 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
738 uint32_t vram_h, uint32_t tt_h);
739 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
740 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
741 uint32_t size, int align, uint32_t flags,
742 struct nouveau_gpuobj **);
743 extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
744 extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
745 uint32_t handle, struct nouveau_gpuobj *,
746 struct nouveau_gpuobj_ref **);
747 extern int nouveau_gpuobj_ref_del(struct drm_device *,
748 struct nouveau_gpuobj_ref **);
749 extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle,
750 struct nouveau_gpuobj_ref **ref_ret);
751 extern int nouveau_gpuobj_new_ref(struct drm_device *,
752 struct nouveau_channel *alloc_chan,
753 struct nouveau_channel *ref_chan,
754 uint32_t handle, uint32_t size, int align,
755 uint32_t flags, struct nouveau_gpuobj_ref **);
756 extern int nouveau_gpuobj_new_fake(struct drm_device *,
757 uint32_t p_offset, uint32_t b_offset,
758 uint32_t size, uint32_t flags,
759 struct nouveau_gpuobj **,
760 struct nouveau_gpuobj_ref**);
761 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
762 uint64_t offset, uint64_t size, int access,
763 int target, struct nouveau_gpuobj **);
764 extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
765 uint64_t offset, uint64_t size,
766 int access, struct nouveau_gpuobj **,
768 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
769 struct nouveau_gpuobj **);
770 extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
771 struct nouveau_gpuobj **);
772 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
774 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
778 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
779 extern void nouveau_irq_preinstall(struct drm_device *);
780 extern int nouveau_irq_postinstall(struct drm_device *);
781 extern void nouveau_irq_uninstall(struct drm_device *);
783 /* nouveau_sgdma.c */
784 extern int nouveau_sgdma_init(struct drm_device *);
785 extern void nouveau_sgdma_takedown(struct drm_device *);
786 extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
788 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
790 /* nouveau_debugfs.c */
791 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
792 extern int nouveau_debugfs_init(struct drm_minor *);
793 extern void nouveau_debugfs_takedown(struct drm_minor *);
794 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
795 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
798 nouveau_debugfs_init(struct drm_minor *minor)
803 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
808 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
814 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
820 extern void nouveau_dma_pre_init(struct nouveau_channel *);
821 extern int nouveau_dma_init(struct nouveau_channel *);
822 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
825 #define ROM_BIOS_PAGE 4096
826 #if defined(CONFIG_ACPI)
827 void nouveau_register_dsm_handler(void);
828 void nouveau_unregister_dsm_handler(void);
829 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
830 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
831 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
833 static inline void nouveau_register_dsm_handler(void) {}
834 static inline void nouveau_unregister_dsm_handler(void) {}
835 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
836 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
837 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
840 /* nouveau_backlight.c */
841 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
842 extern int nouveau_backlight_init(struct drm_device *);
843 extern void nouveau_backlight_exit(struct drm_device *);
845 static inline int nouveau_backlight_init(struct drm_device *dev)
850 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
854 extern int nouveau_bios_init(struct drm_device *);
855 extern void nouveau_bios_takedown(struct drm_device *dev);
856 extern int nouveau_run_vbios_init(struct drm_device *);
857 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
859 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
861 extern struct dcb_connector_table_entry *
862 nouveau_bios_connector_entry(struct drm_device *, int index);
863 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
865 extern int nouveau_bios_run_display_table(struct drm_device *,
867 uint32_t script, int pxclk);
868 extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
870 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
871 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
872 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
873 bool *dl, bool *if_is_24bit);
874 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
875 int head, int pxclk);
876 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
877 enum LVDS_script, int pxclk);
880 int nouveau_ttm_global_init(struct drm_nouveau_private *);
881 void nouveau_ttm_global_release(struct drm_nouveau_private *);
882 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
885 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
886 uint8_t *data, int data_nr);
887 bool nouveau_dp_detect(struct drm_encoder *);
888 bool nouveau_dp_link_train(struct drm_encoder *);
891 extern int nv04_fb_init(struct drm_device *);
892 extern void nv04_fb_takedown(struct drm_device *);
895 extern int nv10_fb_init(struct drm_device *);
896 extern void nv10_fb_takedown(struct drm_device *);
897 extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
901 extern int nv30_fb_init(struct drm_device *);
902 extern void nv30_fb_takedown(struct drm_device *);
905 extern int nv40_fb_init(struct drm_device *);
906 extern void nv40_fb_takedown(struct drm_device *);
907 extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
911 extern int nv50_fb_init(struct drm_device *);
912 extern void nv50_fb_takedown(struct drm_device *);
915 extern int nv04_fifo_init(struct drm_device *);
916 extern void nv04_fifo_disable(struct drm_device *);
917 extern void nv04_fifo_enable(struct drm_device *);
918 extern bool nv04_fifo_reassign(struct drm_device *, bool);
919 extern bool nv04_fifo_cache_flush(struct drm_device *);
920 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
921 extern int nv04_fifo_channel_id(struct drm_device *);
922 extern int nv04_fifo_create_context(struct nouveau_channel *);
923 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
924 extern int nv04_fifo_load_context(struct nouveau_channel *);
925 extern int nv04_fifo_unload_context(struct drm_device *);
928 extern int nv10_fifo_init(struct drm_device *);
929 extern int nv10_fifo_channel_id(struct drm_device *);
930 extern int nv10_fifo_create_context(struct nouveau_channel *);
931 extern void nv10_fifo_destroy_context(struct nouveau_channel *);
932 extern int nv10_fifo_load_context(struct nouveau_channel *);
933 extern int nv10_fifo_unload_context(struct drm_device *);
936 extern int nv40_fifo_init(struct drm_device *);
937 extern int nv40_fifo_create_context(struct nouveau_channel *);
938 extern void nv40_fifo_destroy_context(struct nouveau_channel *);
939 extern int nv40_fifo_load_context(struct nouveau_channel *);
940 extern int nv40_fifo_unload_context(struct drm_device *);
943 extern int nv50_fifo_init(struct drm_device *);
944 extern void nv50_fifo_takedown(struct drm_device *);
945 extern int nv50_fifo_channel_id(struct drm_device *);
946 extern int nv50_fifo_create_context(struct nouveau_channel *);
947 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
948 extern int nv50_fifo_load_context(struct nouveau_channel *);
949 extern int nv50_fifo_unload_context(struct drm_device *);
952 extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
953 extern int nv04_graph_init(struct drm_device *);
954 extern void nv04_graph_takedown(struct drm_device *);
955 extern void nv04_graph_fifo_access(struct drm_device *, bool);
956 extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
957 extern int nv04_graph_create_context(struct nouveau_channel *);
958 extern void nv04_graph_destroy_context(struct nouveau_channel *);
959 extern int nv04_graph_load_context(struct nouveau_channel *);
960 extern int nv04_graph_unload_context(struct drm_device *);
961 extern void nv04_graph_context_switch(struct drm_device *);
964 extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
965 extern int nv10_graph_init(struct drm_device *);
966 extern void nv10_graph_takedown(struct drm_device *);
967 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
968 extern int nv10_graph_create_context(struct nouveau_channel *);
969 extern void nv10_graph_destroy_context(struct nouveau_channel *);
970 extern int nv10_graph_load_context(struct nouveau_channel *);
971 extern int nv10_graph_unload_context(struct drm_device *);
972 extern void nv10_graph_context_switch(struct drm_device *);
973 extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
977 extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
978 extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
979 extern int nv20_graph_create_context(struct nouveau_channel *);
980 extern void nv20_graph_destroy_context(struct nouveau_channel *);
981 extern int nv20_graph_load_context(struct nouveau_channel *);
982 extern int nv20_graph_unload_context(struct drm_device *);
983 extern int nv20_graph_init(struct drm_device *);
984 extern void nv20_graph_takedown(struct drm_device *);
985 extern int nv30_graph_init(struct drm_device *);
986 extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
990 extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
991 extern int nv40_graph_init(struct drm_device *);
992 extern void nv40_graph_takedown(struct drm_device *);
993 extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
994 extern int nv40_graph_create_context(struct nouveau_channel *);
995 extern void nv40_graph_destroy_context(struct nouveau_channel *);
996 extern int nv40_graph_load_context(struct nouveau_channel *);
997 extern int nv40_graph_unload_context(struct drm_device *);
998 extern void nv40_grctx_init(struct nouveau_grctx *);
999 extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1000 uint32_t, uint32_t);
1003 extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
1004 extern int nv50_graph_init(struct drm_device *);
1005 extern void nv50_graph_takedown(struct drm_device *);
1006 extern void nv50_graph_fifo_access(struct drm_device *, bool);
1007 extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1008 extern int nv50_graph_create_context(struct nouveau_channel *);
1009 extern void nv50_graph_destroy_context(struct nouveau_channel *);
1010 extern int nv50_graph_load_context(struct nouveau_channel *);
1011 extern int nv50_graph_unload_context(struct drm_device *);
1012 extern void nv50_graph_context_switch(struct drm_device *);
1013 extern int nv50_grctx_init(struct nouveau_grctx *);
1015 /* nv04_instmem.c */
1016 extern int nv04_instmem_init(struct drm_device *);
1017 extern void nv04_instmem_takedown(struct drm_device *);
1018 extern int nv04_instmem_suspend(struct drm_device *);
1019 extern void nv04_instmem_resume(struct drm_device *);
1020 extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1022 extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1023 extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1024 extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1025 extern void nv04_instmem_flush(struct drm_device *);
1027 /* nv50_instmem.c */
1028 extern int nv50_instmem_init(struct drm_device *);
1029 extern void nv50_instmem_takedown(struct drm_device *);
1030 extern int nv50_instmem_suspend(struct drm_device *);
1031 extern void nv50_instmem_resume(struct drm_device *);
1032 extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1034 extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1035 extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1036 extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1037 extern void nv50_instmem_flush(struct drm_device *);
1038 extern void nv84_instmem_flush(struct drm_device *);
1039 extern void nv50_vm_flush(struct drm_device *, int engine);
1042 extern int nv04_mc_init(struct drm_device *);
1043 extern void nv04_mc_takedown(struct drm_device *);
1046 extern int nv40_mc_init(struct drm_device *);
1047 extern void nv40_mc_takedown(struct drm_device *);
1050 extern int nv50_mc_init(struct drm_device *);
1051 extern void nv50_mc_takedown(struct drm_device *);
1054 extern int nv04_timer_init(struct drm_device *);
1055 extern uint64_t nv04_timer_read(struct drm_device *);
1056 extern void nv04_timer_takedown(struct drm_device *);
1058 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1062 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1063 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1064 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1065 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1066 extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1069 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1070 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1071 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1073 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1074 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1077 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1078 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1081 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1083 /* nv04_display.c */
1084 extern int nv04_display_create(struct drm_device *);
1085 extern void nv04_display_destroy(struct drm_device *);
1086 extern void nv04_display_restore(struct drm_device *);
1089 extern int nv04_crtc_create(struct drm_device *, int index);
1092 extern struct ttm_bo_driver nouveau_bo_driver;
1093 extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1094 int size, int align, uint32_t flags,
1095 uint32_t tile_mode, uint32_t tile_flags,
1096 bool no_vm, bool mappable, struct nouveau_bo **);
1097 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1098 extern int nouveau_bo_unpin(struct nouveau_bo *);
1099 extern int nouveau_bo_map(struct nouveau_bo *);
1100 extern void nouveau_bo_unmap(struct nouveau_bo *);
1101 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1103 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1104 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1105 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1106 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1108 /* nouveau_fence.c */
1109 struct nouveau_fence;
1110 extern int nouveau_fence_init(struct nouveau_channel *);
1111 extern void nouveau_fence_fini(struct nouveau_channel *);
1112 extern void nouveau_fence_update(struct nouveau_channel *);
1113 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1115 extern int nouveau_fence_emit(struct nouveau_fence *);
1116 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1117 extern bool nouveau_fence_signalled(void *obj, void *arg);
1118 extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1119 extern int nouveau_fence_flush(void *obj, void *arg);
1120 extern void nouveau_fence_unref(void **obj);
1121 extern void *nouveau_fence_ref(void *obj);
1124 extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1125 int size, int align, uint32_t flags,
1126 uint32_t tile_mode, uint32_t tile_flags,
1127 bool no_vm, bool mappable, struct nouveau_bo **);
1128 extern int nouveau_gem_object_new(struct drm_gem_object *);
1129 extern void nouveau_gem_object_del(struct drm_gem_object *);
1130 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1132 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1134 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1136 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1138 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1142 int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1143 int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1146 int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1147 int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1148 void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
1151 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1152 int *N1, int *M1, int *N2, int *M2, int *P);
1153 int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1154 int clk, int *N, int *fN, int *M, int *P);
1156 #ifndef ioread32_native
1158 #define ioread16_native ioread16be
1159 #define iowrite16_native iowrite16be
1160 #define ioread32_native ioread32be
1161 #define iowrite32_native iowrite32be
1162 #else /* def __BIG_ENDIAN */
1163 #define ioread16_native ioread16
1164 #define iowrite16_native iowrite16
1165 #define ioread32_native ioread32
1166 #define iowrite32_native iowrite32
1167 #endif /* def __BIG_ENDIAN else */
1168 #endif /* !ioread32_native */
1170 /* channel control reg access */
1171 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1173 return ioread32_native(chan->user + reg);
1176 static inline void nvchan_wr32(struct nouveau_channel *chan,
1177 unsigned reg, u32 val)
1179 iowrite32_native(val, chan->user + reg);
1182 /* register access */
1183 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1185 struct drm_nouveau_private *dev_priv = dev->dev_private;
1186 return ioread32_native(dev_priv->mmio + reg);
1189 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1191 struct drm_nouveau_private *dev_priv = dev->dev_private;
1192 iowrite32_native(val, dev_priv->mmio + reg);
1195 static inline void nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1197 u32 tmp = nv_rd32(dev, reg);
1200 nv_wr32(dev, reg, tmp);
1203 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1205 struct drm_nouveau_private *dev_priv = dev->dev_private;
1206 return ioread8(dev_priv->mmio + reg);
1209 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1211 struct drm_nouveau_private *dev_priv = dev->dev_private;
1212 iowrite8(val, dev_priv->mmio + reg);
1215 #define nv_wait(reg, mask, val) \
1216 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1219 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1221 struct drm_nouveau_private *dev_priv = dev->dev_private;
1222 return ioread32_native(dev_priv->ramin + offset);
1225 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1227 struct drm_nouveau_private *dev_priv = dev->dev_private;
1228 iowrite32_native(val, dev_priv->ramin + offset);
1232 static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1235 return nv_ri32(dev, obj->im_pramin->start + index * 4);
1238 static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1239 unsigned index, u32 val)
1241 nv_wi32(dev, obj->im_pramin->start + index * 4, val);
1246 * Argument d is (struct drm_device *).
1248 #define NV_PRINTK(level, d, fmt, arg...) \
1249 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1250 pci_name(d->pdev), ##arg)
1251 #ifndef NV_DEBUG_NOTRACE
1252 #define NV_DEBUG(d, fmt, arg...) do { \
1253 if (drm_debug & DRM_UT_DRIVER) { \
1254 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1258 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1259 if (drm_debug & DRM_UT_KMS) { \
1260 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1265 #define NV_DEBUG(d, fmt, arg...) do { \
1266 if (drm_debug & DRM_UT_DRIVER) \
1267 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1269 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1270 if (drm_debug & DRM_UT_KMS) \
1271 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1274 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1275 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1276 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1277 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1278 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1280 /* nouveau_reg_debug bitmask */
1282 NOUVEAU_REG_DEBUG_MC = 0x1,
1283 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1284 NOUVEAU_REG_DEBUG_FB = 0x4,
1285 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1286 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1287 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1288 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1289 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1290 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1291 NOUVEAU_REG_DEBUG_EVO = 0x200,
1294 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1295 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1296 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1300 nv_two_heads(struct drm_device *dev)
1302 struct drm_nouveau_private *dev_priv = dev->dev_private;
1303 const int impl = dev->pci_device & 0x0ff0;
1305 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1306 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1313 nv_gf4_disp_arch(struct drm_device *dev)
1315 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1319 nv_two_reg_pll(struct drm_device *dev)
1321 struct drm_nouveau_private *dev_priv = dev->dev_private;
1322 const int impl = dev->pci_device & 0x0ff0;
1324 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1329 #define NV_SW 0x0000506e
1330 #define NV_SW_DMA_SEMAPHORE 0x00000060
1331 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1332 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1333 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1334 #define NV_SW_DMA_VBLSEM 0x0000018c
1335 #define NV_SW_VBLSEM_OFFSET 0x00000400
1336 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1337 #define NV_SW_VBLSEM_RELEASE 0x00000408
1339 #endif /* __NOUVEAU_DRV_H__ */