2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
48 struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
54 #include "nouveau_drm.h"
55 #include "nouveau_reg.h"
56 #include "nouveau_bios.h"
59 #define MAX_NUM_DCB_ENTRIES 16
61 #define NOUVEAU_MAX_CHANNEL_NR 128
62 #define NOUVEAU_MAX_TILE_NR 15
64 #define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65 #define NV50_VM_BLOCK (512*1024*1024ULL)
66 #define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
68 struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
79 u32 busy_placements[3];
80 struct ttm_bo_kmap_obj kmap;
81 struct list_head head;
83 /* protected by ttm_bo_reserve() */
84 struct drm_file *reserved_by;
85 struct list_head entry;
89 struct nouveau_channel *channel;
96 struct nouveau_tile_reg *tile;
98 struct drm_gem_object *gem;
102 #define nouveau_bo_tile_layout(nvbo) \
103 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
105 static inline struct nouveau_bo *
106 nouveau_bo(struct ttm_buffer_object *bo)
108 return container_of(bo, struct nouveau_bo, bo);
111 static inline struct nouveau_bo *
112 nouveau_gem_object(struct drm_gem_object *gem)
114 return gem ? gem->driver_private : NULL;
117 /* TODO: submit equivalent to TTM generic API upstream? */
118 static inline void __iomem *
119 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
122 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
123 &nvbo->kmap, &is_iomem);
124 WARN_ON_ONCE(ioptr && !is_iomem);
129 NV_NFORCE = 0x10000000,
130 NV_NFORCE2 = 0x20000000
133 #define NVOBJ_ENGINE_SW 0
134 #define NVOBJ_ENGINE_GR 1
135 #define NVOBJ_ENGINE_DISPLAY 2
136 #define NVOBJ_ENGINE_INT 0xdeadbeef
138 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
139 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
140 struct nouveau_gpuobj {
141 struct drm_device *dev;
142 struct kref refcount;
143 struct list_head list;
145 struct drm_mm_node *im_pramin;
146 struct nouveau_bo *im_backing;
147 uint32_t *im_backing_suspend;
160 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
164 struct nouveau_channel {
165 struct drm_device *dev;
171 /* owner of this fifo */
172 struct drm_file *file_priv;
173 /* mapping of the fifo itself */
174 struct drm_local_map *map;
176 /* mapping of the regs controling the fifo */
183 /* lock protects the pending list only */
185 struct list_head pending;
187 uint32_t sequence_ack;
188 atomic_t last_sequence_irq;
191 /* DMA push buffer */
192 struct nouveau_gpuobj *pushbuf;
193 struct nouveau_bo *pushbuf_bo;
194 uint32_t pushbuf_base;
196 /* Notifier memory */
197 struct nouveau_bo *notifier_bo;
198 struct drm_mm notifier_heap;
201 struct nouveau_gpuobj *ramfc;
202 struct nouveau_gpuobj *cache;
205 /* XXX may be merge 2 pointers as private data ??? */
206 struct nouveau_gpuobj *ramin_grctx;
210 struct nouveau_gpuobj *vm_pd;
211 struct nouveau_gpuobj *vm_gart_pt;
212 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
215 struct nouveau_gpuobj *ramin; /* Private instmem */
216 struct drm_mm ramin_heap; /* Private PRAMIN heap */
217 struct nouveau_ramht *ramht; /* Hash table */
219 /* GPU object info for stuff used in-kernel (mm_enabled) */
221 uint32_t vram_handle;
222 uint32_t gart_handle;
225 /* Push buffer state (only for drm's channel on !mm_enabled) */
231 /* access via pushbuf_bo */
239 uint32_t sw_subchannel[8];
242 struct nouveau_gpuobj *vblsem;
243 uint32_t vblsem_offset;
244 uint32_t vblsem_rval;
245 struct list_head vbl_wait;
251 struct drm_info_list info;
255 struct nouveau_instmem_engine {
258 int (*init)(struct drm_device *dev);
259 void (*takedown)(struct drm_device *dev);
260 int (*suspend)(struct drm_device *dev);
261 void (*resume)(struct drm_device *dev);
263 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
265 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
266 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
267 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
268 void (*flush)(struct drm_device *);
271 struct nouveau_mc_engine {
272 int (*init)(struct drm_device *dev);
273 void (*takedown)(struct drm_device *dev);
276 struct nouveau_timer_engine {
277 int (*init)(struct drm_device *dev);
278 void (*takedown)(struct drm_device *dev);
279 uint64_t (*read)(struct drm_device *dev);
282 struct nouveau_fb_engine {
285 int (*init)(struct drm_device *dev);
286 void (*takedown)(struct drm_device *dev);
288 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
289 uint32_t size, uint32_t pitch);
292 struct nouveau_fifo_engine {
295 struct nouveau_gpuobj *playlist[2];
298 int (*init)(struct drm_device *);
299 void (*takedown)(struct drm_device *);
301 void (*disable)(struct drm_device *);
302 void (*enable)(struct drm_device *);
303 bool (*reassign)(struct drm_device *, bool enable);
304 bool (*cache_pull)(struct drm_device *dev, bool enable);
306 int (*channel_id)(struct drm_device *);
308 int (*create_context)(struct nouveau_channel *);
309 void (*destroy_context)(struct nouveau_channel *);
310 int (*load_context)(struct nouveau_channel *);
311 int (*unload_context)(struct drm_device *);
312 void (*tlb_flush)(struct drm_device *dev);
315 struct nouveau_pgraph_object_method {
317 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
321 struct nouveau_pgraph_object_class {
324 struct nouveau_pgraph_object_method *methods;
327 struct nouveau_pgraph_engine {
328 struct nouveau_pgraph_object_class *grclass;
332 /* NV2x/NV3x context table (0x400780) */
333 struct nouveau_gpuobj *ctx_table;
335 int (*init)(struct drm_device *);
336 void (*takedown)(struct drm_device *);
338 void (*fifo_access)(struct drm_device *, bool);
340 struct nouveau_channel *(*channel)(struct drm_device *);
341 int (*create_context)(struct nouveau_channel *);
342 void (*destroy_context)(struct nouveau_channel *);
343 int (*load_context)(struct nouveau_channel *);
344 int (*unload_context)(struct drm_device *);
345 void (*tlb_flush)(struct drm_device *dev);
347 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
348 uint32_t size, uint32_t pitch);
351 struct nouveau_display_engine {
352 int (*early_init)(struct drm_device *);
353 void (*late_takedown)(struct drm_device *);
354 int (*create)(struct drm_device *);
355 int (*init)(struct drm_device *);
356 void (*destroy)(struct drm_device *);
359 struct nouveau_gpio_engine {
360 int (*init)(struct drm_device *);
361 void (*takedown)(struct drm_device *);
363 int (*get)(struct drm_device *, enum dcb_gpio_tag);
364 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
366 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
369 struct nouveau_pm_voltage_level {
374 struct nouveau_pm_voltage {
378 struct nouveau_pm_voltage_level *level;
382 #define NOUVEAU_PM_MAX_LEVEL 8
383 struct nouveau_pm_level {
384 struct device_attribute dev_attr;
399 struct nouveau_pm_temp_sensor_constants {
407 struct nouveau_pm_threshold_temp {
413 struct nouveau_pm_memtiming {
424 struct nouveau_pm_memtimings {
426 struct nouveau_pm_memtiming *timing;
430 struct nouveau_pm_engine {
431 struct nouveau_pm_voltage voltage;
432 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
434 struct nouveau_pm_memtimings memtimings;
435 struct nouveau_pm_temp_sensor_constants sensor_constants;
436 struct nouveau_pm_threshold_temp threshold_temp;
438 struct nouveau_pm_level boot;
439 struct nouveau_pm_level *cur;
441 struct device *hwmon;
442 struct notifier_block acpi_nb;
444 int (*clock_get)(struct drm_device *, u32 id);
445 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *,
447 void (*clock_set)(struct drm_device *, void *);
448 int (*voltage_get)(struct drm_device *);
449 int (*voltage_set)(struct drm_device *, int voltage);
450 int (*fanspeed_get)(struct drm_device *);
451 int (*fanspeed_set)(struct drm_device *, int fanspeed);
452 int (*temp_get)(struct drm_device *);
455 struct nouveau_engine {
456 struct nouveau_instmem_engine instmem;
457 struct nouveau_mc_engine mc;
458 struct nouveau_timer_engine timer;
459 struct nouveau_fb_engine fb;
460 struct nouveau_pgraph_engine graph;
461 struct nouveau_fifo_engine fifo;
462 struct nouveau_display_engine display;
463 struct nouveau_gpio_engine gpio;
464 struct nouveau_pm_engine pm;
467 struct nouveau_pll_vals {
471 uint8_t N1, M1, N2, M2;
473 uint8_t M1, N1, M2, N2;
478 } __attribute__((packed));
485 enum nv04_fp_display_regs {
495 struct nv04_crtc_reg {
496 unsigned char MiscOutReg;
499 uint8_t Sequencer[5];
501 uint8_t Attribute[21];
502 unsigned char DAC[768];
512 uint32_t crtc_eng_ctrl;
515 uint32_t nv10_cursync;
516 struct nouveau_pll_vals pllvals;
517 uint32_t ramdac_gen_ctrl;
523 uint32_t tv_vsync_delay;
526 uint32_t tv_hsync_delay;
527 uint32_t tv_hsync_delay2;
528 uint32_t fp_horiz_regs[7];
529 uint32_t fp_vert_regs[7];
532 uint32_t dither_regs[6];
536 uint32_t fp_margin_color;
541 uint32_t ctv_regs[38];
544 struct nv04_output_reg {
549 struct nv04_mode_state {
550 struct nv04_crtc_reg crtc_reg[2];
555 enum nouveau_card_type {
565 struct drm_nouveau_private {
566 struct drm_device *dev;
568 /* the card type, takes NV_* as values */
569 enum nouveau_card_type card_type;
570 /* exact chipset, derived from NV_PMC_BOOT_0 */
576 spinlock_t ramin_lock;
580 bool ramin_available;
581 struct drm_mm ramin_heap;
582 struct list_head gpuobj_list;
584 struct nouveau_bo *vga_ram;
586 struct workqueue_struct *wq;
587 struct work_struct irq_work;
588 struct work_struct hpd_work;
596 struct list_head vbl_waiting;
599 struct drm_global_reference mem_global_ref;
600 struct ttm_bo_global_ref bo_global_ref;
601 struct ttm_bo_device bdev;
602 atomic_t validate_sequence;
608 struct nouveau_bo *bo;
613 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
616 struct nouveau_engine engine;
617 struct nouveau_channel *channel;
619 /* For PFIFO and PGRAPH. */
620 spinlock_t context_switch_lock;
622 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
623 struct nouveau_ramht *ramht;
624 struct nouveau_gpuobj *ramfc;
625 struct nouveau_gpuobj *ramro;
627 uint32_t ramin_rsvd_vram;
631 NOUVEAU_GART_NONE = 0,
639 struct nouveau_gpuobj *sg_ctxdma;
640 struct page *sg_dummy_page;
641 dma_addr_t sg_dummy_bus;
644 /* nv10-nv40 tiling regions */
645 struct nouveau_tile_reg tile[NOUVEAU_MAX_TILE_NR];
647 /* VRAM/fb configuration */
649 uint64_t vram_sys_base;
650 u32 vram_rblock_size;
653 uint64_t fb_available_size;
654 uint64_t fb_mappable_pages;
655 uint64_t fb_aper_free;
658 /* G8x/G9x virtual address space */
659 uint64_t vm_gart_base;
660 uint64_t vm_gart_size;
661 uint64_t vm_vram_base;
662 uint64_t vm_vram_size;
664 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
669 struct nv04_mode_state mode_reg;
670 struct nv04_mode_state saved_reg;
671 uint32_t saved_vga_font[4][16384];
673 uint32_t dac_users[4];
675 struct nouveau_suspend_resume {
676 uint32_t *ramin_copy;
679 struct backlight_device *backlight;
681 struct nouveau_channel *evo;
683 struct dcb_entry *dcb;
689 struct dentry *channel_root;
692 struct nouveau_fbdev *nfbdev;
693 struct apertures_struct *apertures;
696 static inline struct drm_nouveau_private *
697 nouveau_private(struct drm_device *dev)
699 return dev->dev_private;
702 static inline struct drm_nouveau_private *
703 nouveau_bdev(struct ttm_bo_device *bd)
705 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
709 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
711 struct nouveau_bo *prev;
717 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
719 struct ttm_buffer_object *bo = &prev->bo;
728 extern int nouveau_agpmode;
729 extern int nouveau_duallink;
730 extern int nouveau_uscript_lvds;
731 extern int nouveau_uscript_tmds;
732 extern int nouveau_vram_pushbuf;
733 extern int nouveau_vram_notify;
734 extern int nouveau_fbpercrtc;
735 extern int nouveau_tv_disable;
736 extern char *nouveau_tv_norm;
737 extern int nouveau_reg_debug;
738 extern char *nouveau_vbios;
739 extern int nouveau_ignorelid;
740 extern int nouveau_nofbaccel;
741 extern int nouveau_noaccel;
742 extern int nouveau_force_post;
743 extern int nouveau_override_conntype;
744 extern char *nouveau_perflvl;
745 extern int nouveau_perflvl_wr;
747 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
748 extern int nouveau_pci_resume(struct pci_dev *pdev);
750 /* nouveau_state.c */
751 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
752 extern int nouveau_load(struct drm_device *, unsigned long flags);
753 extern int nouveau_firstopen(struct drm_device *);
754 extern void nouveau_lastclose(struct drm_device *);
755 extern int nouveau_unload(struct drm_device *);
756 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
758 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
760 extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
761 uint32_t reg, uint32_t mask, uint32_t val);
762 extern bool nouveau_wait_for_idle(struct drm_device *);
763 extern int nouveau_card_init(struct drm_device *);
766 extern int nouveau_mem_vram_init(struct drm_device *);
767 extern void nouveau_mem_vram_fini(struct drm_device *);
768 extern int nouveau_mem_gart_init(struct drm_device *);
769 extern void nouveau_mem_gart_fini(struct drm_device *);
770 extern int nouveau_mem_init_agp(struct drm_device *);
771 extern int nouveau_mem_reset_agp(struct drm_device *);
772 extern void nouveau_mem_close(struct drm_device *);
773 extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
777 extern void nv10_mem_expire_tiling(struct drm_device *dev,
778 struct nouveau_tile_reg *tile,
779 struct nouveau_fence *fence);
780 extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
781 uint32_t size, uint32_t flags,
783 extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
786 /* nouveau_notifier.c */
787 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
788 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
789 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
790 int cout, uint32_t *offset);
791 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
792 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
794 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
797 /* nouveau_channel.c */
798 extern struct drm_ioctl_desc nouveau_ioctls[];
799 extern int nouveau_max_ioctl;
800 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
801 extern int nouveau_channel_alloc(struct drm_device *dev,
802 struct nouveau_channel **chan,
803 struct drm_file *file_priv,
804 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
805 extern struct nouveau_channel *
806 nouveau_channel_get_unlocked(struct nouveau_channel *);
807 extern struct nouveau_channel *
808 nouveau_channel_get(struct drm_device *, struct drm_file *, int id);
809 extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
810 extern void nouveau_channel_put(struct nouveau_channel **);
812 /* nouveau_object.c */
813 extern int nouveau_gpuobj_early_init(struct drm_device *);
814 extern int nouveau_gpuobj_init(struct drm_device *);
815 extern void nouveau_gpuobj_takedown(struct drm_device *);
816 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
817 extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
818 extern void nouveau_gpuobj_resume(struct drm_device *dev);
819 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
820 uint32_t vram_h, uint32_t tt_h);
821 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
822 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
823 uint32_t size, int align, uint32_t flags,
824 struct nouveau_gpuobj **);
825 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
826 struct nouveau_gpuobj **);
827 extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
829 struct nouveau_gpuobj **);
830 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
831 uint64_t offset, uint64_t size, int access,
832 int target, struct nouveau_gpuobj **);
833 extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
834 uint64_t offset, uint64_t size,
835 int access, struct nouveau_gpuobj **,
837 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
838 struct nouveau_gpuobj **);
839 extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
840 struct nouveau_gpuobj **);
841 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
843 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
847 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
848 extern void nouveau_irq_preinstall(struct drm_device *);
849 extern int nouveau_irq_postinstall(struct drm_device *);
850 extern void nouveau_irq_uninstall(struct drm_device *);
852 /* nouveau_sgdma.c */
853 extern int nouveau_sgdma_init(struct drm_device *);
854 extern void nouveau_sgdma_takedown(struct drm_device *);
855 extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
857 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
859 /* nouveau_debugfs.c */
860 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
861 extern int nouveau_debugfs_init(struct drm_minor *);
862 extern void nouveau_debugfs_takedown(struct drm_minor *);
863 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
864 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
867 nouveau_debugfs_init(struct drm_minor *minor)
872 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
877 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
883 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
889 extern void nouveau_dma_pre_init(struct nouveau_channel *);
890 extern int nouveau_dma_init(struct nouveau_channel *);
891 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
894 #define ROM_BIOS_PAGE 4096
895 #if defined(CONFIG_ACPI)
896 void nouveau_register_dsm_handler(void);
897 void nouveau_unregister_dsm_handler(void);
898 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
899 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
900 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
902 static inline void nouveau_register_dsm_handler(void) {}
903 static inline void nouveau_unregister_dsm_handler(void) {}
904 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
905 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
906 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
909 /* nouveau_backlight.c */
910 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
911 extern int nouveau_backlight_init(struct drm_device *);
912 extern void nouveau_backlight_exit(struct drm_device *);
914 static inline int nouveau_backlight_init(struct drm_device *dev)
919 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
923 extern int nouveau_bios_init(struct drm_device *);
924 extern void nouveau_bios_takedown(struct drm_device *dev);
925 extern int nouveau_run_vbios_init(struct drm_device *);
926 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
928 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
930 extern struct dcb_connector_table_entry *
931 nouveau_bios_connector_entry(struct drm_device *, int index);
932 extern u32 get_pll_register(struct drm_device *, enum pll_types);
933 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
935 extern int nouveau_bios_run_display_table(struct drm_device *,
937 uint32_t script, int pxclk);
938 extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
940 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
941 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
942 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
943 bool *dl, bool *if_is_24bit);
944 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
945 int head, int pxclk);
946 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
947 enum LVDS_script, int pxclk);
950 int nouveau_ttm_global_init(struct drm_nouveau_private *);
951 void nouveau_ttm_global_release(struct drm_nouveau_private *);
952 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
955 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
956 uint8_t *data, int data_nr);
957 bool nouveau_dp_detect(struct drm_encoder *);
958 bool nouveau_dp_link_train(struct drm_encoder *);
961 extern int nv04_fb_init(struct drm_device *);
962 extern void nv04_fb_takedown(struct drm_device *);
965 extern int nv10_fb_init(struct drm_device *);
966 extern void nv10_fb_takedown(struct drm_device *);
967 extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
971 extern int nv30_fb_init(struct drm_device *);
972 extern void nv30_fb_takedown(struct drm_device *);
975 extern int nv40_fb_init(struct drm_device *);
976 extern void nv40_fb_takedown(struct drm_device *);
977 extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
980 extern int nv50_fb_init(struct drm_device *);
981 extern void nv50_fb_takedown(struct drm_device *);
982 extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *);
985 extern int nvc0_fb_init(struct drm_device *);
986 extern void nvc0_fb_takedown(struct drm_device *);
989 extern int nv04_fifo_init(struct drm_device *);
990 extern void nv04_fifo_disable(struct drm_device *);
991 extern void nv04_fifo_enable(struct drm_device *);
992 extern bool nv04_fifo_reassign(struct drm_device *, bool);
993 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
994 extern int nv04_fifo_channel_id(struct drm_device *);
995 extern int nv04_fifo_create_context(struct nouveau_channel *);
996 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
997 extern int nv04_fifo_load_context(struct nouveau_channel *);
998 extern int nv04_fifo_unload_context(struct drm_device *);
1001 extern int nv10_fifo_init(struct drm_device *);
1002 extern int nv10_fifo_channel_id(struct drm_device *);
1003 extern int nv10_fifo_create_context(struct nouveau_channel *);
1004 extern int nv10_fifo_load_context(struct nouveau_channel *);
1005 extern int nv10_fifo_unload_context(struct drm_device *);
1008 extern int nv40_fifo_init(struct drm_device *);
1009 extern int nv40_fifo_create_context(struct nouveau_channel *);
1010 extern int nv40_fifo_load_context(struct nouveau_channel *);
1011 extern int nv40_fifo_unload_context(struct drm_device *);
1014 extern int nv50_fifo_init(struct drm_device *);
1015 extern void nv50_fifo_takedown(struct drm_device *);
1016 extern int nv50_fifo_channel_id(struct drm_device *);
1017 extern int nv50_fifo_create_context(struct nouveau_channel *);
1018 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1019 extern int nv50_fifo_load_context(struct nouveau_channel *);
1020 extern int nv50_fifo_unload_context(struct drm_device *);
1021 extern void nv50_fifo_tlb_flush(struct drm_device *dev);
1024 extern int nvc0_fifo_init(struct drm_device *);
1025 extern void nvc0_fifo_takedown(struct drm_device *);
1026 extern void nvc0_fifo_disable(struct drm_device *);
1027 extern void nvc0_fifo_enable(struct drm_device *);
1028 extern bool nvc0_fifo_reassign(struct drm_device *, bool);
1029 extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1030 extern int nvc0_fifo_channel_id(struct drm_device *);
1031 extern int nvc0_fifo_create_context(struct nouveau_channel *);
1032 extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1033 extern int nvc0_fifo_load_context(struct nouveau_channel *);
1034 extern int nvc0_fifo_unload_context(struct drm_device *);
1037 extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
1038 extern int nv04_graph_init(struct drm_device *);
1039 extern void nv04_graph_takedown(struct drm_device *);
1040 extern void nv04_graph_fifo_access(struct drm_device *, bool);
1041 extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
1042 extern int nv04_graph_create_context(struct nouveau_channel *);
1043 extern void nv04_graph_destroy_context(struct nouveau_channel *);
1044 extern int nv04_graph_load_context(struct nouveau_channel *);
1045 extern int nv04_graph_unload_context(struct drm_device *);
1046 extern void nv04_graph_context_switch(struct drm_device *);
1049 extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
1050 extern int nv10_graph_init(struct drm_device *);
1051 extern void nv10_graph_takedown(struct drm_device *);
1052 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1053 extern int nv10_graph_create_context(struct nouveau_channel *);
1054 extern void nv10_graph_destroy_context(struct nouveau_channel *);
1055 extern int nv10_graph_load_context(struct nouveau_channel *);
1056 extern int nv10_graph_unload_context(struct drm_device *);
1057 extern void nv10_graph_context_switch(struct drm_device *);
1058 extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1059 uint32_t, uint32_t);
1062 extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
1063 extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
1064 extern int nv20_graph_create_context(struct nouveau_channel *);
1065 extern void nv20_graph_destroy_context(struct nouveau_channel *);
1066 extern int nv20_graph_load_context(struct nouveau_channel *);
1067 extern int nv20_graph_unload_context(struct drm_device *);
1068 extern int nv20_graph_init(struct drm_device *);
1069 extern void nv20_graph_takedown(struct drm_device *);
1070 extern int nv30_graph_init(struct drm_device *);
1071 extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1072 uint32_t, uint32_t);
1075 extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
1076 extern int nv40_graph_init(struct drm_device *);
1077 extern void nv40_graph_takedown(struct drm_device *);
1078 extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1079 extern int nv40_graph_create_context(struct nouveau_channel *);
1080 extern void nv40_graph_destroy_context(struct nouveau_channel *);
1081 extern int nv40_graph_load_context(struct nouveau_channel *);
1082 extern int nv40_graph_unload_context(struct drm_device *);
1083 extern void nv40_grctx_init(struct nouveau_grctx *);
1084 extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1085 uint32_t, uint32_t);
1088 extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
1089 extern int nv50_graph_init(struct drm_device *);
1090 extern void nv50_graph_takedown(struct drm_device *);
1091 extern void nv50_graph_fifo_access(struct drm_device *, bool);
1092 extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1093 extern int nv50_graph_create_context(struct nouveau_channel *);
1094 extern void nv50_graph_destroy_context(struct nouveau_channel *);
1095 extern int nv50_graph_load_context(struct nouveau_channel *);
1096 extern int nv50_graph_unload_context(struct drm_device *);
1097 extern void nv50_graph_context_switch(struct drm_device *);
1098 extern int nv50_grctx_init(struct nouveau_grctx *);
1099 extern void nv50_graph_tlb_flush(struct drm_device *dev);
1100 extern void nv86_graph_tlb_flush(struct drm_device *dev);
1103 extern int nvc0_graph_init(struct drm_device *);
1104 extern void nvc0_graph_takedown(struct drm_device *);
1105 extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1106 extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1107 extern int nvc0_graph_create_context(struct nouveau_channel *);
1108 extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1109 extern int nvc0_graph_load_context(struct nouveau_channel *);
1110 extern int nvc0_graph_unload_context(struct drm_device *);
1112 /* nv04_instmem.c */
1113 extern int nv04_instmem_init(struct drm_device *);
1114 extern void nv04_instmem_takedown(struct drm_device *);
1115 extern int nv04_instmem_suspend(struct drm_device *);
1116 extern void nv04_instmem_resume(struct drm_device *);
1117 extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1119 extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1120 extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1121 extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1122 extern void nv04_instmem_flush(struct drm_device *);
1124 /* nv50_instmem.c */
1125 extern int nv50_instmem_init(struct drm_device *);
1126 extern void nv50_instmem_takedown(struct drm_device *);
1127 extern int nv50_instmem_suspend(struct drm_device *);
1128 extern void nv50_instmem_resume(struct drm_device *);
1129 extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1131 extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1132 extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1133 extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1134 extern void nv50_instmem_flush(struct drm_device *);
1135 extern void nv84_instmem_flush(struct drm_device *);
1136 extern void nv50_vm_flush(struct drm_device *, int engine);
1138 /* nvc0_instmem.c */
1139 extern int nvc0_instmem_init(struct drm_device *);
1140 extern void nvc0_instmem_takedown(struct drm_device *);
1141 extern int nvc0_instmem_suspend(struct drm_device *);
1142 extern void nvc0_instmem_resume(struct drm_device *);
1143 extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1145 extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1146 extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1147 extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1148 extern void nvc0_instmem_flush(struct drm_device *);
1151 extern int nv04_mc_init(struct drm_device *);
1152 extern void nv04_mc_takedown(struct drm_device *);
1155 extern int nv40_mc_init(struct drm_device *);
1156 extern void nv40_mc_takedown(struct drm_device *);
1159 extern int nv50_mc_init(struct drm_device *);
1160 extern void nv50_mc_takedown(struct drm_device *);
1163 extern int nv04_timer_init(struct drm_device *);
1164 extern uint64_t nv04_timer_read(struct drm_device *);
1165 extern void nv04_timer_takedown(struct drm_device *);
1167 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1171 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1172 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1173 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1174 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1175 extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1178 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1179 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1180 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1182 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1183 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1186 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1187 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1190 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1192 /* nv04_display.c */
1193 extern int nv04_display_early_init(struct drm_device *);
1194 extern void nv04_display_late_takedown(struct drm_device *);
1195 extern int nv04_display_create(struct drm_device *);
1196 extern int nv04_display_init(struct drm_device *);
1197 extern void nv04_display_destroy(struct drm_device *);
1200 extern int nv04_crtc_create(struct drm_device *, int index);
1203 extern struct ttm_bo_driver nouveau_bo_driver;
1204 extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1205 int size, int align, uint32_t flags,
1206 uint32_t tile_mode, uint32_t tile_flags,
1207 bool no_vm, bool mappable, struct nouveau_bo **);
1208 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1209 extern int nouveau_bo_unpin(struct nouveau_bo *);
1210 extern int nouveau_bo_map(struct nouveau_bo *);
1211 extern void nouveau_bo_unmap(struct nouveau_bo *);
1212 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1214 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1215 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1216 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1217 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1219 /* nouveau_fence.c */
1220 struct nouveau_fence;
1221 extern int nouveau_fence_init(struct drm_device *);
1222 extern void nouveau_fence_fini(struct drm_device *);
1223 extern int nouveau_fence_channel_init(struct nouveau_channel *);
1224 extern void nouveau_fence_channel_fini(struct nouveau_channel *);
1225 extern void nouveau_fence_update(struct nouveau_channel *);
1226 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1228 extern int nouveau_fence_emit(struct nouveau_fence *);
1229 extern void nouveau_fence_work(struct nouveau_fence *fence,
1230 void (*work)(void *priv, bool signalled),
1232 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1233 extern bool nouveau_fence_signalled(void *obj, void *arg);
1234 extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1235 extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
1236 extern int nouveau_fence_flush(void *obj, void *arg);
1237 extern void nouveau_fence_unref(void **obj);
1238 extern void *nouveau_fence_ref(void *obj);
1241 extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1242 int size, int align, uint32_t flags,
1243 uint32_t tile_mode, uint32_t tile_flags,
1244 bool no_vm, bool mappable, struct nouveau_bo **);
1245 extern int nouveau_gem_object_new(struct drm_gem_object *);
1246 extern void nouveau_gem_object_del(struct drm_gem_object *);
1247 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1249 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1251 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1253 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1255 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1259 int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1260 int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1263 int nv50_gpio_init(struct drm_device *dev);
1264 int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1265 int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1266 void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
1269 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1270 int *N1, int *M1, int *N2, int *M2, int *P);
1271 int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1272 int clk, int *N, int *fN, int *M, int *P);
1274 #ifndef ioread32_native
1276 #define ioread16_native ioread16be
1277 #define iowrite16_native iowrite16be
1278 #define ioread32_native ioread32be
1279 #define iowrite32_native iowrite32be
1280 #else /* def __BIG_ENDIAN */
1281 #define ioread16_native ioread16
1282 #define iowrite16_native iowrite16
1283 #define ioread32_native ioread32
1284 #define iowrite32_native iowrite32
1285 #endif /* def __BIG_ENDIAN else */
1286 #endif /* !ioread32_native */
1288 /* channel control reg access */
1289 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1291 return ioread32_native(chan->user + reg);
1294 static inline void nvchan_wr32(struct nouveau_channel *chan,
1295 unsigned reg, u32 val)
1297 iowrite32_native(val, chan->user + reg);
1300 /* register access */
1301 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1303 struct drm_nouveau_private *dev_priv = dev->dev_private;
1304 return ioread32_native(dev_priv->mmio + reg);
1307 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1309 struct drm_nouveau_private *dev_priv = dev->dev_private;
1310 iowrite32_native(val, dev_priv->mmio + reg);
1313 static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1315 u32 tmp = nv_rd32(dev, reg);
1316 nv_wr32(dev, reg, (tmp & ~mask) | val);
1320 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1322 struct drm_nouveau_private *dev_priv = dev->dev_private;
1323 return ioread8(dev_priv->mmio + reg);
1326 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1328 struct drm_nouveau_private *dev_priv = dev->dev_private;
1329 iowrite8(val, dev_priv->mmio + reg);
1332 #define nv_wait(dev, reg, mask, val) \
1333 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1336 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1338 struct drm_nouveau_private *dev_priv = dev->dev_private;
1339 return ioread32_native(dev_priv->ramin + offset);
1342 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1344 struct drm_nouveau_private *dev_priv = dev->dev_private;
1345 iowrite32_native(val, dev_priv->ramin + offset);
1349 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1350 extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
1354 * Argument d is (struct drm_device *).
1356 #define NV_PRINTK(level, d, fmt, arg...) \
1357 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1358 pci_name(d->pdev), ##arg)
1359 #ifndef NV_DEBUG_NOTRACE
1360 #define NV_DEBUG(d, fmt, arg...) do { \
1361 if (drm_debug & DRM_UT_DRIVER) { \
1362 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1366 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1367 if (drm_debug & DRM_UT_KMS) { \
1368 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1373 #define NV_DEBUG(d, fmt, arg...) do { \
1374 if (drm_debug & DRM_UT_DRIVER) \
1375 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1377 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1378 if (drm_debug & DRM_UT_KMS) \
1379 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1382 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1383 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1384 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1385 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1386 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1388 /* nouveau_reg_debug bitmask */
1390 NOUVEAU_REG_DEBUG_MC = 0x1,
1391 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1392 NOUVEAU_REG_DEBUG_FB = 0x4,
1393 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1394 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1395 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1396 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1397 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1398 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1399 NOUVEAU_REG_DEBUG_EVO = 0x200,
1402 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1403 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1404 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1408 nv_two_heads(struct drm_device *dev)
1410 struct drm_nouveau_private *dev_priv = dev->dev_private;
1411 const int impl = dev->pci_device & 0x0ff0;
1413 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1414 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1421 nv_gf4_disp_arch(struct drm_device *dev)
1423 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1427 nv_two_reg_pll(struct drm_device *dev)
1429 struct drm_nouveau_private *dev_priv = dev->dev_private;
1430 const int impl = dev->pci_device & 0x0ff0;
1432 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1438 nv_match_device(struct drm_device *dev, unsigned device,
1439 unsigned sub_vendor, unsigned sub_device)
1441 return dev->pdev->device == device &&
1442 dev->pdev->subsystem_vendor == sub_vendor &&
1443 dev->pdev->subsystem_device == sub_device;
1446 #define NV_SW 0x0000506e
1447 #define NV_SW_DMA_SEMAPHORE 0x00000060
1448 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1449 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1450 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1451 #define NV_SW_YIELD 0x00000080
1452 #define NV_SW_DMA_VBLSEM 0x0000018c
1453 #define NV_SW_VBLSEM_OFFSET 0x00000400
1454 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1455 #define NV_SW_VBLSEM_RELEASE 0x00000408
1457 #endif /* __NOUVEAU_DRV_H__ */