2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
48 struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
54 #include "nouveau_drm.h"
55 #include "nouveau_reg.h"
56 #include "nouveau_bios.h"
57 #include "nouveau_util.h"
61 #include "nouveau_vm.h"
63 #define MAX_NUM_DCB_ENTRIES 16
65 #define NOUVEAU_MAX_CHANNEL_NR 128
66 #define NOUVEAU_MAX_TILE_NR 15
69 struct drm_device *dev;
71 struct nouveau_vma bar_vma;
73 struct list_head regions;
79 struct nouveau_tile_reg {
85 struct drm_mm_node *tag_mem;
86 struct nouveau_fence *fence;
90 struct ttm_buffer_object bo;
91 struct ttm_placement placement;
93 u32 busy_placements[3];
94 struct ttm_bo_kmap_obj kmap;
95 struct list_head head;
97 /* protected by ttm_bo_reserve() */
98 struct drm_file *reserved_by;
99 struct list_head entry;
101 bool validate_mapped;
103 struct nouveau_channel *channel;
105 struct nouveau_vma vma;
111 struct nouveau_tile_reg *tile;
113 struct drm_gem_object *gem;
117 #define nouveau_bo_tile_layout(nvbo) \
118 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
120 static inline struct nouveau_bo *
121 nouveau_bo(struct ttm_buffer_object *bo)
123 return container_of(bo, struct nouveau_bo, bo);
126 static inline struct nouveau_bo *
127 nouveau_gem_object(struct drm_gem_object *gem)
129 return gem ? gem->driver_private : NULL;
132 /* TODO: submit equivalent to TTM generic API upstream? */
133 static inline void __iomem *
134 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
137 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
138 &nvbo->kmap, &is_iomem);
139 WARN_ON_ONCE(ioptr && !is_iomem);
144 NV_NFORCE = 0x10000000,
145 NV_NFORCE2 = 0x20000000
148 #define NVOBJ_ENGINE_SW 0
149 #define NVOBJ_ENGINE_GR 1
150 #define NVOBJ_ENGINE_PPP 2
151 #define NVOBJ_ENGINE_COPY 3
152 #define NVOBJ_ENGINE_VP 4
153 #define NVOBJ_ENGINE_CRYPT 5
154 #define NVOBJ_ENGINE_BSP 6
155 #define NVOBJ_ENGINE_DISPLAY 0xcafe0001
156 #define NVOBJ_ENGINE_INT 0xdeadbeef
158 #define NVOBJ_FLAG_DONT_MAP (1 << 0)
159 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
160 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
161 #define NVOBJ_FLAG_VM (1 << 3)
163 #define NVOBJ_CINST_GLOBAL 0xdeadbeef
165 struct nouveau_gpuobj {
166 struct drm_device *dev;
167 struct kref refcount;
168 struct list_head list;
183 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
187 struct nouveau_page_flip_state {
188 struct list_head head;
189 struct drm_pending_vblank_event *event;
190 int crtc, bpp, pitch, x, y;
194 enum nouveau_channel_mutex_class {
195 NOUVEAU_UCHANNEL_MUTEX,
196 NOUVEAU_KCHANNEL_MUTEX
199 struct nouveau_channel {
200 struct drm_device *dev;
203 /* references to the channel data structure */
205 /* users of the hardware channel resources, the hardware
206 * context will be kicked off when it reaches zero. */
210 /* owner of this fifo */
211 struct drm_file *file_priv;
212 /* mapping of the fifo itself */
213 struct drm_local_map *map;
215 /* mapping of the regs controling the fifo */
222 /* lock protects the pending list only */
224 struct list_head pending;
226 uint32_t sequence_ack;
227 atomic_t last_sequence_irq;
230 /* DMA push buffer */
231 struct nouveau_gpuobj *pushbuf;
232 struct nouveau_bo *pushbuf_bo;
233 uint32_t pushbuf_base;
235 /* Notifier memory */
236 struct nouveau_bo *notifier_bo;
237 struct drm_mm notifier_heap;
240 struct nouveau_gpuobj *ramfc;
241 struct nouveau_gpuobj *cache;
244 /* XXX may be merge 2 pointers as private data ??? */
245 struct nouveau_gpuobj *ramin_grctx;
246 struct nouveau_gpuobj *crypt_ctx;
250 struct nouveau_vm *vm;
251 struct nouveau_gpuobj *vm_pd;
254 struct nouveau_gpuobj *ramin; /* Private instmem */
255 struct drm_mm ramin_heap; /* Private PRAMIN heap */
256 struct nouveau_ramht *ramht; /* Hash table */
258 /* GPU object info for stuff used in-kernel (mm_enabled) */
260 uint32_t vram_handle;
261 uint32_t gart_handle;
264 /* Push buffer state (only for drm's channel on !mm_enabled) */
270 /* access via pushbuf_bo */
278 uint32_t sw_subchannel[8];
281 struct nouveau_gpuobj *vblsem;
282 uint32_t vblsem_head;
283 uint32_t vblsem_offset;
284 uint32_t vblsem_rval;
285 struct list_head vbl_wait;
286 struct list_head flip;
292 struct drm_info_list info;
296 struct nouveau_instmem_engine {
299 int (*init)(struct drm_device *dev);
300 void (*takedown)(struct drm_device *dev);
301 int (*suspend)(struct drm_device *dev);
302 void (*resume)(struct drm_device *dev);
304 int (*get)(struct nouveau_gpuobj *, u32 size, u32 align);
305 void (*put)(struct nouveau_gpuobj *);
306 int (*map)(struct nouveau_gpuobj *);
307 void (*unmap)(struct nouveau_gpuobj *);
309 void (*flush)(struct drm_device *);
312 struct nouveau_mc_engine {
313 int (*init)(struct drm_device *dev);
314 void (*takedown)(struct drm_device *dev);
317 struct nouveau_timer_engine {
318 int (*init)(struct drm_device *dev);
319 void (*takedown)(struct drm_device *dev);
320 uint64_t (*read)(struct drm_device *dev);
323 struct nouveau_fb_engine {
325 struct drm_mm tag_heap;
328 int (*init)(struct drm_device *dev);
329 void (*takedown)(struct drm_device *dev);
331 void (*init_tile_region)(struct drm_device *dev, int i,
332 uint32_t addr, uint32_t size,
333 uint32_t pitch, uint32_t flags);
334 void (*set_tile_region)(struct drm_device *dev, int i);
335 void (*free_tile_region)(struct drm_device *dev, int i);
338 struct nouveau_fifo_engine {
341 struct nouveau_gpuobj *playlist[2];
344 int (*init)(struct drm_device *);
345 void (*takedown)(struct drm_device *);
347 void (*disable)(struct drm_device *);
348 void (*enable)(struct drm_device *);
349 bool (*reassign)(struct drm_device *, bool enable);
350 bool (*cache_pull)(struct drm_device *dev, bool enable);
352 int (*channel_id)(struct drm_device *);
354 int (*create_context)(struct nouveau_channel *);
355 void (*destroy_context)(struct nouveau_channel *);
356 int (*load_context)(struct nouveau_channel *);
357 int (*unload_context)(struct drm_device *);
358 void (*tlb_flush)(struct drm_device *dev);
361 struct nouveau_pgraph_engine {
366 /* NV2x/NV3x context table (0x400780) */
367 struct nouveau_gpuobj *ctx_table;
369 int (*init)(struct drm_device *);
370 void (*takedown)(struct drm_device *);
372 void (*fifo_access)(struct drm_device *, bool);
374 struct nouveau_channel *(*channel)(struct drm_device *);
375 int (*create_context)(struct nouveau_channel *);
376 void (*destroy_context)(struct nouveau_channel *);
377 int (*load_context)(struct nouveau_channel *);
378 int (*unload_context)(struct drm_device *);
379 void (*tlb_flush)(struct drm_device *dev);
381 void (*set_tile_region)(struct drm_device *dev, int i);
384 struct nouveau_display_engine {
385 int (*early_init)(struct drm_device *);
386 void (*late_takedown)(struct drm_device *);
387 int (*create)(struct drm_device *);
388 int (*init)(struct drm_device *);
389 void (*destroy)(struct drm_device *);
392 struct nouveau_gpio_engine {
395 int (*init)(struct drm_device *);
396 void (*takedown)(struct drm_device *);
398 int (*get)(struct drm_device *, enum dcb_gpio_tag);
399 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
401 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag,
402 void (*)(void *, int), void *);
403 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag,
404 void (*)(void *, int), void *);
405 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
408 struct nouveau_pm_voltage_level {
413 struct nouveau_pm_voltage {
417 struct nouveau_pm_voltage_level *level;
421 #define NOUVEAU_PM_MAX_LEVEL 8
422 struct nouveau_pm_level {
423 struct device_attribute dev_attr;
438 struct nouveau_pm_temp_sensor_constants {
446 struct nouveau_pm_threshold_temp {
452 struct nouveau_pm_memtiming {
463 struct nouveau_pm_memtimings {
465 struct nouveau_pm_memtiming *timing;
469 struct nouveau_pm_engine {
470 struct nouveau_pm_voltage voltage;
471 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
473 struct nouveau_pm_memtimings memtimings;
474 struct nouveau_pm_temp_sensor_constants sensor_constants;
475 struct nouveau_pm_threshold_temp threshold_temp;
477 struct nouveau_pm_level boot;
478 struct nouveau_pm_level *cur;
480 struct device *hwmon;
481 struct notifier_block acpi_nb;
483 int (*clock_get)(struct drm_device *, u32 id);
484 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *,
486 void (*clock_set)(struct drm_device *, void *);
487 int (*voltage_get)(struct drm_device *);
488 int (*voltage_set)(struct drm_device *, int voltage);
489 int (*fanspeed_get)(struct drm_device *);
490 int (*fanspeed_set)(struct drm_device *, int fanspeed);
491 int (*temp_get)(struct drm_device *);
494 struct nouveau_crypt_engine {
497 int (*init)(struct drm_device *);
498 void (*takedown)(struct drm_device *);
499 int (*create_context)(struct nouveau_channel *);
500 void (*destroy_context)(struct nouveau_channel *);
501 void (*tlb_flush)(struct drm_device *dev);
504 struct nouveau_vram_engine {
505 int (*init)(struct drm_device *);
506 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc,
507 u32 type, struct nouveau_vram **);
508 void (*put)(struct drm_device *, struct nouveau_vram **);
510 bool (*flags_valid)(struct drm_device *, u32 tile_flags);
513 struct nouveau_engine {
514 struct nouveau_instmem_engine instmem;
515 struct nouveau_mc_engine mc;
516 struct nouveau_timer_engine timer;
517 struct nouveau_fb_engine fb;
518 struct nouveau_pgraph_engine graph;
519 struct nouveau_fifo_engine fifo;
520 struct nouveau_display_engine display;
521 struct nouveau_gpio_engine gpio;
522 struct nouveau_pm_engine pm;
523 struct nouveau_crypt_engine crypt;
524 struct nouveau_vram_engine vram;
527 struct nouveau_pll_vals {
531 uint8_t N1, M1, N2, M2;
533 uint8_t M1, N1, M2, N2;
538 } __attribute__((packed));
545 enum nv04_fp_display_regs {
555 struct nv04_crtc_reg {
556 unsigned char MiscOutReg;
559 uint8_t Sequencer[5];
561 uint8_t Attribute[21];
562 unsigned char DAC[768];
572 uint32_t crtc_eng_ctrl;
575 uint32_t nv10_cursync;
576 struct nouveau_pll_vals pllvals;
577 uint32_t ramdac_gen_ctrl;
583 uint32_t tv_vsync_delay;
586 uint32_t tv_hsync_delay;
587 uint32_t tv_hsync_delay2;
588 uint32_t fp_horiz_regs[7];
589 uint32_t fp_vert_regs[7];
592 uint32_t dither_regs[6];
596 uint32_t fp_margin_color;
601 uint32_t ctv_regs[38];
604 struct nv04_output_reg {
609 struct nv04_mode_state {
610 struct nv04_crtc_reg crtc_reg[2];
615 enum nouveau_card_type {
625 struct drm_nouveau_private {
626 struct drm_device *dev;
628 /* the card type, takes NV_* as values */
629 enum nouveau_card_type card_type;
630 /* exact chipset, derived from NV_PMC_BOOT_0 */
636 spinlock_t ramin_lock;
640 bool ramin_available;
641 struct drm_mm ramin_heap;
642 struct list_head gpuobj_list;
643 struct list_head classes;
645 struct nouveau_bo *vga_ram;
647 /* interrupt handling */
648 void (*irq_handler[32])(struct drm_device *);
650 struct workqueue_struct *wq;
651 struct work_struct irq_work;
653 struct list_head vbl_waiting;
656 struct drm_global_reference mem_global_ref;
657 struct ttm_bo_global_ref bo_global_ref;
658 struct ttm_bo_device bdev;
659 atomic_t validate_sequence;
665 struct nouveau_bo *bo;
670 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
673 struct nouveau_engine engine;
674 struct nouveau_channel *channel;
676 /* For PFIFO and PGRAPH. */
677 spinlock_t context_switch_lock;
679 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
680 struct nouveau_ramht *ramht;
681 struct nouveau_gpuobj *ramfc;
682 struct nouveau_gpuobj *ramro;
684 uint32_t ramin_rsvd_vram;
688 NOUVEAU_GART_NONE = 0,
696 struct nouveau_gpuobj *sg_ctxdma;
697 struct nouveau_vma vma;
700 /* nv10-nv40 tiling regions */
702 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
706 /* VRAM/fb configuration */
708 uint64_t vram_sys_base;
709 u32 vram_rblock_size;
712 uint64_t fb_available_size;
713 uint64_t fb_mappable_pages;
714 uint64_t fb_aper_free;
717 /* BAR control (NV50-) */
718 struct nouveau_vm *bar1_vm;
719 struct nouveau_vm *bar3_vm;
721 /* G8x/G9x virtual address space */
722 struct nouveau_vm *chan_vm;
726 struct nv04_mode_state mode_reg;
727 struct nv04_mode_state saved_reg;
728 uint32_t saved_vga_font[4][16384];
730 uint32_t dac_users[4];
732 struct nouveau_suspend_resume {
733 uint32_t *ramin_copy;
736 struct backlight_device *backlight;
738 struct nouveau_channel *evo;
741 struct dcb_entry *dcb;
747 struct dentry *channel_root;
750 struct nouveau_fbdev *nfbdev;
751 struct apertures_struct *apertures;
754 static inline struct drm_nouveau_private *
755 nouveau_private(struct drm_device *dev)
757 return dev->dev_private;
760 static inline struct drm_nouveau_private *
761 nouveau_bdev(struct ttm_bo_device *bd)
763 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
767 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
769 struct nouveau_bo *prev;
775 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
777 struct ttm_buffer_object *bo = &prev->bo;
786 extern int nouveau_agpmode;
787 extern int nouveau_duallink;
788 extern int nouveau_uscript_lvds;
789 extern int nouveau_uscript_tmds;
790 extern int nouveau_vram_pushbuf;
791 extern int nouveau_vram_notify;
792 extern int nouveau_fbpercrtc;
793 extern int nouveau_tv_disable;
794 extern char *nouveau_tv_norm;
795 extern int nouveau_reg_debug;
796 extern char *nouveau_vbios;
797 extern int nouveau_ignorelid;
798 extern int nouveau_nofbaccel;
799 extern int nouveau_noaccel;
800 extern int nouveau_force_post;
801 extern int nouveau_override_conntype;
802 extern char *nouveau_perflvl;
803 extern int nouveau_perflvl_wr;
804 extern int nouveau_msi;
806 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
807 extern int nouveau_pci_resume(struct pci_dev *pdev);
809 /* nouveau_state.c */
810 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
811 extern int nouveau_load(struct drm_device *, unsigned long flags);
812 extern int nouveau_firstopen(struct drm_device *);
813 extern void nouveau_lastclose(struct drm_device *);
814 extern int nouveau_unload(struct drm_device *);
815 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
817 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
819 extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout,
820 uint32_t reg, uint32_t mask, uint32_t val);
821 extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout,
822 uint32_t reg, uint32_t mask, uint32_t val);
823 extern bool nouveau_wait_for_idle(struct drm_device *);
824 extern int nouveau_card_init(struct drm_device *);
827 extern int nouveau_mem_vram_init(struct drm_device *);
828 extern void nouveau_mem_vram_fini(struct drm_device *);
829 extern int nouveau_mem_gart_init(struct drm_device *);
830 extern void nouveau_mem_gart_fini(struct drm_device *);
831 extern int nouveau_mem_init_agp(struct drm_device *);
832 extern int nouveau_mem_reset_agp(struct drm_device *);
833 extern void nouveau_mem_close(struct drm_device *);
834 extern int nouveau_mem_detect(struct drm_device *);
835 extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags);
836 extern struct nouveau_tile_reg *nv10_mem_set_tiling(
837 struct drm_device *dev, uint32_t addr, uint32_t size,
838 uint32_t pitch, uint32_t flags);
839 extern void nv10_mem_put_tile_region(struct drm_device *dev,
840 struct nouveau_tile_reg *tile,
841 struct nouveau_fence *fence);
842 extern const struct ttm_mem_type_manager_func nouveau_vram_manager;
844 /* nouveau_notifier.c */
845 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
846 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
847 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
848 int cout, uint32_t *offset);
849 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
850 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
852 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
855 /* nouveau_channel.c */
856 extern struct drm_ioctl_desc nouveau_ioctls[];
857 extern int nouveau_max_ioctl;
858 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
859 extern int nouveau_channel_alloc(struct drm_device *dev,
860 struct nouveau_channel **chan,
861 struct drm_file *file_priv,
862 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
863 extern struct nouveau_channel *
864 nouveau_channel_get_unlocked(struct nouveau_channel *);
865 extern struct nouveau_channel *
866 nouveau_channel_get(struct drm_device *, struct drm_file *, int id);
867 extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
868 extern void nouveau_channel_put(struct nouveau_channel **);
869 extern void nouveau_channel_ref(struct nouveau_channel *chan,
870 struct nouveau_channel **pchan);
871 extern void nouveau_channel_idle(struct nouveau_channel *chan);
873 /* nouveau_object.c */
874 #define NVOBJ_CLASS(d,c,e) do { \
875 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
880 #define NVOBJ_MTHD(d,c,m,e) do { \
881 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
886 extern int nouveau_gpuobj_early_init(struct drm_device *);
887 extern int nouveau_gpuobj_init(struct drm_device *);
888 extern void nouveau_gpuobj_takedown(struct drm_device *);
889 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
890 extern void nouveau_gpuobj_resume(struct drm_device *dev);
891 extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
892 extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
893 int (*exec)(struct nouveau_channel *,
894 u32 class, u32 mthd, u32 data));
895 extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
896 extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32);
897 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
898 uint32_t vram_h, uint32_t tt_h);
899 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
900 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
901 uint32_t size, int align, uint32_t flags,
902 struct nouveau_gpuobj **);
903 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
904 struct nouveau_gpuobj **);
905 extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
907 struct nouveau_gpuobj **);
908 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
909 uint64_t offset, uint64_t size, int access,
910 int target, struct nouveau_gpuobj **);
911 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class);
912 extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base,
913 u64 size, int target, int access, u32 type,
914 u32 comp, struct nouveau_gpuobj **pobj);
915 extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset,
916 int class, u64 base, u64 size, int target,
917 int access, u32 type, u32 comp);
918 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
920 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
924 extern int nouveau_irq_init(struct drm_device *);
925 extern void nouveau_irq_fini(struct drm_device *);
926 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
927 extern void nouveau_irq_register(struct drm_device *, int status_bit,
928 void (*)(struct drm_device *));
929 extern void nouveau_irq_unregister(struct drm_device *, int status_bit);
930 extern void nouveau_irq_preinstall(struct drm_device *);
931 extern int nouveau_irq_postinstall(struct drm_device *);
932 extern void nouveau_irq_uninstall(struct drm_device *);
934 /* nouveau_sgdma.c */
935 extern int nouveau_sgdma_init(struct drm_device *);
936 extern void nouveau_sgdma_takedown(struct drm_device *);
937 extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
939 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
941 /* nouveau_debugfs.c */
942 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
943 extern int nouveau_debugfs_init(struct drm_minor *);
944 extern void nouveau_debugfs_takedown(struct drm_minor *);
945 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
946 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
949 nouveau_debugfs_init(struct drm_minor *minor)
954 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
959 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
965 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
971 extern void nouveau_dma_pre_init(struct nouveau_channel *);
972 extern int nouveau_dma_init(struct nouveau_channel *);
973 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
976 #define ROM_BIOS_PAGE 4096
977 #if defined(CONFIG_ACPI)
978 void nouveau_register_dsm_handler(void);
979 void nouveau_unregister_dsm_handler(void);
980 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
981 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
982 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
984 static inline void nouveau_register_dsm_handler(void) {}
985 static inline void nouveau_unregister_dsm_handler(void) {}
986 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
987 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
988 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
991 /* nouveau_backlight.c */
992 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
993 extern int nouveau_backlight_init(struct drm_device *);
994 extern void nouveau_backlight_exit(struct drm_device *);
996 static inline int nouveau_backlight_init(struct drm_device *dev)
1001 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
1004 /* nouveau_bios.c */
1005 extern int nouveau_bios_init(struct drm_device *);
1006 extern void nouveau_bios_takedown(struct drm_device *dev);
1007 extern int nouveau_run_vbios_init(struct drm_device *);
1008 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
1009 struct dcb_entry *);
1010 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
1012 extern struct dcb_connector_table_entry *
1013 nouveau_bios_connector_entry(struct drm_device *, int index);
1014 extern u32 get_pll_register(struct drm_device *, enum pll_types);
1015 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
1017 extern int nouveau_bios_run_display_table(struct drm_device *,
1019 uint32_t script, int pxclk);
1020 extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
1022 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
1023 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
1024 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
1025 bool *dl, bool *if_is_24bit);
1026 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
1027 int head, int pxclk);
1028 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
1029 enum LVDS_script, int pxclk);
1032 int nouveau_ttm_global_init(struct drm_nouveau_private *);
1033 void nouveau_ttm_global_release(struct drm_nouveau_private *);
1034 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
1037 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
1038 uint8_t *data, int data_nr);
1039 bool nouveau_dp_detect(struct drm_encoder *);
1040 bool nouveau_dp_link_train(struct drm_encoder *);
1043 extern int nv04_fb_init(struct drm_device *);
1044 extern void nv04_fb_takedown(struct drm_device *);
1047 extern int nv10_fb_init(struct drm_device *);
1048 extern void nv10_fb_takedown(struct drm_device *);
1049 extern void nv10_fb_init_tile_region(struct drm_device *dev, int i,
1050 uint32_t addr, uint32_t size,
1051 uint32_t pitch, uint32_t flags);
1052 extern void nv10_fb_set_tile_region(struct drm_device *dev, int i);
1053 extern void nv10_fb_free_tile_region(struct drm_device *dev, int i);
1056 extern int nv30_fb_init(struct drm_device *);
1057 extern void nv30_fb_takedown(struct drm_device *);
1058 extern void nv30_fb_init_tile_region(struct drm_device *dev, int i,
1059 uint32_t addr, uint32_t size,
1060 uint32_t pitch, uint32_t flags);
1061 extern void nv30_fb_free_tile_region(struct drm_device *dev, int i);
1064 extern int nv40_fb_init(struct drm_device *);
1065 extern void nv40_fb_takedown(struct drm_device *);
1066 extern void nv40_fb_set_tile_region(struct drm_device *dev, int i);
1069 extern int nv50_fb_init(struct drm_device *);
1070 extern void nv50_fb_takedown(struct drm_device *);
1071 extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *);
1074 extern int nvc0_fb_init(struct drm_device *);
1075 extern void nvc0_fb_takedown(struct drm_device *);
1078 extern int nv04_fifo_init(struct drm_device *);
1079 extern void nv04_fifo_fini(struct drm_device *);
1080 extern void nv04_fifo_disable(struct drm_device *);
1081 extern void nv04_fifo_enable(struct drm_device *);
1082 extern bool nv04_fifo_reassign(struct drm_device *, bool);
1083 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
1084 extern int nv04_fifo_channel_id(struct drm_device *);
1085 extern int nv04_fifo_create_context(struct nouveau_channel *);
1086 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
1087 extern int nv04_fifo_load_context(struct nouveau_channel *);
1088 extern int nv04_fifo_unload_context(struct drm_device *);
1089 extern void nv04_fifo_isr(struct drm_device *);
1092 extern int nv10_fifo_init(struct drm_device *);
1093 extern int nv10_fifo_channel_id(struct drm_device *);
1094 extern int nv10_fifo_create_context(struct nouveau_channel *);
1095 extern int nv10_fifo_load_context(struct nouveau_channel *);
1096 extern int nv10_fifo_unload_context(struct drm_device *);
1099 extern int nv40_fifo_init(struct drm_device *);
1100 extern int nv40_fifo_create_context(struct nouveau_channel *);
1101 extern int nv40_fifo_load_context(struct nouveau_channel *);
1102 extern int nv40_fifo_unload_context(struct drm_device *);
1105 extern int nv50_fifo_init(struct drm_device *);
1106 extern void nv50_fifo_takedown(struct drm_device *);
1107 extern int nv50_fifo_channel_id(struct drm_device *);
1108 extern int nv50_fifo_create_context(struct nouveau_channel *);
1109 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1110 extern int nv50_fifo_load_context(struct nouveau_channel *);
1111 extern int nv50_fifo_unload_context(struct drm_device *);
1112 extern void nv50_fifo_tlb_flush(struct drm_device *dev);
1115 extern int nvc0_fifo_init(struct drm_device *);
1116 extern void nvc0_fifo_takedown(struct drm_device *);
1117 extern void nvc0_fifo_disable(struct drm_device *);
1118 extern void nvc0_fifo_enable(struct drm_device *);
1119 extern bool nvc0_fifo_reassign(struct drm_device *, bool);
1120 extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1121 extern int nvc0_fifo_channel_id(struct drm_device *);
1122 extern int nvc0_fifo_create_context(struct nouveau_channel *);
1123 extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1124 extern int nvc0_fifo_load_context(struct nouveau_channel *);
1125 extern int nvc0_fifo_unload_context(struct drm_device *);
1128 extern int nv04_graph_init(struct drm_device *);
1129 extern void nv04_graph_takedown(struct drm_device *);
1130 extern void nv04_graph_fifo_access(struct drm_device *, bool);
1131 extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
1132 extern int nv04_graph_create_context(struct nouveau_channel *);
1133 extern void nv04_graph_destroy_context(struct nouveau_channel *);
1134 extern int nv04_graph_load_context(struct nouveau_channel *);
1135 extern int nv04_graph_unload_context(struct drm_device *);
1136 extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
1137 u32 class, u32 mthd, u32 data);
1138 extern struct nouveau_bitfield nv04_graph_nsource[];
1141 extern int nv10_graph_init(struct drm_device *);
1142 extern void nv10_graph_takedown(struct drm_device *);
1143 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1144 extern int nv10_graph_create_context(struct nouveau_channel *);
1145 extern void nv10_graph_destroy_context(struct nouveau_channel *);
1146 extern int nv10_graph_load_context(struct nouveau_channel *);
1147 extern int nv10_graph_unload_context(struct drm_device *);
1148 extern void nv10_graph_set_tile_region(struct drm_device *dev, int i);
1149 extern struct nouveau_bitfield nv10_graph_intr[];
1150 extern struct nouveau_bitfield nv10_graph_nstatus[];
1153 extern int nv20_graph_create_context(struct nouveau_channel *);
1154 extern void nv20_graph_destroy_context(struct nouveau_channel *);
1155 extern int nv20_graph_load_context(struct nouveau_channel *);
1156 extern int nv20_graph_unload_context(struct drm_device *);
1157 extern int nv20_graph_init(struct drm_device *);
1158 extern void nv20_graph_takedown(struct drm_device *);
1159 extern int nv30_graph_init(struct drm_device *);
1160 extern void nv20_graph_set_tile_region(struct drm_device *dev, int i);
1163 extern int nv40_graph_init(struct drm_device *);
1164 extern void nv40_graph_takedown(struct drm_device *);
1165 extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1166 extern int nv40_graph_create_context(struct nouveau_channel *);
1167 extern void nv40_graph_destroy_context(struct nouveau_channel *);
1168 extern int nv40_graph_load_context(struct nouveau_channel *);
1169 extern int nv40_graph_unload_context(struct drm_device *);
1170 extern void nv40_grctx_init(struct nouveau_grctx *);
1171 extern void nv40_graph_set_tile_region(struct drm_device *dev, int i);
1174 extern int nv50_graph_init(struct drm_device *);
1175 extern void nv50_graph_takedown(struct drm_device *);
1176 extern void nv50_graph_fifo_access(struct drm_device *, bool);
1177 extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1178 extern int nv50_graph_create_context(struct nouveau_channel *);
1179 extern void nv50_graph_destroy_context(struct nouveau_channel *);
1180 extern int nv50_graph_load_context(struct nouveau_channel *);
1181 extern int nv50_graph_unload_context(struct drm_device *);
1182 extern int nv50_grctx_init(struct nouveau_grctx *);
1183 extern void nv50_graph_tlb_flush(struct drm_device *dev);
1184 extern void nv86_graph_tlb_flush(struct drm_device *dev);
1187 extern int nvc0_graph_init(struct drm_device *);
1188 extern void nvc0_graph_takedown(struct drm_device *);
1189 extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1190 extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1191 extern int nvc0_graph_create_context(struct nouveau_channel *);
1192 extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1193 extern int nvc0_graph_load_context(struct nouveau_channel *);
1194 extern int nvc0_graph_unload_context(struct drm_device *);
1197 extern int nv84_crypt_init(struct drm_device *dev);
1198 extern void nv84_crypt_fini(struct drm_device *dev);
1199 extern int nv84_crypt_create_context(struct nouveau_channel *);
1200 extern void nv84_crypt_destroy_context(struct nouveau_channel *);
1201 extern void nv84_crypt_tlb_flush(struct drm_device *dev);
1203 /* nv04_instmem.c */
1204 extern int nv04_instmem_init(struct drm_device *);
1205 extern void nv04_instmem_takedown(struct drm_device *);
1206 extern int nv04_instmem_suspend(struct drm_device *);
1207 extern void nv04_instmem_resume(struct drm_device *);
1208 extern int nv04_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align);
1209 extern void nv04_instmem_put(struct nouveau_gpuobj *);
1210 extern int nv04_instmem_map(struct nouveau_gpuobj *);
1211 extern void nv04_instmem_unmap(struct nouveau_gpuobj *);
1212 extern void nv04_instmem_flush(struct drm_device *);
1214 /* nv50_instmem.c */
1215 extern int nv50_instmem_init(struct drm_device *);
1216 extern void nv50_instmem_takedown(struct drm_device *);
1217 extern int nv50_instmem_suspend(struct drm_device *);
1218 extern void nv50_instmem_resume(struct drm_device *);
1219 extern int nv50_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align);
1220 extern void nv50_instmem_put(struct nouveau_gpuobj *);
1221 extern int nv50_instmem_map(struct nouveau_gpuobj *);
1222 extern void nv50_instmem_unmap(struct nouveau_gpuobj *);
1223 extern void nv50_instmem_flush(struct drm_device *);
1224 extern void nv84_instmem_flush(struct drm_device *);
1226 /* nvc0_instmem.c */
1227 extern int nvc0_instmem_init(struct drm_device *);
1228 extern void nvc0_instmem_takedown(struct drm_device *);
1229 extern int nvc0_instmem_suspend(struct drm_device *);
1230 extern void nvc0_instmem_resume(struct drm_device *);
1231 extern int nvc0_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align);
1232 extern void nvc0_instmem_put(struct nouveau_gpuobj *);
1233 extern int nvc0_instmem_map(struct nouveau_gpuobj *);
1234 extern void nvc0_instmem_unmap(struct nouveau_gpuobj *);
1235 extern void nvc0_instmem_flush(struct drm_device *);
1238 extern int nv04_mc_init(struct drm_device *);
1239 extern void nv04_mc_takedown(struct drm_device *);
1242 extern int nv40_mc_init(struct drm_device *);
1243 extern void nv40_mc_takedown(struct drm_device *);
1246 extern int nv50_mc_init(struct drm_device *);
1247 extern void nv50_mc_takedown(struct drm_device *);
1250 extern int nv04_timer_init(struct drm_device *);
1251 extern uint64_t nv04_timer_read(struct drm_device *);
1252 extern void nv04_timer_takedown(struct drm_device *);
1254 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1258 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1259 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1260 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1261 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1262 extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1265 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1266 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1267 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1269 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1270 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1273 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1274 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1277 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1279 /* nv04_display.c */
1280 extern int nv04_display_early_init(struct drm_device *);
1281 extern void nv04_display_late_takedown(struct drm_device *);
1282 extern int nv04_display_create(struct drm_device *);
1283 extern int nv04_display_init(struct drm_device *);
1284 extern void nv04_display_destroy(struct drm_device *);
1287 extern int nv04_crtc_create(struct drm_device *, int index);
1290 extern struct ttm_bo_driver nouveau_bo_driver;
1291 extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1292 int size, int align, uint32_t flags,
1293 uint32_t tile_mode, uint32_t tile_flags,
1294 bool no_vm, bool mappable, struct nouveau_bo **);
1295 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1296 extern int nouveau_bo_unpin(struct nouveau_bo *);
1297 extern int nouveau_bo_map(struct nouveau_bo *);
1298 extern void nouveau_bo_unmap(struct nouveau_bo *);
1299 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1301 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1302 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1303 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1304 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1305 extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *);
1306 extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible,
1307 bool no_wait_reserve, bool no_wait_gpu);
1309 /* nouveau_fence.c */
1310 struct nouveau_fence;
1311 extern int nouveau_fence_init(struct drm_device *);
1312 extern void nouveau_fence_fini(struct drm_device *);
1313 extern int nouveau_fence_channel_init(struct nouveau_channel *);
1314 extern void nouveau_fence_channel_fini(struct nouveau_channel *);
1315 extern void nouveau_fence_update(struct nouveau_channel *);
1316 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1318 extern int nouveau_fence_emit(struct nouveau_fence *);
1319 extern void nouveau_fence_work(struct nouveau_fence *fence,
1320 void (*work)(void *priv, bool signalled),
1322 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1324 extern bool __nouveau_fence_signalled(void *obj, void *arg);
1325 extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1326 extern int __nouveau_fence_flush(void *obj, void *arg);
1327 extern void __nouveau_fence_unref(void **obj);
1328 extern void *__nouveau_fence_ref(void *obj);
1330 static inline bool nouveau_fence_signalled(struct nouveau_fence *obj)
1332 return __nouveau_fence_signalled(obj, NULL);
1335 nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr)
1337 return __nouveau_fence_wait(obj, NULL, lazy, intr);
1339 extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
1340 static inline int nouveau_fence_flush(struct nouveau_fence *obj)
1342 return __nouveau_fence_flush(obj, NULL);
1344 static inline void nouveau_fence_unref(struct nouveau_fence **obj)
1346 __nouveau_fence_unref((void **)obj);
1348 static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj)
1350 return __nouveau_fence_ref(obj);
1354 extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1355 int size, int align, uint32_t flags,
1356 uint32_t tile_mode, uint32_t tile_flags,
1357 bool no_vm, bool mappable, struct nouveau_bo **);
1358 extern int nouveau_gem_object_new(struct drm_gem_object *);
1359 extern void nouveau_gem_object_del(struct drm_gem_object *);
1360 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1362 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1364 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1366 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1368 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1371 /* nouveau_display.c */
1372 int nouveau_vblank_enable(struct drm_device *dev, int crtc);
1373 void nouveau_vblank_disable(struct drm_device *dev, int crtc);
1374 int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1375 struct drm_pending_vblank_event *event);
1376 int nouveau_finish_page_flip(struct nouveau_channel *,
1377 struct nouveau_page_flip_state *);
1380 int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1381 int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1384 int nv50_gpio_init(struct drm_device *dev);
1385 void nv50_gpio_fini(struct drm_device *dev);
1386 int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1387 int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1388 int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag,
1389 void (*)(void *, int), void *);
1390 void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag,
1391 void (*)(void *, int), void *);
1392 bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
1395 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1396 int *N1, int *M1, int *N2, int *M2, int *P);
1397 int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1398 int clk, int *N, int *fN, int *M, int *P);
1400 #ifndef ioread32_native
1402 #define ioread16_native ioread16be
1403 #define iowrite16_native iowrite16be
1404 #define ioread32_native ioread32be
1405 #define iowrite32_native iowrite32be
1406 #else /* def __BIG_ENDIAN */
1407 #define ioread16_native ioread16
1408 #define iowrite16_native iowrite16
1409 #define ioread32_native ioread32
1410 #define iowrite32_native iowrite32
1411 #endif /* def __BIG_ENDIAN else */
1412 #endif /* !ioread32_native */
1414 /* channel control reg access */
1415 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1417 return ioread32_native(chan->user + reg);
1420 static inline void nvchan_wr32(struct nouveau_channel *chan,
1421 unsigned reg, u32 val)
1423 iowrite32_native(val, chan->user + reg);
1426 /* register access */
1427 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1429 struct drm_nouveau_private *dev_priv = dev->dev_private;
1430 return ioread32_native(dev_priv->mmio + reg);
1433 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1435 struct drm_nouveau_private *dev_priv = dev->dev_private;
1436 iowrite32_native(val, dev_priv->mmio + reg);
1439 static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1441 u32 tmp = nv_rd32(dev, reg);
1442 nv_wr32(dev, reg, (tmp & ~mask) | val);
1446 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1448 struct drm_nouveau_private *dev_priv = dev->dev_private;
1449 return ioread8(dev_priv->mmio + reg);
1452 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1454 struct drm_nouveau_private *dev_priv = dev->dev_private;
1455 iowrite8(val, dev_priv->mmio + reg);
1458 #define nv_wait(dev, reg, mask, val) \
1459 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val))
1460 #define nv_wait_ne(dev, reg, mask, val) \
1461 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val))
1464 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1466 struct drm_nouveau_private *dev_priv = dev->dev_private;
1467 return ioread32_native(dev_priv->ramin + offset);
1470 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1472 struct drm_nouveau_private *dev_priv = dev->dev_private;
1473 iowrite32_native(val, dev_priv->ramin + offset);
1477 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1478 extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
1482 * Argument d is (struct drm_device *).
1484 #define NV_PRINTK(level, d, fmt, arg...) \
1485 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1486 pci_name(d->pdev), ##arg)
1487 #ifndef NV_DEBUG_NOTRACE
1488 #define NV_DEBUG(d, fmt, arg...) do { \
1489 if (drm_debug & DRM_UT_DRIVER) { \
1490 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1494 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1495 if (drm_debug & DRM_UT_KMS) { \
1496 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1501 #define NV_DEBUG(d, fmt, arg...) do { \
1502 if (drm_debug & DRM_UT_DRIVER) \
1503 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1505 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1506 if (drm_debug & DRM_UT_KMS) \
1507 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1510 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1511 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1512 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1513 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1514 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1516 /* nouveau_reg_debug bitmask */
1518 NOUVEAU_REG_DEBUG_MC = 0x1,
1519 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1520 NOUVEAU_REG_DEBUG_FB = 0x4,
1521 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1522 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1523 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1524 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1525 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1526 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1527 NOUVEAU_REG_DEBUG_EVO = 0x200,
1530 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1531 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1532 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1536 nv_two_heads(struct drm_device *dev)
1538 struct drm_nouveau_private *dev_priv = dev->dev_private;
1539 const int impl = dev->pci_device & 0x0ff0;
1541 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1542 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1549 nv_gf4_disp_arch(struct drm_device *dev)
1551 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1555 nv_two_reg_pll(struct drm_device *dev)
1557 struct drm_nouveau_private *dev_priv = dev->dev_private;
1558 const int impl = dev->pci_device & 0x0ff0;
1560 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1566 nv_match_device(struct drm_device *dev, unsigned device,
1567 unsigned sub_vendor, unsigned sub_device)
1569 return dev->pdev->device == device &&
1570 dev->pdev->subsystem_vendor == sub_vendor &&
1571 dev->pdev->subsystem_device == sub_device;
1574 /* memory type/access flags, do not match hardware values */
1575 #define NV_MEM_ACCESS_RO 1
1576 #define NV_MEM_ACCESS_WO 2
1577 #define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO)
1578 #define NV_MEM_ACCESS_SYS 4
1579 #define NV_MEM_ACCESS_VM 8
1581 #define NV_MEM_TARGET_VRAM 0
1582 #define NV_MEM_TARGET_PCI 1
1583 #define NV_MEM_TARGET_PCI_NOSNOOP 2
1584 #define NV_MEM_TARGET_VM 3
1585 #define NV_MEM_TARGET_GART 4
1587 #define NV_MEM_TYPE_VM 0x7f
1588 #define NV_MEM_COMP_VM 0x03
1590 /* NV_SW object class */
1591 #define NV_SW 0x0000506e
1592 #define NV_SW_DMA_SEMAPHORE 0x00000060
1593 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1594 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1595 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1596 #define NV_SW_YIELD 0x00000080
1597 #define NV_SW_DMA_VBLSEM 0x0000018c
1598 #define NV_SW_VBLSEM_OFFSET 0x00000400
1599 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1600 #define NV_SW_VBLSEM_RELEASE 0x00000408
1601 #define NV_SW_PAGE_FLIP 0x00000500
1603 #endif /* __NOUVEAU_DRV_H__ */