2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
48 struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
54 #include "nouveau_drm.h"
55 #include "nouveau_reg.h"
56 #include "nouveau_bios.h"
59 #define MAX_NUM_DCB_ENTRIES 16
61 #define NOUVEAU_MAX_CHANNEL_NR 128
62 #define NOUVEAU_MAX_TILE_NR 15
64 #define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65 #define NV50_VM_BLOCK (512*1024*1024ULL)
66 #define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
68 struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
79 u32 busy_placements[3];
80 struct ttm_bo_kmap_obj kmap;
81 struct list_head head;
83 /* protected by ttm_bo_reserve() */
84 struct drm_file *reserved_by;
85 struct list_head entry;
89 struct nouveau_channel *channel;
96 struct nouveau_tile_reg *tile;
98 struct drm_gem_object *gem;
99 struct drm_file *cpu_filp;
103 #define nouveau_bo_tile_layout(nvbo) \
104 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
106 static inline struct nouveau_bo *
107 nouveau_bo(struct ttm_buffer_object *bo)
109 return container_of(bo, struct nouveau_bo, bo);
112 static inline struct nouveau_bo *
113 nouveau_gem_object(struct drm_gem_object *gem)
115 return gem ? gem->driver_private : NULL;
118 /* TODO: submit equivalent to TTM generic API upstream? */
119 static inline void __iomem *
120 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
123 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
124 &nvbo->kmap, &is_iomem);
125 WARN_ON_ONCE(ioptr && !is_iomem);
130 NV_NFORCE = 0x10000000,
131 NV_NFORCE2 = 0x20000000
134 #define NVOBJ_ENGINE_SW 0
135 #define NVOBJ_ENGINE_GR 1
136 #define NVOBJ_ENGINE_DISPLAY 2
137 #define NVOBJ_ENGINE_INT 0xdeadbeef
139 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
140 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
141 struct nouveau_gpuobj {
142 struct drm_device *dev;
143 struct kref refcount;
144 struct list_head list;
146 struct drm_mm_node *im_pramin;
147 struct nouveau_bo *im_backing;
148 uint32_t *im_backing_suspend;
161 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
165 struct nouveau_channel {
166 struct drm_device *dev;
169 /* owner of this fifo */
170 struct drm_file *file_priv;
171 /* mapping of the fifo itself */
172 struct drm_local_map *map;
174 /* mapping of the regs controling the fifo */
181 /* lock protects the pending list only */
183 struct list_head pending;
185 uint32_t sequence_ack;
186 atomic_t last_sequence_irq;
189 /* DMA push buffer */
190 struct nouveau_gpuobj *pushbuf;
191 struct nouveau_bo *pushbuf_bo;
192 uint32_t pushbuf_base;
194 /* Notifier memory */
195 struct nouveau_bo *notifier_bo;
196 struct drm_mm notifier_heap;
199 struct nouveau_gpuobj *ramfc;
200 struct nouveau_gpuobj *cache;
203 /* XXX may be merge 2 pointers as private data ??? */
204 struct nouveau_gpuobj *ramin_grctx;
208 struct nouveau_gpuobj *vm_pd;
209 struct nouveau_gpuobj *vm_gart_pt;
210 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
213 struct nouveau_gpuobj *ramin; /* Private instmem */
214 struct drm_mm ramin_heap; /* Private PRAMIN heap */
215 struct nouveau_ramht *ramht; /* Hash table */
217 /* GPU object info for stuff used in-kernel (mm_enabled) */
219 uint32_t vram_handle;
220 uint32_t gart_handle;
223 /* Push buffer state (only for drm's channel on !mm_enabled) */
229 /* access via pushbuf_bo */
237 uint32_t sw_subchannel[8];
240 struct nouveau_gpuobj *vblsem;
241 uint32_t vblsem_offset;
242 uint32_t vblsem_rval;
243 struct list_head vbl_wait;
249 struct drm_info_list info;
253 struct nouveau_instmem_engine {
256 int (*init)(struct drm_device *dev);
257 void (*takedown)(struct drm_device *dev);
258 int (*suspend)(struct drm_device *dev);
259 void (*resume)(struct drm_device *dev);
261 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
263 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
264 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
265 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
266 void (*flush)(struct drm_device *);
269 struct nouveau_mc_engine {
270 int (*init)(struct drm_device *dev);
271 void (*takedown)(struct drm_device *dev);
274 struct nouveau_timer_engine {
275 int (*init)(struct drm_device *dev);
276 void (*takedown)(struct drm_device *dev);
277 uint64_t (*read)(struct drm_device *dev);
280 struct nouveau_fb_engine {
283 int (*init)(struct drm_device *dev);
284 void (*takedown)(struct drm_device *dev);
286 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
287 uint32_t size, uint32_t pitch);
290 struct nouveau_fifo_engine {
293 struct nouveau_gpuobj *playlist[2];
296 int (*init)(struct drm_device *);
297 void (*takedown)(struct drm_device *);
299 void (*disable)(struct drm_device *);
300 void (*enable)(struct drm_device *);
301 bool (*reassign)(struct drm_device *, bool enable);
302 bool (*cache_pull)(struct drm_device *dev, bool enable);
304 int (*channel_id)(struct drm_device *);
306 int (*create_context)(struct nouveau_channel *);
307 void (*destroy_context)(struct nouveau_channel *);
308 int (*load_context)(struct nouveau_channel *);
309 int (*unload_context)(struct drm_device *);
310 void (*tlb_flush)(struct drm_device *dev);
313 struct nouveau_pgraph_object_method {
315 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
319 struct nouveau_pgraph_object_class {
322 struct nouveau_pgraph_object_method *methods;
325 struct nouveau_pgraph_engine {
326 struct nouveau_pgraph_object_class *grclass;
330 /* NV2x/NV3x context table (0x400780) */
331 struct nouveau_gpuobj *ctx_table;
333 int (*init)(struct drm_device *);
334 void (*takedown)(struct drm_device *);
336 void (*fifo_access)(struct drm_device *, bool);
338 struct nouveau_channel *(*channel)(struct drm_device *);
339 int (*create_context)(struct nouveau_channel *);
340 void (*destroy_context)(struct nouveau_channel *);
341 int (*load_context)(struct nouveau_channel *);
342 int (*unload_context)(struct drm_device *);
343 void (*tlb_flush)(struct drm_device *dev);
345 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
346 uint32_t size, uint32_t pitch);
349 struct nouveau_display_engine {
350 int (*early_init)(struct drm_device *);
351 void (*late_takedown)(struct drm_device *);
352 int (*create)(struct drm_device *);
353 int (*init)(struct drm_device *);
354 void (*destroy)(struct drm_device *);
357 struct nouveau_gpio_engine {
358 int (*init)(struct drm_device *);
359 void (*takedown)(struct drm_device *);
361 int (*get)(struct drm_device *, enum dcb_gpio_tag);
362 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
364 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
367 struct nouveau_pm_voltage_level {
372 struct nouveau_pm_voltage {
376 struct nouveau_pm_voltage_level *level;
380 #define NOUVEAU_PM_MAX_LEVEL 8
381 struct nouveau_pm_level {
382 struct device_attribute dev_attr;
397 struct nouveau_pm_temp_sensor_constants {
405 struct nouveau_pm_threshold_temp {
411 struct nouveau_pm_memtiming {
422 struct nouveau_pm_memtimings {
424 struct nouveau_pm_memtiming *timing;
428 struct nouveau_pm_engine {
429 struct nouveau_pm_voltage voltage;
430 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
432 struct nouveau_pm_memtimings memtimings;
433 struct nouveau_pm_temp_sensor_constants sensor_constants;
434 struct nouveau_pm_threshold_temp threshold_temp;
436 struct nouveau_pm_level boot;
437 struct nouveau_pm_level *cur;
439 struct device *hwmon;
441 int (*clock_get)(struct drm_device *, u32 id);
442 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *,
444 void (*clock_set)(struct drm_device *, void *);
445 int (*voltage_get)(struct drm_device *);
446 int (*voltage_set)(struct drm_device *, int voltage);
447 int (*fanspeed_get)(struct drm_device *);
448 int (*fanspeed_set)(struct drm_device *, int fanspeed);
449 int (*temp_get)(struct drm_device *);
452 struct nouveau_engine {
453 struct nouveau_instmem_engine instmem;
454 struct nouveau_mc_engine mc;
455 struct nouveau_timer_engine timer;
456 struct nouveau_fb_engine fb;
457 struct nouveau_pgraph_engine graph;
458 struct nouveau_fifo_engine fifo;
459 struct nouveau_display_engine display;
460 struct nouveau_gpio_engine gpio;
461 struct nouveau_pm_engine pm;
464 struct nouveau_pll_vals {
468 uint8_t N1, M1, N2, M2;
470 uint8_t M1, N1, M2, N2;
475 } __attribute__((packed));
482 enum nv04_fp_display_regs {
492 struct nv04_crtc_reg {
493 unsigned char MiscOutReg;
496 uint8_t Sequencer[5];
498 uint8_t Attribute[21];
499 unsigned char DAC[768];
509 uint32_t crtc_eng_ctrl;
512 uint32_t nv10_cursync;
513 struct nouveau_pll_vals pllvals;
514 uint32_t ramdac_gen_ctrl;
520 uint32_t tv_vsync_delay;
523 uint32_t tv_hsync_delay;
524 uint32_t tv_hsync_delay2;
525 uint32_t fp_horiz_regs[7];
526 uint32_t fp_vert_regs[7];
529 uint32_t dither_regs[6];
533 uint32_t fp_margin_color;
538 uint32_t ctv_regs[38];
541 struct nv04_output_reg {
546 struct nv04_mode_state {
547 struct nv04_crtc_reg crtc_reg[2];
552 enum nouveau_card_type {
562 struct drm_nouveau_private {
563 struct drm_device *dev;
565 /* the card type, takes NV_* as values */
566 enum nouveau_card_type card_type;
567 /* exact chipset, derived from NV_PMC_BOOT_0 */
573 spinlock_t ramin_lock;
577 bool ramin_available;
578 struct drm_mm ramin_heap;
579 struct list_head gpuobj_list;
581 struct nouveau_bo *vga_ram;
583 struct workqueue_struct *wq;
584 struct work_struct irq_work;
585 struct work_struct hpd_work;
593 struct list_head vbl_waiting;
596 struct drm_global_reference mem_global_ref;
597 struct ttm_bo_global_ref bo_global_ref;
598 struct ttm_bo_device bdev;
599 atomic_t validate_sequence;
605 struct nouveau_bo *bo;
608 int fifo_alloc_count;
609 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
611 struct nouveau_engine engine;
612 struct nouveau_channel *channel;
614 /* For PFIFO and PGRAPH. */
615 spinlock_t context_switch_lock;
617 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
618 struct nouveau_ramht *ramht;
619 struct nouveau_gpuobj *ramfc;
620 struct nouveau_gpuobj *ramro;
622 uint32_t ramin_rsvd_vram;
626 NOUVEAU_GART_NONE = 0,
634 struct nouveau_gpuobj *sg_ctxdma;
635 struct page *sg_dummy_page;
636 dma_addr_t sg_dummy_bus;
639 /* nv10-nv40 tiling regions */
640 struct nouveau_tile_reg tile[NOUVEAU_MAX_TILE_NR];
642 /* VRAM/fb configuration */
644 uint64_t vram_sys_base;
645 u32 vram_rblock_size;
648 uint64_t fb_available_size;
649 uint64_t fb_mappable_pages;
650 uint64_t fb_aper_free;
653 /* G8x/G9x virtual address space */
654 uint64_t vm_gart_base;
655 uint64_t vm_gart_size;
656 uint64_t vm_vram_base;
657 uint64_t vm_vram_size;
659 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
664 struct nv04_mode_state mode_reg;
665 struct nv04_mode_state saved_reg;
666 uint32_t saved_vga_font[4][16384];
668 uint32_t dac_users[4];
670 struct nouveau_suspend_resume {
671 uint32_t *ramin_copy;
674 struct backlight_device *backlight;
676 struct nouveau_channel *evo;
678 struct dcb_entry *dcb;
684 struct dentry *channel_root;
687 struct nouveau_fbdev *nfbdev;
688 struct apertures_struct *apertures;
691 static inline struct drm_nouveau_private *
692 nouveau_private(struct drm_device *dev)
694 return dev->dev_private;
697 static inline struct drm_nouveau_private *
698 nouveau_bdev(struct ttm_bo_device *bd)
700 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
704 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
706 struct nouveau_bo *prev;
712 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
714 struct ttm_buffer_object *bo = &prev->bo;
722 #define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
723 struct drm_nouveau_private *nv = dev->dev_private; \
724 if (!nouveau_channel_owner(dev, (cl), (id))) { \
725 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
726 DRM_CURRENTPID, (id)); \
729 (ch) = nv->fifos[(id)]; \
733 extern int nouveau_agpmode;
734 extern int nouveau_duallink;
735 extern int nouveau_uscript_lvds;
736 extern int nouveau_uscript_tmds;
737 extern int nouveau_vram_pushbuf;
738 extern int nouveau_vram_notify;
739 extern int nouveau_fbpercrtc;
740 extern int nouveau_tv_disable;
741 extern char *nouveau_tv_norm;
742 extern int nouveau_reg_debug;
743 extern char *nouveau_vbios;
744 extern int nouveau_ignorelid;
745 extern int nouveau_nofbaccel;
746 extern int nouveau_noaccel;
747 extern int nouveau_force_post;
748 extern int nouveau_override_conntype;
749 extern char *nouveau_perflvl;
750 extern int nouveau_perflvl_wr;
752 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
753 extern int nouveau_pci_resume(struct pci_dev *pdev);
755 /* nouveau_state.c */
756 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
757 extern int nouveau_load(struct drm_device *, unsigned long flags);
758 extern int nouveau_firstopen(struct drm_device *);
759 extern void nouveau_lastclose(struct drm_device *);
760 extern int nouveau_unload(struct drm_device *);
761 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
763 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
765 extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
766 uint32_t reg, uint32_t mask, uint32_t val);
767 extern bool nouveau_wait_for_idle(struct drm_device *);
768 extern int nouveau_card_init(struct drm_device *);
771 extern int nouveau_mem_vram_init(struct drm_device *);
772 extern void nouveau_mem_vram_fini(struct drm_device *);
773 extern int nouveau_mem_gart_init(struct drm_device *);
774 extern void nouveau_mem_gart_fini(struct drm_device *);
775 extern int nouveau_mem_init_agp(struct drm_device *);
776 extern int nouveau_mem_reset_agp(struct drm_device *);
777 extern void nouveau_mem_close(struct drm_device *);
778 extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
782 extern void nv10_mem_expire_tiling(struct drm_device *dev,
783 struct nouveau_tile_reg *tile,
784 struct nouveau_fence *fence);
785 extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
786 uint32_t size, uint32_t flags,
788 extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
791 /* nouveau_notifier.c */
792 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
793 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
794 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
795 int cout, uint32_t *offset);
796 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
797 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
799 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
802 /* nouveau_channel.c */
803 extern struct drm_ioctl_desc nouveau_ioctls[];
804 extern int nouveau_max_ioctl;
805 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
806 extern int nouveau_channel_owner(struct drm_device *, struct drm_file *,
808 extern int nouveau_channel_alloc(struct drm_device *dev,
809 struct nouveau_channel **chan,
810 struct drm_file *file_priv,
811 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
812 extern void nouveau_channel_free(struct nouveau_channel *);
814 /* nouveau_object.c */
815 extern int nouveau_gpuobj_early_init(struct drm_device *);
816 extern int nouveau_gpuobj_init(struct drm_device *);
817 extern void nouveau_gpuobj_takedown(struct drm_device *);
818 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
819 extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
820 extern void nouveau_gpuobj_resume(struct drm_device *dev);
821 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
822 uint32_t vram_h, uint32_t tt_h);
823 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
824 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
825 uint32_t size, int align, uint32_t flags,
826 struct nouveau_gpuobj **);
827 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
828 struct nouveau_gpuobj **);
829 extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
831 struct nouveau_gpuobj **);
832 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
833 uint64_t offset, uint64_t size, int access,
834 int target, struct nouveau_gpuobj **);
835 extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
836 uint64_t offset, uint64_t size,
837 int access, struct nouveau_gpuobj **,
839 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
840 struct nouveau_gpuobj **);
841 extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
842 struct nouveau_gpuobj **);
843 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
845 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
849 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
850 extern void nouveau_irq_preinstall(struct drm_device *);
851 extern int nouveau_irq_postinstall(struct drm_device *);
852 extern void nouveau_irq_uninstall(struct drm_device *);
854 /* nouveau_sgdma.c */
855 extern int nouveau_sgdma_init(struct drm_device *);
856 extern void nouveau_sgdma_takedown(struct drm_device *);
857 extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
859 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
861 /* nouveau_debugfs.c */
862 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
863 extern int nouveau_debugfs_init(struct drm_minor *);
864 extern void nouveau_debugfs_takedown(struct drm_minor *);
865 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
866 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
869 nouveau_debugfs_init(struct drm_minor *minor)
874 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
879 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
885 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
891 extern void nouveau_dma_pre_init(struct nouveau_channel *);
892 extern int nouveau_dma_init(struct nouveau_channel *);
893 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
896 #define ROM_BIOS_PAGE 4096
897 #if defined(CONFIG_ACPI)
898 void nouveau_register_dsm_handler(void);
899 void nouveau_unregister_dsm_handler(void);
900 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
901 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
902 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
904 static inline void nouveau_register_dsm_handler(void) {}
905 static inline void nouveau_unregister_dsm_handler(void) {}
906 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
907 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
908 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
911 /* nouveau_backlight.c */
912 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
913 extern int nouveau_backlight_init(struct drm_device *);
914 extern void nouveau_backlight_exit(struct drm_device *);
916 static inline int nouveau_backlight_init(struct drm_device *dev)
921 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
925 extern int nouveau_bios_init(struct drm_device *);
926 extern void nouveau_bios_takedown(struct drm_device *dev);
927 extern int nouveau_run_vbios_init(struct drm_device *);
928 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
930 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
932 extern struct dcb_connector_table_entry *
933 nouveau_bios_connector_entry(struct drm_device *, int index);
934 extern u32 get_pll_register(struct drm_device *, enum pll_types);
935 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
937 extern int nouveau_bios_run_display_table(struct drm_device *,
939 uint32_t script, int pxclk);
940 extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
942 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
943 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
944 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
945 bool *dl, bool *if_is_24bit);
946 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
947 int head, int pxclk);
948 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
949 enum LVDS_script, int pxclk);
952 int nouveau_ttm_global_init(struct drm_nouveau_private *);
953 void nouveau_ttm_global_release(struct drm_nouveau_private *);
954 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
957 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
958 uint8_t *data, int data_nr);
959 bool nouveau_dp_detect(struct drm_encoder *);
960 bool nouveau_dp_link_train(struct drm_encoder *);
963 extern int nv04_fb_init(struct drm_device *);
964 extern void nv04_fb_takedown(struct drm_device *);
967 extern int nv10_fb_init(struct drm_device *);
968 extern void nv10_fb_takedown(struct drm_device *);
969 extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
973 extern int nv30_fb_init(struct drm_device *);
974 extern void nv30_fb_takedown(struct drm_device *);
977 extern int nv40_fb_init(struct drm_device *);
978 extern void nv40_fb_takedown(struct drm_device *);
979 extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
982 extern int nv50_fb_init(struct drm_device *);
983 extern void nv50_fb_takedown(struct drm_device *);
984 extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *);
987 extern int nvc0_fb_init(struct drm_device *);
988 extern void nvc0_fb_takedown(struct drm_device *);
991 extern int nv04_fifo_init(struct drm_device *);
992 extern void nv04_fifo_disable(struct drm_device *);
993 extern void nv04_fifo_enable(struct drm_device *);
994 extern bool nv04_fifo_reassign(struct drm_device *, bool);
995 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
996 extern int nv04_fifo_channel_id(struct drm_device *);
997 extern int nv04_fifo_create_context(struct nouveau_channel *);
998 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
999 extern int nv04_fifo_load_context(struct nouveau_channel *);
1000 extern int nv04_fifo_unload_context(struct drm_device *);
1003 extern int nv10_fifo_init(struct drm_device *);
1004 extern int nv10_fifo_channel_id(struct drm_device *);
1005 extern int nv10_fifo_create_context(struct nouveau_channel *);
1006 extern void nv10_fifo_destroy_context(struct nouveau_channel *);
1007 extern int nv10_fifo_load_context(struct nouveau_channel *);
1008 extern int nv10_fifo_unload_context(struct drm_device *);
1011 extern int nv40_fifo_init(struct drm_device *);
1012 extern int nv40_fifo_create_context(struct nouveau_channel *);
1013 extern void nv40_fifo_destroy_context(struct nouveau_channel *);
1014 extern int nv40_fifo_load_context(struct nouveau_channel *);
1015 extern int nv40_fifo_unload_context(struct drm_device *);
1018 extern int nv50_fifo_init(struct drm_device *);
1019 extern void nv50_fifo_takedown(struct drm_device *);
1020 extern int nv50_fifo_channel_id(struct drm_device *);
1021 extern int nv50_fifo_create_context(struct nouveau_channel *);
1022 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1023 extern int nv50_fifo_load_context(struct nouveau_channel *);
1024 extern int nv50_fifo_unload_context(struct drm_device *);
1025 extern void nv50_fifo_tlb_flush(struct drm_device *dev);
1028 extern int nvc0_fifo_init(struct drm_device *);
1029 extern void nvc0_fifo_takedown(struct drm_device *);
1030 extern void nvc0_fifo_disable(struct drm_device *);
1031 extern void nvc0_fifo_enable(struct drm_device *);
1032 extern bool nvc0_fifo_reassign(struct drm_device *, bool);
1033 extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1034 extern int nvc0_fifo_channel_id(struct drm_device *);
1035 extern int nvc0_fifo_create_context(struct nouveau_channel *);
1036 extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1037 extern int nvc0_fifo_load_context(struct nouveau_channel *);
1038 extern int nvc0_fifo_unload_context(struct drm_device *);
1041 extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
1042 extern int nv04_graph_init(struct drm_device *);
1043 extern void nv04_graph_takedown(struct drm_device *);
1044 extern void nv04_graph_fifo_access(struct drm_device *, bool);
1045 extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
1046 extern int nv04_graph_create_context(struct nouveau_channel *);
1047 extern void nv04_graph_destroy_context(struct nouveau_channel *);
1048 extern int nv04_graph_load_context(struct nouveau_channel *);
1049 extern int nv04_graph_unload_context(struct drm_device *);
1050 extern void nv04_graph_context_switch(struct drm_device *);
1053 extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
1054 extern int nv10_graph_init(struct drm_device *);
1055 extern void nv10_graph_takedown(struct drm_device *);
1056 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1057 extern int nv10_graph_create_context(struct nouveau_channel *);
1058 extern void nv10_graph_destroy_context(struct nouveau_channel *);
1059 extern int nv10_graph_load_context(struct nouveau_channel *);
1060 extern int nv10_graph_unload_context(struct drm_device *);
1061 extern void nv10_graph_context_switch(struct drm_device *);
1062 extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1063 uint32_t, uint32_t);
1066 extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
1067 extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
1068 extern int nv20_graph_create_context(struct nouveau_channel *);
1069 extern void nv20_graph_destroy_context(struct nouveau_channel *);
1070 extern int nv20_graph_load_context(struct nouveau_channel *);
1071 extern int nv20_graph_unload_context(struct drm_device *);
1072 extern int nv20_graph_init(struct drm_device *);
1073 extern void nv20_graph_takedown(struct drm_device *);
1074 extern int nv30_graph_init(struct drm_device *);
1075 extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1076 uint32_t, uint32_t);
1079 extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
1080 extern int nv40_graph_init(struct drm_device *);
1081 extern void nv40_graph_takedown(struct drm_device *);
1082 extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1083 extern int nv40_graph_create_context(struct nouveau_channel *);
1084 extern void nv40_graph_destroy_context(struct nouveau_channel *);
1085 extern int nv40_graph_load_context(struct nouveau_channel *);
1086 extern int nv40_graph_unload_context(struct drm_device *);
1087 extern void nv40_grctx_init(struct nouveau_grctx *);
1088 extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1089 uint32_t, uint32_t);
1092 extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
1093 extern int nv50_graph_init(struct drm_device *);
1094 extern void nv50_graph_takedown(struct drm_device *);
1095 extern void nv50_graph_fifo_access(struct drm_device *, bool);
1096 extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1097 extern int nv50_graph_create_context(struct nouveau_channel *);
1098 extern void nv50_graph_destroy_context(struct nouveau_channel *);
1099 extern int nv50_graph_load_context(struct nouveau_channel *);
1100 extern int nv50_graph_unload_context(struct drm_device *);
1101 extern void nv50_graph_context_switch(struct drm_device *);
1102 extern int nv50_grctx_init(struct nouveau_grctx *);
1103 extern void nv50_graph_tlb_flush(struct drm_device *dev);
1104 extern void nv86_graph_tlb_flush(struct drm_device *dev);
1107 extern int nvc0_graph_init(struct drm_device *);
1108 extern void nvc0_graph_takedown(struct drm_device *);
1109 extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1110 extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1111 extern int nvc0_graph_create_context(struct nouveau_channel *);
1112 extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1113 extern int nvc0_graph_load_context(struct nouveau_channel *);
1114 extern int nvc0_graph_unload_context(struct drm_device *);
1116 /* nv04_instmem.c */
1117 extern int nv04_instmem_init(struct drm_device *);
1118 extern void nv04_instmem_takedown(struct drm_device *);
1119 extern int nv04_instmem_suspend(struct drm_device *);
1120 extern void nv04_instmem_resume(struct drm_device *);
1121 extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1123 extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1124 extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1125 extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1126 extern void nv04_instmem_flush(struct drm_device *);
1128 /* nv50_instmem.c */
1129 extern int nv50_instmem_init(struct drm_device *);
1130 extern void nv50_instmem_takedown(struct drm_device *);
1131 extern int nv50_instmem_suspend(struct drm_device *);
1132 extern void nv50_instmem_resume(struct drm_device *);
1133 extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1135 extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1136 extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1137 extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1138 extern void nv50_instmem_flush(struct drm_device *);
1139 extern void nv84_instmem_flush(struct drm_device *);
1140 extern void nv50_vm_flush(struct drm_device *, int engine);
1142 /* nvc0_instmem.c */
1143 extern int nvc0_instmem_init(struct drm_device *);
1144 extern void nvc0_instmem_takedown(struct drm_device *);
1145 extern int nvc0_instmem_suspend(struct drm_device *);
1146 extern void nvc0_instmem_resume(struct drm_device *);
1147 extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1149 extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1150 extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1151 extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1152 extern void nvc0_instmem_flush(struct drm_device *);
1155 extern int nv04_mc_init(struct drm_device *);
1156 extern void nv04_mc_takedown(struct drm_device *);
1159 extern int nv40_mc_init(struct drm_device *);
1160 extern void nv40_mc_takedown(struct drm_device *);
1163 extern int nv50_mc_init(struct drm_device *);
1164 extern void nv50_mc_takedown(struct drm_device *);
1167 extern int nv04_timer_init(struct drm_device *);
1168 extern uint64_t nv04_timer_read(struct drm_device *);
1169 extern void nv04_timer_takedown(struct drm_device *);
1171 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1175 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1176 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1177 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1178 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1179 extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1182 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1183 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1184 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1186 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1187 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1190 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1191 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1194 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1196 /* nv04_display.c */
1197 extern int nv04_display_early_init(struct drm_device *);
1198 extern void nv04_display_late_takedown(struct drm_device *);
1199 extern int nv04_display_create(struct drm_device *);
1200 extern int nv04_display_init(struct drm_device *);
1201 extern void nv04_display_destroy(struct drm_device *);
1204 extern int nv04_crtc_create(struct drm_device *, int index);
1207 extern struct ttm_bo_driver nouveau_bo_driver;
1208 extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1209 int size, int align, uint32_t flags,
1210 uint32_t tile_mode, uint32_t tile_flags,
1211 bool no_vm, bool mappable, struct nouveau_bo **);
1212 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1213 extern int nouveau_bo_unpin(struct nouveau_bo *);
1214 extern int nouveau_bo_map(struct nouveau_bo *);
1215 extern void nouveau_bo_unmap(struct nouveau_bo *);
1216 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1218 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1219 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1220 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1221 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1223 /* nouveau_fence.c */
1224 struct nouveau_fence;
1225 extern int nouveau_fence_init(struct drm_device *);
1226 extern void nouveau_fence_fini(struct drm_device *);
1227 extern int nouveau_fence_channel_init(struct nouveau_channel *);
1228 extern void nouveau_fence_channel_fini(struct nouveau_channel *);
1229 extern void nouveau_fence_update(struct nouveau_channel *);
1230 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1232 extern int nouveau_fence_emit(struct nouveau_fence *);
1233 extern void nouveau_fence_work(struct nouveau_fence *fence,
1234 void (*work)(void *priv, bool signalled),
1236 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1237 extern bool nouveau_fence_signalled(void *obj, void *arg);
1238 extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1239 extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
1240 extern int nouveau_fence_flush(void *obj, void *arg);
1241 extern void nouveau_fence_unref(void **obj);
1242 extern void *nouveau_fence_ref(void *obj);
1245 extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1246 int size, int align, uint32_t flags,
1247 uint32_t tile_mode, uint32_t tile_flags,
1248 bool no_vm, bool mappable, struct nouveau_bo **);
1249 extern int nouveau_gem_object_new(struct drm_gem_object *);
1250 extern void nouveau_gem_object_del(struct drm_gem_object *);
1251 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1253 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1255 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1257 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1259 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1263 int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1264 int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1267 int nv50_gpio_init(struct drm_device *dev);
1268 int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1269 int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1270 void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
1273 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1274 int *N1, int *M1, int *N2, int *M2, int *P);
1275 int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1276 int clk, int *N, int *fN, int *M, int *P);
1278 #ifndef ioread32_native
1280 #define ioread16_native ioread16be
1281 #define iowrite16_native iowrite16be
1282 #define ioread32_native ioread32be
1283 #define iowrite32_native iowrite32be
1284 #else /* def __BIG_ENDIAN */
1285 #define ioread16_native ioread16
1286 #define iowrite16_native iowrite16
1287 #define ioread32_native ioread32
1288 #define iowrite32_native iowrite32
1289 #endif /* def __BIG_ENDIAN else */
1290 #endif /* !ioread32_native */
1292 /* channel control reg access */
1293 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1295 return ioread32_native(chan->user + reg);
1298 static inline void nvchan_wr32(struct nouveau_channel *chan,
1299 unsigned reg, u32 val)
1301 iowrite32_native(val, chan->user + reg);
1304 /* register access */
1305 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1307 struct drm_nouveau_private *dev_priv = dev->dev_private;
1308 return ioread32_native(dev_priv->mmio + reg);
1311 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1313 struct drm_nouveau_private *dev_priv = dev->dev_private;
1314 iowrite32_native(val, dev_priv->mmio + reg);
1317 static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1319 u32 tmp = nv_rd32(dev, reg);
1320 nv_wr32(dev, reg, (tmp & ~mask) | val);
1324 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1326 struct drm_nouveau_private *dev_priv = dev->dev_private;
1327 return ioread8(dev_priv->mmio + reg);
1330 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1332 struct drm_nouveau_private *dev_priv = dev->dev_private;
1333 iowrite8(val, dev_priv->mmio + reg);
1336 #define nv_wait(dev, reg, mask, val) \
1337 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1340 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1342 struct drm_nouveau_private *dev_priv = dev->dev_private;
1343 return ioread32_native(dev_priv->ramin + offset);
1346 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1348 struct drm_nouveau_private *dev_priv = dev->dev_private;
1349 iowrite32_native(val, dev_priv->ramin + offset);
1353 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1354 extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
1358 * Argument d is (struct drm_device *).
1360 #define NV_PRINTK(level, d, fmt, arg...) \
1361 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1362 pci_name(d->pdev), ##arg)
1363 #ifndef NV_DEBUG_NOTRACE
1364 #define NV_DEBUG(d, fmt, arg...) do { \
1365 if (drm_debug & DRM_UT_DRIVER) { \
1366 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1370 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1371 if (drm_debug & DRM_UT_KMS) { \
1372 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1377 #define NV_DEBUG(d, fmt, arg...) do { \
1378 if (drm_debug & DRM_UT_DRIVER) \
1379 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1381 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1382 if (drm_debug & DRM_UT_KMS) \
1383 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1386 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1387 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1388 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1389 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1390 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1392 /* nouveau_reg_debug bitmask */
1394 NOUVEAU_REG_DEBUG_MC = 0x1,
1395 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1396 NOUVEAU_REG_DEBUG_FB = 0x4,
1397 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1398 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1399 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1400 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1401 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1402 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1403 NOUVEAU_REG_DEBUG_EVO = 0x200,
1406 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1407 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1408 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1412 nv_two_heads(struct drm_device *dev)
1414 struct drm_nouveau_private *dev_priv = dev->dev_private;
1415 const int impl = dev->pci_device & 0x0ff0;
1417 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1418 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1425 nv_gf4_disp_arch(struct drm_device *dev)
1427 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1431 nv_two_reg_pll(struct drm_device *dev)
1433 struct drm_nouveau_private *dev_priv = dev->dev_private;
1434 const int impl = dev->pci_device & 0x0ff0;
1436 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1442 nv_match_device(struct drm_device *dev, unsigned device,
1443 unsigned sub_vendor, unsigned sub_device)
1445 return dev->pdev->device == device &&
1446 dev->pdev->subsystem_vendor == sub_vendor &&
1447 dev->pdev->subsystem_device == sub_device;
1450 #define NV_SW 0x0000506e
1451 #define NV_SW_DMA_SEMAPHORE 0x00000060
1452 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1453 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1454 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1455 #define NV_SW_YIELD 0x00000080
1456 #define NV_SW_DMA_VBLSEM 0x0000018c
1457 #define NV_SW_VBLSEM_OFFSET 0x00000400
1458 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1459 #define NV_SW_VBLSEM_RELEASE 0x00000408
1461 #endif /* __NOUVEAU_DRV_H__ */