drivers/gpu/drm/nouveau/nouveau_mem.c

   1 /*
   2  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3  * Copyright 2005 Stephane Marchesin
   4  *
   5  * The Weather Channel (TM) funded Tungsten Graphics to develop the
   6  * initial release of the Radeon 8500 driver under the XFree86 license.
   7  * This notice must be preserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26  * DEALINGS IN THE SOFTWARE.
  27  *
  28  * Authors:
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  */
  31
  32
  33 #include "drmP.h"
  34 #include "drm.h"
  35 #include "drm_sarea.h"
  36
  37 #include "nouveau_drv.h"
  38 #include "nouveau_pm.h"
  39
  40 /*
  41  * NV10-NV40 tiling helpers
  42  */
  43
  44 static void
  45 nv10_mem_update_tile_region(struct drm_device *dev,
  46                             struct nouveau_tile_reg *tile, uint32_t addr,
  47                             uint32_t size, uint32_t pitch, uint32_t flags)
  48 {
  49         struct drm_nouveau_private *dev_priv = dev->dev_private;
  50         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
  51         struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
  52         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
  53         int i = tile - dev_priv->tile.reg;
  54         unsigned long save;
  55
  56         nouveau_fence_unref(&tile->fence);
  57
  58         if (tile->pitch)
  59                 pfb->free_tile_region(dev, i);
  60
  61         if (pitch)
  62                 pfb->init_tile_region(dev, i, addr, size, pitch, flags);
  63
  64         spin_lock_irqsave(&dev_priv->context_switch_lock, save);
  65         pfifo->reassign(dev, false);
  66         pfifo->cache_pull(dev, false);
  67
  68         nouveau_wait_for_idle(dev);
  69
  70         pfb->set_tile_region(dev, i);
  71         pgraph->set_tile_region(dev, i);
  72
  73         pfifo->cache_pull(dev, true);
  74         pfifo->reassign(dev, true);
  75         spin_unlock_irqrestore(&dev_priv->context_switch_lock, save);
  76 }
  77
  78 static struct nouveau_tile_reg *
  79 nv10_mem_get_tile_region(struct drm_device *dev, int i)
  80 {
  81         struct drm_nouveau_private *dev_priv = dev->dev_private;
  82         struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
  83
  84         spin_lock(&dev_priv->tile.lock);
  85
  86         if (!tile->used &&
  87             (!tile->fence || nouveau_fence_signalled(tile->fence)))
  88                 tile->used = true;
  89         else
  90                 tile = NULL;
  91
  92         spin_unlock(&dev_priv->tile.lock);
  93         return tile;
  94 }
  95
  96 void
  97 nv10_mem_put_tile_region(struct drm_device *dev, struct nouveau_tile_reg *tile,
  98                          struct nouveau_fence *fence)
  99 {
 100         struct drm_nouveau_private *dev_priv = dev->dev_private;
 101
 102         if (tile) {
 103                 spin_lock(&dev_priv->tile.lock);
 104                 if (fence) {
 105                         /* Mark it as pending. */
 106                         tile->fence = fence;
 107                         nouveau_fence_ref(fence);
 108                 }
 109
 110                 tile->used = false;
 111                 spin_unlock(&dev_priv->tile.lock);
 112         }
 113 }
 114
 115 struct nouveau_tile_reg *
 116 nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
 117                     uint32_t pitch, uint32_t flags)
 118 {
 119         struct drm_nouveau_private *dev_priv = dev->dev_private;
 120         struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
 121         struct nouveau_tile_reg *tile, *found = NULL;
 122         int i;
 123
 124         for (i = 0; i < pfb->num_tiles; i++) {
 125                 tile = nv10_mem_get_tile_region(dev, i);
 126
 127                 if (pitch && !found) {
 128                         found = tile;
 129                         continue;
 130
 131                 } else if (tile && tile->pitch) {
 132                         /* Kill an unused tile region. */
 133                         nv10_mem_update_tile_region(dev, tile, 0, 0, 0, 0);
 134                 }
 135
 136                 nv10_mem_put_tile_region(dev, tile, NULL);
 137         }
 138
 139         if (found)
 140                 nv10_mem_update_tile_region(dev, found, addr, size,
 141                                             pitch, flags);
 142         return found;
 143 }
 144
 145 /*
 146  * NV50 VM helpers
 147  */
 148 int
 149 nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
 150                         uint32_t flags, uint64_t phys)
 151 {
 152         struct drm_nouveau_private *dev_priv = dev->dev_private;
 153         struct nouveau_gpuobj *pgt;
 154         unsigned block;
 155         int i;
 156
 157         virt = ((virt - dev_priv->vm_vram_base) >> 16) << 1;
 158         size = (size >> 16) << 1;
 159
 160         phys |= ((uint64_t)flags << 32);
 161         phys |= 1;
 162         if (dev_priv->vram_sys_base) {
 163                 phys += dev_priv->vram_sys_base;
 164                 phys |= 0x30;
 165         }
 166
 167         while (size) {
 168                 unsigned offset_h = upper_32_bits(phys);
 169                 unsigned offset_l = lower_32_bits(phys);
 170                 unsigned pte, end;
 171
 172                 for (i = 7; i >= 0; i--) {
 173                         block = 1 << (i + 1);
 174                         if (size >= block && !(virt & (block - 1)))
 175                                 break;
 176                 }
 177                 offset_l |= (i << 7);
 178
 179                 phys += block << 15;
 180                 size -= block;
 181
 182                 while (block) {
 183                         pgt = dev_priv->vm_vram_pt[virt >> 14];
 184                         pte = virt & 0x3ffe;
 185
 186                         end = pte + block;
 187                         if (end > 16384)
 188                                 end = 16384;
 189                         block -= (end - pte);
 190                         virt  += (end - pte);
 191
 192                         while (pte < end) {
 193                                 nv_wo32(pgt, (pte * 4) + 0, offset_l);
 194                                 nv_wo32(pgt, (pte * 4) + 4, offset_h);
 195                                 pte += 2;
 196                         }
 197                 }
 198         }
 199
 200         dev_priv->engine.instmem.flush(dev);
 201         dev_priv->engine.fifo.tlb_flush(dev);
 202         dev_priv->engine.graph.tlb_flush(dev);
 203         nv50_vm_flush(dev, 6);
 204         return 0;
 205 }
 206
 207 void
 208 nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size)
 209 {
 210         struct drm_nouveau_private *dev_priv = dev->dev_private;
 211         struct nouveau_gpuobj *pgt;
 212         unsigned pages, pte, end;
 213
 214         virt -= dev_priv->vm_vram_base;
 215         pages = (size >> 16) << 1;
 216
 217         while (pages) {
 218                 pgt = dev_priv->vm_vram_pt[virt >> 29];
 219                 pte = (virt & 0x1ffe0000ULL) >> 15;
 220
 221                 end = pte + pages;
 222                 if (end > 16384)
 223                         end = 16384;
 224                 pages -= (end - pte);
 225                 virt  += (end - pte) << 15;
 226
 227                 while (pte < end) {
 228                         nv_wo32(pgt, (pte * 4), 0);
 229                         pte++;
 230                 }
 231         }
 232
 233         dev_priv->engine.instmem.flush(dev);
 234         dev_priv->engine.fifo.tlb_flush(dev);
 235         dev_priv->engine.graph.tlb_flush(dev);
 236         nv50_vm_flush(dev, 6);
 237 }
 238
 239 /*
 240  * Cleanup everything
 241  */
 242 void
 243 nouveau_mem_vram_fini(struct drm_device *dev)
 244 {
 245         struct drm_nouveau_private *dev_priv = dev->dev_private;
 246
 247         nouveau_bo_unpin(dev_priv->vga_ram);
 248         nouveau_bo_ref(NULL, &dev_priv->vga_ram);
 249
 250         ttm_bo_device_release(&dev_priv->ttm.bdev);
 251
 252         nouveau_ttm_global_release(dev_priv);
 253
 254         if (dev_priv->fb_mtrr >= 0) {
 255                 drm_mtrr_del(dev_priv->fb_mtrr,
 256                              pci_resource_start(dev->pdev, 1),
 257                              pci_resource_len(dev->pdev, 1), DRM_MTRR_WC);
 258                 dev_priv->fb_mtrr = -1;
 259         }
 260 }
 261
 262 void
 263 nouveau_mem_gart_fini(struct drm_device *dev)
 264 {
 265         nouveau_sgdma_takedown(dev);
 266
 267         if (drm_core_has_AGP(dev) && dev->agp) {
 268                 struct drm_agp_mem *entry, *tempe;
 269
 270                 /* Remove AGP resources, but leave dev->agp
 271                    intact until drv_cleanup is called. */
 272                 list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
 273                         if (entry->bound)
 274                                 drm_unbind_agp(entry->memory);
 275                         drm_free_agp(entry->memory, entry->pages);
 276                         kfree(entry);
 277                 }
 278                 INIT_LIST_HEAD(&dev->agp->memory);
 279
 280                 if (dev->agp->acquired)
 281                         drm_agp_release(dev);
 282
 283                 dev->agp->acquired = 0;
 284                 dev->agp->enabled = 0;
 285         }
 286 }
 287
 288 static uint32_t
 289 nouveau_mem_detect_nv04(struct drm_device *dev)
 290 {
 291         uint32_t boot0 = nv_rd32(dev, NV04_PFB_BOOT_0);
 292
 293         if (boot0 & 0x00000100)
 294                 return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;
 295
 296         switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
 297         case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
 298                 return 32 * 1024 * 1024;
 299         case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
 300                 return 16 * 1024 * 1024;
 301         case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
 302                 return 8 * 1024 * 1024;
 303         case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
 304                 return 4 * 1024 * 1024;
 305         }
 306
 307         return 0;
 308 }
 309
 310 static uint32_t
 311 nouveau_mem_detect_nforce(struct drm_device *dev)
 312 {
 313         struct drm_nouveau_private *dev_priv = dev->dev_private;
 314         struct pci_dev *bridge;
 315         uint32_t mem;
 316
 317         bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
 318         if (!bridge) {
 319                 NV_ERROR(dev, "no bridge device\n");
 320                 return 0;
 321         }
 322
 323         if (dev_priv->flags & NV_NFORCE) {
 324                 pci_read_config_dword(bridge, 0x7C, &mem);
 325                 return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024;
 326         } else
 327         if (dev_priv->flags & NV_NFORCE2) {
 328                 pci_read_config_dword(bridge, 0x84, &mem);
 329                 return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024;
 330         }
 331
 332         NV_ERROR(dev, "impossible!\n");
 333         return 0;
 334 }
 335
 336 static void
 337 nv50_vram_preinit(struct drm_device *dev)
 338 {
 339         struct drm_nouveau_private *dev_priv = dev->dev_private;
 340         int i, parts, colbits, rowbitsa, rowbitsb, banks;
 341         u64 rowsize, predicted;
 342         u32 r0, r4, rt, ru;
 343
 344         r0 = nv_rd32(dev, 0x100200);
 345         r4 = nv_rd32(dev, 0x100204);
 346         rt = nv_rd32(dev, 0x100250);
 347         ru = nv_rd32(dev, 0x001540);
 348         NV_DEBUG(dev, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt, ru);
 349
 350         for (i = 0, parts = 0; i < 8; i++) {
 351                 if (ru & (0x00010000 << i))
 352                         parts++;
 353         }
 354
 355         colbits  =  (r4 & 0x0000f000) >> 12;
 356         rowbitsa = ((r4 & 0x000f0000) >> 16) + 8;
 357         rowbitsb = ((r4 & 0x00f00000) >> 20) + 8;
 358         banks    = ((r4 & 0x01000000) ? 8 : 4);
 359
 360         rowsize = parts * banks * (1 << colbits) * 8;
 361         predicted = rowsize << rowbitsa;
 362         if (r0 & 0x00000004)
 363                 predicted += rowsize << rowbitsb;
 364
 365         if (predicted != dev_priv->vram_size) {
 366                 NV_WARN(dev, "memory controller reports %dMiB VRAM\n",
 367                         (u32)(dev_priv->vram_size >> 20));
 368                 NV_WARN(dev, "we calculated %dMiB VRAM\n",
 369                         (u32)(predicted >> 20));
 370         }
 371
 372         dev_priv->vram_rblock_size = rowsize >> 12;
 373         if (rt & 1)
 374                 dev_priv->vram_rblock_size *= 3;
 375
 376         NV_DEBUG(dev, "rblock %lld bytes\n",
 377                  (u64)dev_priv->vram_rblock_size << 12);
 378 }
 379
 380 static void
 381 nvaa_vram_preinit(struct drm_device *dev)
 382 {
 383         struct drm_nouveau_private *dev_priv = dev->dev_private;
 384
 385         /* To our knowledge, there's no large scale reordering of pages
 386          * that occurs on IGP chipsets.
 387          */
 388         dev_priv->vram_rblock_size = 1;
 389 }
 390
 391 static int
 392 nouveau_mem_detect(struct drm_device *dev)
 393 {
 394         struct drm_nouveau_private *dev_priv = dev->dev_private;
 395
 396         if (dev_priv->card_type == NV_04) {
 397                 dev_priv->vram_size = nouveau_mem_detect_nv04(dev);
 398         } else
 399         if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) {
 400                 dev_priv->vram_size = nouveau_mem_detect_nforce(dev);
 401         } else
 402         if (dev_priv->card_type < NV_50) {
 403                 dev_priv->vram_size  = nv_rd32(dev, NV04_PFB_FIFO_DATA);
 404                 dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
 405         } else
 406         if (dev_priv->card_type < NV_C0) {
 407                 dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA);
 408                 dev_priv->vram_size |= (dev_priv->vram_size & 0xff) << 32;
 409                 dev_priv->vram_size &= 0xffffffff00ll;
 410
 411                 switch (dev_priv->chipset) {
 412                 case 0xaa:
 413                 case 0xac:
 414                 case 0xaf:
 415                         dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10);
 416                         dev_priv->vram_sys_base <<= 12;
 417                         nvaa_vram_preinit(dev);
 418                         break;
 419                 default:
 420                         nv50_vram_preinit(dev);
 421                         break;
 422                 }
 423         } else {
 424                 dev_priv->vram_size  = nv_rd32(dev, 0x10f20c) << 20;
 425                 dev_priv->vram_size *= nv_rd32(dev, 0x121c74);
 426         }
 427
 428         NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
 429         if (dev_priv->vram_sys_base) {
 430                 NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
 431                         dev_priv->vram_sys_base);
 432         }
 433
 434         if (dev_priv->vram_size)
 435                 return 0;
 436         return -ENOMEM;
 437 }
 438
 439 #if __OS_HAS_AGP
 440 static unsigned long
 441 get_agp_mode(struct drm_device *dev, unsigned long mode)
 442 {
 443         struct drm_nouveau_private *dev_priv = dev->dev_private;
 444
 445         /*
 446          * FW seems to be broken on nv18, it makes the card lock up
 447          * randomly.
 448          */
 449         if (dev_priv->chipset == 0x18)
 450                 mode &= ~PCI_AGP_COMMAND_FW;
 451
 452         /*
 453          * AGP mode set in the command line.
 454          */
 455         if (nouveau_agpmode > 0) {
 456                 bool agpv3 = mode & 0x8;
 457                 int rate = agpv3 ? nouveau_agpmode / 4 : nouveau_agpmode;
 458
 459                 mode = (mode & ~0x7) | (rate & 0x7);
 460         }
 461
 462         return mode;
 463 }
 464 #endif
 465
 466 int
 467 nouveau_mem_reset_agp(struct drm_device *dev)
 468 {
 469 #if __OS_HAS_AGP
 470         uint32_t saved_pci_nv_1, pmc_enable;
 471         int ret;
 472
 473         /* First of all, disable fast writes, otherwise if it's
 474          * already enabled in the AGP bridge and we disable the card's
 475          * AGP controller we might be locking ourselves out of it. */
 476         if ((nv_rd32(dev, NV04_PBUS_PCI_NV_19) |
 477              dev->agp->mode) & PCI_AGP_COMMAND_FW) {
 478                 struct drm_agp_info info;
 479                 struct drm_agp_mode mode;
 480
 481                 ret = drm_agp_info(dev, &info);
 482                 if (ret)
 483                         return ret;
 484
 485                 mode.mode = get_agp_mode(dev, info.mode) & ~PCI_AGP_COMMAND_FW;
 486                 ret = drm_agp_enable(dev, mode);
 487                 if (ret)
 488                         return ret;
 489         }
 490
 491         saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);
 492
 493         /* clear busmaster bit */
 494         nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
 495         /* disable AGP */
 496         nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0);
 497
 498         /* power cycle pgraph, if enabled */
 499         pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
 500         if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
 501                 nv_wr32(dev, NV03_PMC_ENABLE,
 502                                 pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
 503                 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
 504                                 NV_PMC_ENABLE_PGRAPH);
 505         }
 506
 507         /* and restore (gives effect of resetting AGP) */
 508         nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
 509 #endif
 510
 511         return 0;
 512 }
 513
 514 int
 515 nouveau_mem_init_agp(struct drm_device *dev)
 516 {
 517 #if __OS_HAS_AGP
 518         struct drm_nouveau_private *dev_priv = dev->dev_private;
 519         struct drm_agp_info info;
 520         struct drm_agp_mode mode;
 521         int ret;
 522
 523         if (!dev->agp->acquired) {
 524                 ret = drm_agp_acquire(dev);
 525                 if (ret) {
 526                         NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
 527                         return ret;
 528                 }
 529         }
 530
 531         nouveau_mem_reset_agp(dev);
 532
 533         ret = drm_agp_info(dev, &info);
 534         if (ret) {
 535                 NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
 536                 return ret;
 537         }
 538
 539         /* see agp.h for the AGPSTAT_* modes available */
 540         mode.mode = get_agp_mode(dev, info.mode);
 541         ret = drm_agp_enable(dev, mode);
 542         if (ret) {
 543                 NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
 544                 return ret;
 545         }
 546
 547         dev_priv->gart_info.type        = NOUVEAU_GART_AGP;
 548         dev_priv->gart_info.aper_base   = info.aperture_base;
 549         dev_priv->gart_info.aper_size   = info.aperture_size;
 550 #endif
 551         return 0;
 552 }
 553
 554 int
 555 nouveau_mem_vram_init(struct drm_device *dev)
 556 {
 557         struct drm_nouveau_private *dev_priv = dev->dev_private;
 558         struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
 559         int ret, dma_bits;
 560
 561         if (dev_priv->card_type >= NV_50 &&
 562             pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
 563                 dma_bits = 40;
 564         else
 565                 dma_bits = 32;
 566
 567         ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
 568         if (ret)
 569                 return ret;
 570
 571         ret = nouveau_mem_detect(dev);
 572         if (ret)
 573                 return ret;
 574
 575         dev_priv->fb_phys = pci_resource_start(dev->pdev, 1);
 576
 577         ret = nouveau_ttm_global_init(dev_priv);
 578         if (ret)
 579                 return ret;
 580
 581         ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
 582                                  dev_priv->ttm.bo_global_ref.ref.object,
 583                                  &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
 584                                  dma_bits <= 32 ? true : false);
 585         if (ret) {
 586                 NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
 587                 return ret;
 588         }
 589
 590         dev_priv->fb_available_size = dev_priv->vram_size;
 591         dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
 592         if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1))
 593                 dev_priv->fb_mappable_pages =
 594                         pci_resource_len(dev->pdev, 1);
 595         dev_priv->fb_mappable_pages >>= PAGE_SHIFT;
 596
 597         /* reserve space at end of VRAM for PRAMIN */
 598         if (dev_priv->chipset == 0x40 || dev_priv->chipset == 0x47 ||
 599             dev_priv->chipset == 0x49 || dev_priv->chipset == 0x4b)
 600                 dev_priv->ramin_rsvd_vram = (2 * 1024 * 1024);
 601         else
 602         if (dev_priv->card_type >= NV_40)
 603                 dev_priv->ramin_rsvd_vram = (1 * 1024 * 1024);
 604         else
 605                 dev_priv->ramin_rsvd_vram = (512 * 1024);
 606
 607         dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
 608         dev_priv->fb_aper_free = dev_priv->fb_available_size;
 609
 610         /* mappable vram */
 611         ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
 612                              dev_priv->fb_available_size >> PAGE_SHIFT);
 613         if (ret) {
 614                 NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
 615                 return ret;
 616         }
 617
 618         ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM,
 619                              0, 0, true, true, &dev_priv->vga_ram);
 620         if (ret == 0)
 621                 ret = nouveau_bo_pin(dev_priv->vga_ram, TTM_PL_FLAG_VRAM);
 622         if (ret) {
 623                 NV_WARN(dev, "failed to reserve VGA memory\n");
 624                 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
 625         }
 626
 627         dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1),
 628                                          pci_resource_len(dev->pdev, 1),
 629                                          DRM_MTRR_WC);
 630         return 0;
 631 }
 632
 633 int
 634 nouveau_mem_gart_init(struct drm_device *dev)
 635 {
 636         struct drm_nouveau_private *dev_priv = dev->dev_private;
 637         struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
 638         int ret;
 639
 640         dev_priv->gart_info.type = NOUVEAU_GART_NONE;
 641
 642 #if !defined(__powerpc__) && !defined(__ia64__)
 643         if (drm_device_is_agp(dev) && dev->agp && nouveau_agpmode) {
 644                 ret = nouveau_mem_init_agp(dev);
 645                 if (ret)
 646                         NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
 647         }
 648 #endif
 649
 650         if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
 651                 ret = nouveau_sgdma_init(dev);
 652                 if (ret) {
 653                         NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
 654                         return ret;
 655                 }
 656         }
 657
 658         NV_INFO(dev, "%d MiB GART (aperture)\n",
 659                 (int)(dev_priv->gart_info.aper_size >> 20));
 660         dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;
 661
 662         ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
 663                              dev_priv->gart_info.aper_size >> PAGE_SHIFT);
 664         if (ret) {
 665                 NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
 666                 return ret;
 667         }
 668
 669         return 0;
 670 }
 671
 672 void
 673 nouveau_mem_timing_init(struct drm_device *dev)
 674 {
 675         /* cards < NVC0 only */
 676         struct drm_nouveau_private *dev_priv = dev->dev_private;
 677         struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
 678         struct nouveau_pm_memtimings *memtimings = &pm->memtimings;
 679         struct nvbios *bios = &dev_priv->vbios;
 680         struct bit_entry P;
 681         u8 tUNK_0, tUNK_1, tUNK_2;
 682         u8 tRP;         /* Byte 3 */
 683         u8 tRAS;        /* Byte 5 */
 684         u8 tRFC;        /* Byte 7 */
 685         u8 tRC;         /* Byte 9 */
 686         u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14;
 687         u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21;
 688         u8 *mem = NULL, *entry;
 689         int i, recordlen, entries;
 690
 691         if (bios->type == NVBIOS_BIT) {
 692                 if (bit_table(dev, 'P', &P))
 693                         return;
 694
 695                 if (P.version == 1)
 696                         mem = ROMPTR(bios, P.data[4]);
 697                 else
 698                 if (P.version == 2)
 699                         mem = ROMPTR(bios, P.data[8]);
 700                 else {
 701                         NV_WARN(dev, "unknown mem for BIT P %d\n", P.version);
 702                 }
 703         } else {
 704                 NV_DEBUG(dev, "BMP version too old for memory\n");
 705                 return;
 706         }
 707
 708         if (!mem) {
 709                 NV_DEBUG(dev, "memory timing table pointer invalid\n");
 710                 return;
 711         }
 712
 713         if (mem[0] != 0x10) {
 714                 NV_WARN(dev, "memory timing table 0x%02x unknown\n", mem[0]);
 715                 return;
 716         }
 717
 718         /* validate record length */
 719         entries   = mem[2];
 720         recordlen = mem[3];
 721         if (recordlen < 15) {
 722                 NV_ERROR(dev, "mem timing table length unknown: %d\n", mem[3]);
 723                 return;
 724         }
 725
 726         /* parse vbios entries into common format */
 727         memtimings->timing =
 728                 kcalloc(entries, sizeof(*memtimings->timing), GFP_KERNEL);
 729         if (!memtimings->timing)
 730                 return;
 731
 732         entry = mem + mem[1];
 733         for (i = 0; i < entries; i++, entry += recordlen) {
 734                 struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i];
 735                 if (entry[0] == 0)
 736                         continue;
 737
 738                 tUNK_18 = 1;
 739                 tUNK_19 = 1;
 740                 tUNK_20 = 0;
 741                 tUNK_21 = 0;
 742                 switch (min(recordlen, 22)) {
 743                 case 22:
 744                         tUNK_21 = entry[21];
 745                 case 21:
 746                         tUNK_20 = entry[20];
 747                 case 20:
 748                         tUNK_19 = entry[19];
 749                 case 19:
 750                         tUNK_18 = entry[18];
 751                 default:
 752                         tUNK_0  = entry[0];
 753                         tUNK_1  = entry[1];
 754                         tUNK_2  = entry[2];
 755                         tRP     = entry[3];
 756                         tRAS    = entry[5];
 757                         tRFC    = entry[7];
 758                         tRC     = entry[9];
 759                         tUNK_10 = entry[10];
 760                         tUNK_11 = entry[11];
 761                         tUNK_12 = entry[12];
 762                         tUNK_13 = entry[13];
 763                         tUNK_14 = entry[14];
 764                         break;
 765                 }
 766
 767                 timing->reg_100220 = (tRC << 24 | tRFC << 16 | tRAS << 8 | tRP);
 768
 769                 /* XXX: I don't trust the -1's and +1's... they must come
 770                  *      from somewhere! */
 771                 timing->reg_100224 = ((tUNK_0 + tUNK_19 + 1) << 24 |
 772                                       tUNK_18 << 16 |
 773                                       (tUNK_1 + tUNK_19 + 1) << 8 |
 774                                       (tUNK_2 - 1));
 775
 776                 timing->reg_100228 = (tUNK_12 << 16 | tUNK_11 << 8 | tUNK_10);
 777                 if(recordlen > 19) {
 778                         timing->reg_100228 += (tUNK_19 - 1) << 24;
 779                 }/* I cannot back-up this else-statement right now
 780                          else {
 781                         timing->reg_100228 += tUNK_12 << 24;
 782                 }*/
 783
 784                 /* XXX: reg_10022c */
 785                 timing->reg_10022c = tUNK_2 - 1;
 786
 787                 timing->reg_100230 = (tUNK_20 << 24 | tUNK_21 << 16 |
 788                                       tUNK_13 << 8  | tUNK_13);
 789
 790                 /* XXX: +6? */
 791                 timing->reg_100234 = (tRAS << 24 | (tUNK_19 + 6) << 8 | tRC);
 792                 timing->reg_100234 += max(tUNK_10,tUNK_11) << 16;
 793
 794                 /* XXX; reg_100238, reg_10023c
 795                  * reg: 0x00??????
 796                  * reg_10023c:
 797                  *      0 for pre-NV50 cards
 798                  *      0x????0202 for NV50+ cards (empirical evidence) */
 799                 if(dev_priv->card_type >= NV_50) {
 800                         timing->reg_10023c = 0x202;
 801                 }
 802
 803                 NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", i,
 804                          timing->reg_100220, timing->reg_100224,
 805                          timing->reg_100228, timing->reg_10022c);
 806                 NV_DEBUG(dev, "         230: %08x %08x %08x %08x\n",
 807                          timing->reg_100230, timing->reg_100234,
 808                          timing->reg_100238, timing->reg_10023c);
 809         }
 810
 811         memtimings->nr_timing  = entries;
 812         memtimings->supported = true;
 813 }
 814
 815 void
 816 nouveau_mem_timing_fini(struct drm_device *dev)
 817 {
 818         struct drm_nouveau_private *dev_priv = dev->dev_private;
 819         struct nouveau_pm_memtimings *mem = &dev_priv->engine.pm.memtimings;
 820
 821         kfree(mem->timing);
 822 }