2 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3 * Copyright 2005 Stephane Marchesin
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
29 * Keith Whitwell <keith@tungstengraphics.com>
35 #include "drm_sarea.h"
37 #include "nouveau_drv.h"
38 #include "nouveau_pm.h"
39 #include "nouveau_mm.h"
40 #include "nouveau_vm.h"
43 * NV10-NV40 tiling helpers
47 nv10_mem_update_tile_region(struct drm_device *dev,
48 struct nouveau_tile_reg *tile, uint32_t addr,
49 uint32_t size, uint32_t pitch, uint32_t flags)
51 struct drm_nouveau_private *dev_priv = dev->dev_private;
52 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
53 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
54 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
55 int i = tile - dev_priv->tile.reg;
58 nouveau_fence_unref(&tile->fence);
61 pfb->free_tile_region(dev, i);
64 pfb->init_tile_region(dev, i, addr, size, pitch, flags);
66 spin_lock_irqsave(&dev_priv->context_switch_lock, save);
67 pfifo->reassign(dev, false);
68 pfifo->cache_pull(dev, false);
70 nouveau_wait_for_idle(dev);
72 pfb->set_tile_region(dev, i);
73 pgraph->set_tile_region(dev, i);
75 pfifo->cache_pull(dev, true);
76 pfifo->reassign(dev, true);
77 spin_unlock_irqrestore(&dev_priv->context_switch_lock, save);
80 static struct nouveau_tile_reg *
81 nv10_mem_get_tile_region(struct drm_device *dev, int i)
83 struct drm_nouveau_private *dev_priv = dev->dev_private;
84 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
86 spin_lock(&dev_priv->tile.lock);
89 (!tile->fence || nouveau_fence_signalled(tile->fence)))
94 spin_unlock(&dev_priv->tile.lock);
99 nv10_mem_put_tile_region(struct drm_device *dev, struct nouveau_tile_reg *tile,
100 struct nouveau_fence *fence)
102 struct drm_nouveau_private *dev_priv = dev->dev_private;
105 spin_lock(&dev_priv->tile.lock);
107 /* Mark it as pending. */
109 nouveau_fence_ref(fence);
113 spin_unlock(&dev_priv->tile.lock);
117 struct nouveau_tile_reg *
118 nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
119 uint32_t pitch, uint32_t flags)
121 struct drm_nouveau_private *dev_priv = dev->dev_private;
122 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
123 struct nouveau_tile_reg *tile, *found = NULL;
126 for (i = 0; i < pfb->num_tiles; i++) {
127 tile = nv10_mem_get_tile_region(dev, i);
129 if (pitch && !found) {
133 } else if (tile && tile->pitch) {
134 /* Kill an unused tile region. */
135 nv10_mem_update_tile_region(dev, tile, 0, 0, 0, 0);
138 nv10_mem_put_tile_region(dev, tile, NULL);
142 nv10_mem_update_tile_region(dev, found, addr, size,
151 nouveau_mem_vram_fini(struct drm_device *dev)
153 struct drm_nouveau_private *dev_priv = dev->dev_private;
155 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
157 ttm_bo_device_release(&dev_priv->ttm.bdev);
159 nouveau_ttm_global_release(dev_priv);
161 if (dev_priv->fb_mtrr >= 0) {
162 drm_mtrr_del(dev_priv->fb_mtrr,
163 pci_resource_start(dev->pdev, 1),
164 pci_resource_len(dev->pdev, 1), DRM_MTRR_WC);
165 dev_priv->fb_mtrr = -1;
170 nouveau_mem_gart_fini(struct drm_device *dev)
172 nouveau_sgdma_takedown(dev);
174 if (drm_core_has_AGP(dev) && dev->agp) {
175 struct drm_agp_mem *entry, *tempe;
177 /* Remove AGP resources, but leave dev->agp
178 intact until drv_cleanup is called. */
179 list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
181 drm_unbind_agp(entry->memory);
182 drm_free_agp(entry->memory, entry->pages);
185 INIT_LIST_HEAD(&dev->agp->memory);
187 if (dev->agp->acquired)
188 drm_agp_release(dev);
190 dev->agp->acquired = 0;
191 dev->agp->enabled = 0;
196 nouveau_mem_detect_nv04(struct drm_device *dev)
198 uint32_t boot0 = nv_rd32(dev, NV04_PFB_BOOT_0);
200 if (boot0 & 0x00000100)
201 return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;
203 switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
204 case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
205 return 32 * 1024 * 1024;
206 case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
207 return 16 * 1024 * 1024;
208 case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
209 return 8 * 1024 * 1024;
210 case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
211 return 4 * 1024 * 1024;
218 nouveau_mem_detect_nforce(struct drm_device *dev)
220 struct drm_nouveau_private *dev_priv = dev->dev_private;
221 struct pci_dev *bridge;
224 bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
226 NV_ERROR(dev, "no bridge device\n");
230 if (dev_priv->flags & NV_NFORCE) {
231 pci_read_config_dword(bridge, 0x7C, &mem);
232 return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024;
234 if (dev_priv->flags & NV_NFORCE2) {
235 pci_read_config_dword(bridge, 0x84, &mem);
236 return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024;
239 NV_ERROR(dev, "impossible!\n");
244 nouveau_mem_detect(struct drm_device *dev)
246 struct drm_nouveau_private *dev_priv = dev->dev_private;
248 if (dev_priv->card_type == NV_04) {
249 dev_priv->vram_size = nouveau_mem_detect_nv04(dev);
251 if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) {
252 dev_priv->vram_size = nouveau_mem_detect_nforce(dev);
254 if (dev_priv->card_type < NV_50) {
255 dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA);
256 dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
259 if (dev_priv->vram_size)
265 nouveau_mem_flags_valid(struct drm_device *dev, u32 tile_flags)
267 if (!(tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK))
275 get_agp_mode(struct drm_device *dev, unsigned long mode)
277 struct drm_nouveau_private *dev_priv = dev->dev_private;
280 * FW seems to be broken on nv18, it makes the card lock up
283 if (dev_priv->chipset == 0x18)
284 mode &= ~PCI_AGP_COMMAND_FW;
287 * AGP mode set in the command line.
289 if (nouveau_agpmode > 0) {
290 bool agpv3 = mode & 0x8;
291 int rate = agpv3 ? nouveau_agpmode / 4 : nouveau_agpmode;
293 mode = (mode & ~0x7) | (rate & 0x7);
301 nouveau_mem_reset_agp(struct drm_device *dev)
304 uint32_t saved_pci_nv_1, pmc_enable;
307 /* First of all, disable fast writes, otherwise if it's
308 * already enabled in the AGP bridge and we disable the card's
309 * AGP controller we might be locking ourselves out of it. */
310 if ((nv_rd32(dev, NV04_PBUS_PCI_NV_19) |
311 dev->agp->mode) & PCI_AGP_COMMAND_FW) {
312 struct drm_agp_info info;
313 struct drm_agp_mode mode;
315 ret = drm_agp_info(dev, &info);
319 mode.mode = get_agp_mode(dev, info.mode) & ~PCI_AGP_COMMAND_FW;
320 ret = drm_agp_enable(dev, mode);
325 saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);
327 /* clear busmaster bit */
328 nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
330 nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0);
332 /* power cycle pgraph, if enabled */
333 pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
334 if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
335 nv_wr32(dev, NV03_PMC_ENABLE,
336 pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
337 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
338 NV_PMC_ENABLE_PGRAPH);
341 /* and restore (gives effect of resetting AGP) */
342 nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
349 nouveau_mem_init_agp(struct drm_device *dev)
352 struct drm_nouveau_private *dev_priv = dev->dev_private;
353 struct drm_agp_info info;
354 struct drm_agp_mode mode;
357 if (!dev->agp->acquired) {
358 ret = drm_agp_acquire(dev);
360 NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
365 nouveau_mem_reset_agp(dev);
367 ret = drm_agp_info(dev, &info);
369 NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
373 /* see agp.h for the AGPSTAT_* modes available */
374 mode.mode = get_agp_mode(dev, info.mode);
375 ret = drm_agp_enable(dev, mode);
377 NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
381 dev_priv->gart_info.type = NOUVEAU_GART_AGP;
382 dev_priv->gart_info.aper_base = info.aperture_base;
383 dev_priv->gart_info.aper_size = info.aperture_size;
389 nouveau_mem_vram_init(struct drm_device *dev)
391 struct drm_nouveau_private *dev_priv = dev->dev_private;
392 struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
396 if (dev_priv->card_type >= NV_50) {
397 if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
400 if (drm_pci_device_is_pcie(dev) &&
401 dev_priv->chipset != 0x40 &&
402 dev_priv->chipset != 0x45) {
403 if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(39)))
407 ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
411 dev_priv->fb_phys = pci_resource_start(dev->pdev, 1);
413 ret = nouveau_ttm_global_init(dev_priv);
417 ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
418 dev_priv->ttm.bo_global_ref.ref.object,
419 &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
420 dma_bits <= 32 ? true : false);
422 NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
426 /* reserve space at end of VRAM for PRAMIN */
427 if (dev_priv->chipset == 0x40 || dev_priv->chipset == 0x47 ||
428 dev_priv->chipset == 0x49 || dev_priv->chipset == 0x4b)
429 dev_priv->ramin_rsvd_vram = (2 * 1024 * 1024);
431 if (dev_priv->card_type >= NV_40)
432 dev_priv->ramin_rsvd_vram = (1 * 1024 * 1024);
434 dev_priv->ramin_rsvd_vram = (512 * 1024);
436 ret = dev_priv->engine.vram.init(dev);
440 NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
441 if (dev_priv->vram_sys_base) {
442 NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
443 dev_priv->vram_sys_base);
446 dev_priv->fb_available_size = dev_priv->vram_size;
447 dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
448 if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1))
449 dev_priv->fb_mappable_pages = pci_resource_len(dev->pdev, 1);
450 dev_priv->fb_mappable_pages >>= PAGE_SHIFT;
452 dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
453 dev_priv->fb_aper_free = dev_priv->fb_available_size;
456 ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
457 dev_priv->fb_available_size >> PAGE_SHIFT);
459 NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
463 if (dev_priv->card_type < NV_50) {
464 ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM,
465 0, 0, &dev_priv->vga_ram);
467 ret = nouveau_bo_pin(dev_priv->vga_ram,
471 NV_WARN(dev, "failed to reserve VGA memory\n");
472 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
476 dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1),
477 pci_resource_len(dev->pdev, 1),
483 nouveau_mem_gart_init(struct drm_device *dev)
485 struct drm_nouveau_private *dev_priv = dev->dev_private;
486 struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
489 dev_priv->gart_info.type = NOUVEAU_GART_NONE;
491 #if !defined(__powerpc__) && !defined(__ia64__)
492 if (drm_pci_device_is_agp(dev) && dev->agp && nouveau_agpmode) {
493 ret = nouveau_mem_init_agp(dev);
495 NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
499 if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
500 ret = nouveau_sgdma_init(dev);
502 NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
507 NV_INFO(dev, "%d MiB GART (aperture)\n",
508 (int)(dev_priv->gart_info.aper_size >> 20));
509 dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;
511 ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
512 dev_priv->gart_info.aper_size >> PAGE_SHIFT);
514 NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
522 nouveau_mem_timing_init(struct drm_device *dev)
524 /* cards < NVC0 only */
525 struct drm_nouveau_private *dev_priv = dev->dev_private;
526 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
527 struct nouveau_pm_memtimings *memtimings = &pm->memtimings;
528 struct nvbios *bios = &dev_priv->vbios;
530 u8 tUNK_0, tUNK_1, tUNK_2;
532 u8 tRAS; /* Byte 5 */
533 u8 tRFC; /* Byte 7 */
535 u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14;
536 u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21;
537 u8 *mem = NULL, *entry;
538 int i, recordlen, entries;
540 if (bios->type == NVBIOS_BIT) {
541 if (bit_table(dev, 'P', &P))
545 mem = ROMPTR(bios, P.data[4]);
548 mem = ROMPTR(bios, P.data[8]);
550 NV_WARN(dev, "unknown mem for BIT P %d\n", P.version);
553 NV_DEBUG(dev, "BMP version too old for memory\n");
558 NV_DEBUG(dev, "memory timing table pointer invalid\n");
562 if (mem[0] != 0x10) {
563 NV_WARN(dev, "memory timing table 0x%02x unknown\n", mem[0]);
567 /* validate record length */
570 if (recordlen < 15) {
571 NV_ERROR(dev, "mem timing table length unknown: %d\n", mem[3]);
575 /* parse vbios entries into common format */
577 kcalloc(entries, sizeof(*memtimings->timing), GFP_KERNEL);
578 if (!memtimings->timing)
581 entry = mem + mem[1];
582 for (i = 0; i < entries; i++, entry += recordlen) {
583 struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i];
591 switch (min(recordlen, 22)) {
616 timing->reg_100220 = (tRC << 24 | tRFC << 16 | tRAS << 8 | tRP);
618 /* XXX: I don't trust the -1's and +1's... they must come
620 timing->reg_100224 = ((tUNK_0 + tUNK_19 + 1) << 24 |
622 (tUNK_1 + tUNK_19 + 1) << 8 |
625 timing->reg_100228 = (tUNK_12 << 16 | tUNK_11 << 8 | tUNK_10);
627 timing->reg_100228 += (tUNK_19 - 1) << 24;
628 }/* I cannot back-up this else-statement right now
630 timing->reg_100228 += tUNK_12 << 24;
633 /* XXX: reg_10022c */
634 timing->reg_10022c = tUNK_2 - 1;
636 timing->reg_100230 = (tUNK_20 << 24 | tUNK_21 << 16 |
637 tUNK_13 << 8 | tUNK_13);
640 timing->reg_100234 = (tRAS << 24 | (tUNK_19 + 6) << 8 | tRC);
641 timing->reg_100234 += max(tUNK_10,tUNK_11) << 16;
643 /* XXX; reg_100238, reg_10023c
646 * 0 for pre-NV50 cards
647 * 0x????0202 for NV50+ cards (empirical evidence) */
648 if(dev_priv->card_type >= NV_50) {
649 timing->reg_10023c = 0x202;
652 NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", i,
653 timing->reg_100220, timing->reg_100224,
654 timing->reg_100228, timing->reg_10022c);
655 NV_DEBUG(dev, " 230: %08x %08x %08x %08x\n",
656 timing->reg_100230, timing->reg_100234,
657 timing->reg_100238, timing->reg_10023c);
660 memtimings->nr_timing = entries;
661 memtimings->supported = true;
665 nouveau_mem_timing_fini(struct drm_device *dev)
667 struct drm_nouveau_private *dev_priv = dev->dev_private;
668 struct nouveau_pm_memtimings *mem = &dev_priv->engine.pm.memtimings;
674 nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long p_size)
676 struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
677 struct nouveau_mm *mm;
678 u64 size, block, rsvd;
681 rsvd = (256 * 1024); /* vga memory */
682 size = (p_size << PAGE_SHIFT) - rsvd;
683 block = dev_priv->vram_rblock_size;
685 ret = nouveau_mm_init(&mm, rsvd >> 12, size >> 12, block >> 12);
694 nouveau_vram_manager_fini(struct ttm_mem_type_manager *man)
696 struct nouveau_mm *mm = man->priv;
699 ret = nouveau_mm_fini(&mm);
708 nouveau_vram_manager_del(struct ttm_mem_type_manager *man,
709 struct ttm_mem_reg *mem)
711 struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
712 struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
713 struct nouveau_mem *node = mem->mm_node;
714 struct drm_device *dev = dev_priv->dev;
716 if (node->tmp_vma.node) {
717 nouveau_vm_unmap(&node->tmp_vma);
718 nouveau_vm_put(&node->tmp_vma);
721 vram->put(dev, (struct nouveau_mem **)&mem->mm_node);
725 nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
726 struct ttm_buffer_object *bo,
727 struct ttm_placement *placement,
728 struct ttm_mem_reg *mem)
730 struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
731 struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
732 struct drm_device *dev = dev_priv->dev;
733 struct nouveau_bo *nvbo = nouveau_bo(bo);
734 struct nouveau_mem *node;
738 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG)
739 size_nc = 1 << nvbo->vma.node->type;
741 ret = vram->get(dev, mem->num_pages << PAGE_SHIFT,
742 mem->page_alignment << PAGE_SHIFT, size_nc,
743 (nvbo->tile_flags >> 8) & 0x3ff, &node);
747 node->page_shift = 12;
749 node->page_shift = nvbo->vma.node->type;
752 mem->start = node->offset >> PAGE_SHIFT;
757 nouveau_vram_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
759 struct nouveau_mm *mm = man->priv;
760 struct nouveau_mm_node *r;
761 u32 total = 0, free = 0;
763 mutex_lock(&mm->mutex);
764 list_for_each_entry(r, &mm->nodes, nl_entry) {
765 printk(KERN_DEBUG "%s %d: 0x%010llx 0x%010llx\n",
766 prefix, r->type, ((u64)r->offset << 12),
767 (((u64)r->offset + r->length) << 12));
773 mutex_unlock(&mm->mutex);
775 printk(KERN_DEBUG "%s total: 0x%010llx free: 0x%010llx\n",
776 prefix, (u64)total << 12, (u64)free << 12);
777 printk(KERN_DEBUG "%s block: 0x%08x\n",
778 prefix, mm->block_size << 12);
781 const struct ttm_mem_type_manager_func nouveau_vram_manager = {
782 nouveau_vram_manager_init,
783 nouveau_vram_manager_fini,
784 nouveau_vram_manager_new,
785 nouveau_vram_manager_del,
786 nouveau_vram_manager_debug
790 nouveau_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
796 nouveau_gart_manager_fini(struct ttm_mem_type_manager *man)
802 nouveau_gart_manager_del(struct ttm_mem_type_manager *man,
803 struct ttm_mem_reg *mem)
805 struct nouveau_mem *node = mem->mm_node;
807 if (node->tmp_vma.node) {
808 nouveau_vm_unmap(&node->tmp_vma);
809 nouveau_vm_put(&node->tmp_vma);
815 nouveau_gart_manager_new(struct ttm_mem_type_manager *man,
816 struct ttm_buffer_object *bo,
817 struct ttm_placement *placement,
818 struct ttm_mem_reg *mem)
820 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
821 struct nouveau_bo *nvbo = nouveau_bo(bo);
822 struct nouveau_vma *vma = &nvbo->vma;
823 struct nouveau_vm *vm = vma->vm;
824 struct nouveau_mem *node;
827 if (unlikely((mem->num_pages << PAGE_SHIFT) >=
828 dev_priv->gart_info.aper_size))
831 node = kzalloc(sizeof(*node), GFP_KERNEL);
835 /* This node must be for evicting large-paged VRAM
836 * to system memory. Due to a nv50 limitation of
837 * not being able to mix large/small pages within
838 * the same PDE, we need to create a temporary
839 * small-paged VMA for the eviction.
841 if (vma->node->type != vm->spg_shift) {
842 ret = nouveau_vm_get(vm, (u64)vma->node->length << 12,
843 vm->spg_shift, NV_MEM_ACCESS_RW,
851 node->page_shift = nvbo->vma.node->type;
858 nouveau_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
862 const struct ttm_mem_type_manager_func nouveau_gart_manager = {
863 nouveau_gart_manager_init,
864 nouveau_gart_manager_fini,
865 nouveau_gart_manager_new,
866 nouveau_gart_manager_del,
867 nouveau_gart_manager_debug