2 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3 * Copyright 2005 Stephane Marchesin
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
29 * Ben Skeggs <bskeggs@redhat.com>
30 * Roy Spliet <r.spliet@student.tudelft.nl>
33 #include "nouveau_drm.h"
34 #include "nouveau_pm.h"
36 #include <subdev/fb.h>
39 nv40_mem_timing_calc(struct drm_device *dev, u32 freq,
40 struct nouveau_pm_tbl_entry *e, u8 len,
41 struct nouveau_pm_memtiming *boot,
42 struct nouveau_pm_memtiming *t)
44 struct nouveau_drm *drm = nouveau_drm(dev);
46 t->reg[0] = (e->tRP << 24 | e->tRAS << 16 | e->tRFC << 8 | e->tRC);
48 /* XXX: I don't trust the -1's and +1's... they must come
50 t->reg[1] = (e->tWR + 2 + (t->tCWL - 1)) << 24 |
52 (e->tWTR + 2 + (t->tCWL - 1)) << 8 |
53 (e->tCL + 2 - (t->tCWL - 1));
55 t->reg[2] = 0x20200000 |
56 ((t->tCWL - 1) << 24 |
61 NV_DEBUG(drm, "Entry %d: 220: %08x %08x %08x\n", t->id,
62 t->reg[0], t->reg[1], t->reg[2]);
67 nv50_mem_timing_calc(struct drm_device *dev, u32 freq,
68 struct nouveau_pm_tbl_entry *e, u8 len,
69 struct nouveau_pm_memtiming *boot,
70 struct nouveau_pm_memtiming *t)
72 struct nouveau_device *device = nouveau_dev(dev);
73 struct nouveau_fb *pfb = nouveau_fb(device);
74 struct nouveau_drm *drm = nouveau_drm(dev);
76 uint8_t unk18 = 1, unk20 = 0, unk21 = 0, tmp7_3;
78 if (bit_table(dev, 'P', &P))
81 switch (min(len, (u8) 22)) {
94 t->reg[0] = (e->tRP << 24 | e->tRAS << 16 | e->tRFC << 8 | e->tRC);
96 t->reg[1] = (e->tWR + 2 + (t->tCWL - 1)) << 24 |
97 max(unk18, (u8) 1) << 16 |
98 (e->tWTR + 2 + (t->tCWL - 1)) << 8;
100 t->reg[2] = ((t->tCWL - 1) << 24 |
105 t->reg[4] = e->tUNK_13 << 8 | e->tUNK_13;
107 t->reg[5] = (e->tRFC << 24 | max(e->tRCDRD, e->tRCDWR) << 16 | e->tRP);
109 t->reg[8] = boot->reg[8] & 0xffffff00;
111 if (P.version == 1) {
112 t->reg[1] |= (e->tCL + 2 - (t->tCWL - 1));
114 t->reg[3] = (0x14 + e->tCL) << 24 |
119 t->reg[4] |= boot->reg[4] & 0xffff0000;
121 t->reg[6] = (0x33 - t->tCWL) << 16 |
123 (0x2e + e->tCL - t->tCWL);
125 t->reg[7] = 0x4000202 | (e->tCL - 1) << 16;
127 /* XXX: P.version == 1 only has DDR2 and GDDR3? */
128 if (pfb->ram.type == NV_MEM_TYPE_DDR2) {
129 t->reg[5] |= (e->tCL + 3) << 8;
130 t->reg[6] |= (t->tCWL - 2) << 8;
131 t->reg[8] |= (e->tCL - 4);
133 t->reg[5] |= (e->tCL + 2) << 8;
134 t->reg[6] |= t->tCWL << 8;
135 t->reg[8] |= (e->tCL - 2);
138 t->reg[1] |= (5 + e->tCL - (t->tCWL));
140 /* XXX: 0xb? 0x30? */
141 t->reg[3] = (0x30 + e->tCL) << 24 |
142 (boot->reg[3] & 0x00ff0000)|
143 (0xb + e->tCL) << 8 |
146 t->reg[4] |= (unk20 << 24 | unk21 << 16);
149 t->reg[5] |= (t->tCWL + 6) << 8;
151 t->reg[6] = (0x5a + e->tCL) << 16 |
152 (6 - e->tCL + t->tCWL) << 8 |
153 (0x50 + e->tCL - t->tCWL);
155 tmp7_3 = (boot->reg[7] & 0xff000000) >> 24;
156 t->reg[7] = (tmp7_3 << 24) |
157 ((tmp7_3 - 6 + e->tCL) << 16) |
161 NV_DEBUG(drm, "Entry %d: 220: %08x %08x %08x %08x\n", t->id,
162 t->reg[0], t->reg[1], t->reg[2], t->reg[3]);
163 NV_DEBUG(drm, " 230: %08x %08x %08x %08x\n",
164 t->reg[4], t->reg[5], t->reg[6], t->reg[7]);
165 NV_DEBUG(drm, " 240: %08x\n", t->reg[8]);
170 nvc0_mem_timing_calc(struct drm_device *dev, u32 freq,
171 struct nouveau_pm_tbl_entry *e, u8 len,
172 struct nouveau_pm_memtiming *boot,
173 struct nouveau_pm_memtiming *t)
175 struct nouveau_drm *drm = nouveau_drm(dev);
180 t->reg[0] = (e->tRP << 24 | (e->tRAS & 0x7f) << 17 |
181 e->tRFC << 8 | e->tRC);
183 t->reg[1] = (boot->reg[1] & 0xff000000) |
184 (e->tRCDWR & 0x0f) << 20 |
185 (e->tRCDRD & 0x0f) << 14 |
189 t->reg[2] = (boot->reg[2] & 0xff0000ff) |
190 e->tWR << 16 | e->tWTR << 8;
192 t->reg[3] = (e->tUNK_20 & 0x1f) << 9 |
193 (e->tUNK_21 & 0xf) << 5 |
196 t->reg[4] = (boot->reg[4] & 0xfff00fff) |
197 (e->tRRD&0x1f) << 15;
199 NV_DEBUG(drm, "Entry %d: 290: %08x %08x %08x %08x\n", t->id,
200 t->reg[0], t->reg[1], t->reg[2], t->reg[3]);
201 NV_DEBUG(drm, " 2a0: %08x\n", t->reg[4]);
206 * MR generation methods
210 nouveau_mem_ddr2_mr(struct drm_device *dev, u32 freq,
211 struct nouveau_pm_tbl_entry *e, u8 len,
212 struct nouveau_pm_memtiming *boot,
213 struct nouveau_pm_memtiming *t)
215 struct nouveau_drm *drm = nouveau_drm(dev);
217 t->drive_strength = 0;
221 t->odt = e->RAM_FT1 & 0x07;
224 if (e->tCL >= NV_MEM_CL_DDR2_MAX) {
225 NV_WARN(drm, "(%u) Invalid tCL: %u", t->id, e->tCL);
229 if (e->tWR >= NV_MEM_WR_DDR2_MAX) {
230 NV_WARN(drm, "(%u) Invalid tWR: %u", t->id, e->tWR);
235 NV_WARN(drm, "(%u) Invalid odt value, assuming disabled: %x",
240 t->mr[0] = (boot->mr[0] & 0x100f) |
243 t->mr[1] = (boot->mr[1] & 0x101fbb) |
244 (t->odt & 0x1) << 2 |
247 NV_DEBUG(drm, "(%u) MR: %08x", t->id, t->mr[0]);
251 static const uint8_t nv_mem_wr_lut_ddr3[NV_MEM_WR_DDR3_MAX] = {
252 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
255 nouveau_mem_ddr3_mr(struct drm_device *dev, u32 freq,
256 struct nouveau_pm_tbl_entry *e, u8 len,
257 struct nouveau_pm_memtiming *boot,
258 struct nouveau_pm_memtiming *t)
260 struct nouveau_drm *drm = nouveau_drm(dev);
263 t->drive_strength = 0;
267 t->odt = e->RAM_FT1 & 0x07;
270 if (e->tCL >= NV_MEM_CL_DDR3_MAX || e->tCL < 4) {
271 NV_WARN(drm, "(%u) Invalid tCL: %u", t->id, e->tCL);
275 if (e->tWR >= NV_MEM_WR_DDR3_MAX || e->tWR < 4) {
276 NV_WARN(drm, "(%u) Invalid tWR: %u", t->id, e->tWR);
281 NV_WARN(drm, "(%u) Invalid tCWL: %u", t->id, e->tCWL);
285 t->mr[0] = (boot->mr[0] & 0x180b) |
289 (nv_mem_wr_lut_ddr3[e->tWR]) << 9;
290 t->mr[1] = (boot->mr[1] & 0x101dbb) |
291 (t->odt & 0x1) << 2 |
292 (t->odt & 0x2) << 5 |
294 t->mr[2] = (boot->mr[2] & 0x20ffb7) | (e->tCWL - 5) << 3;
296 NV_DEBUG(drm, "(%u) MR: %08x %08x", t->id, t->mr[0], t->mr[2]);
300 static const uint8_t nv_mem_cl_lut_gddr3[NV_MEM_CL_GDDR3_MAX] = {
301 0, 0, 0, 0, 4, 5, 6, 7, 0, 1, 2, 3, 8, 9, 10, 11};
302 static const uint8_t nv_mem_wr_lut_gddr3[NV_MEM_WR_GDDR3_MAX] = {
303 0, 0, 0, 0, 0, 2, 3, 8, 9, 10, 11, 0, 0, 1, 1, 0, 3};
306 nouveau_mem_gddr3_mr(struct drm_device *dev, u32 freq,
307 struct nouveau_pm_tbl_entry *e, u8 len,
308 struct nouveau_pm_memtiming *boot,
309 struct nouveau_pm_memtiming *t)
311 struct nouveau_drm *drm = nouveau_drm(dev);
314 t->drive_strength = boot->drive_strength;
317 t->drive_strength = (e->RAM_FT1 & 0x30) >> 4;
318 t->odt = e->RAM_FT1 & 0x07;
321 if (e->tCL >= NV_MEM_CL_GDDR3_MAX) {
322 NV_WARN(drm, "(%u) Invalid tCL: %u", t->id, e->tCL);
326 if (e->tWR >= NV_MEM_WR_GDDR3_MAX) {
327 NV_WARN(drm, "(%u) Invalid tWR: %u", t->id, e->tWR);
332 NV_WARN(drm, "(%u) Invalid odt value, assuming autocal: %x",
337 t->mr[0] = (boot->mr[0] & 0xe0b) |
339 ((nv_mem_cl_lut_gddr3[e->tCL] & 0x7) << 4) |
340 ((nv_mem_cl_lut_gddr3[e->tCL] & 0x8) >> 2);
341 t->mr[1] = (boot->mr[1] & 0x100f40) | t->drive_strength |
343 (nv_mem_wr_lut_gddr3[e->tWR] & 0xf) << 4;
344 t->mr[2] = boot->mr[2];
346 NV_DEBUG(drm, "(%u) MR: %08x %08x %08x", t->id,
347 t->mr[0], t->mr[1], t->mr[2]);
352 nouveau_mem_gddr5_mr(struct drm_device *dev, u32 freq,
353 struct nouveau_pm_tbl_entry *e, u8 len,
354 struct nouveau_pm_memtiming *boot,
355 struct nouveau_pm_memtiming *t)
357 struct nouveau_drm *drm = nouveau_drm(dev);
360 t->drive_strength = boot->drive_strength;
363 t->drive_strength = (e->RAM_FT1 & 0x30) >> 4;
364 t->odt = e->RAM_FT1 & 0x03;
367 if (e->tCL >= NV_MEM_CL_GDDR5_MAX) {
368 NV_WARN(drm, "(%u) Invalid tCL: %u", t->id, e->tCL);
372 if (e->tWR >= NV_MEM_WR_GDDR5_MAX) {
373 NV_WARN(drm, "(%u) Invalid tWR: %u", t->id, e->tWR);
378 NV_WARN(drm, "(%u) Invalid odt value, assuming autocal: %x",
383 t->mr[0] = (boot->mr[0] & 0x007) |
384 ((e->tCL - 5) << 3) |
386 t->mr[1] = (boot->mr[1] & 0x1007f0) |
390 NV_DEBUG(drm, "(%u) MR: %08x %08x", t->id, t->mr[0], t->mr[1]);
395 nouveau_mem_timing_calc(struct drm_device *dev, u32 freq,
396 struct nouveau_pm_memtiming *t)
398 struct nouveau_device *device = nouveau_dev(dev);
399 struct nouveau_fb *pfb = nouveau_fb(device);
400 struct nouveau_pm *pm = nouveau_pm(dev);
401 struct nouveau_pm_memtiming *boot = &pm->boot.timing;
402 struct nouveau_pm_tbl_entry *e;
403 u8 ver, len, *ptr, *ramcfg;
406 ptr = nouveau_perf_timing(dev, freq, &ver, &len);
407 if (!ptr || ptr[0] == 0x00) {
411 e = (struct nouveau_pm_tbl_entry *)ptr;
413 t->tCWL = boot->tCWL;
415 switch (device->card_type) {
417 ret = nv40_mem_timing_calc(dev, freq, e, len, boot, t);
420 ret = nv50_mem_timing_calc(dev, freq, e, len, boot, t);
424 ret = nvc0_mem_timing_calc(dev, freq, e, len, boot, t);
431 switch (pfb->ram.type * !ret) {
432 case NV_MEM_TYPE_GDDR3:
433 ret = nouveau_mem_gddr3_mr(dev, freq, e, len, boot, t);
435 case NV_MEM_TYPE_GDDR5:
436 ret = nouveau_mem_gddr5_mr(dev, freq, e, len, boot, t);
438 case NV_MEM_TYPE_DDR2:
439 ret = nouveau_mem_ddr2_mr(dev, freq, e, len, boot, t);
441 case NV_MEM_TYPE_DDR3:
442 ret = nouveau_mem_ddr3_mr(dev, freq, e, len, boot, t);
449 ramcfg = nouveau_perf_ramcfg(dev, freq, &ver, &len);
454 dll_off = !!(ramcfg[3] & 0x04);
456 dll_off = !!(ramcfg[2] & 0x40);
458 switch (pfb->ram.type) {
459 case NV_MEM_TYPE_GDDR3:
460 t->mr[1] &= ~0x00000040;
461 t->mr[1] |= 0x00000040 * dll_off;
464 t->mr[1] &= ~0x00000001;
465 t->mr[1] |= 0x00000001 * dll_off;
474 nouveau_mem_timing_read(struct drm_device *dev, struct nouveau_pm_memtiming *t)
476 struct nouveau_device *device = nouveau_dev(dev);
477 struct nouveau_fb *pfb = nouveau_fb(device);
478 u32 timing_base, timing_regs, mr_base;
481 if (device->card_type >= 0xC0) {
482 timing_base = 0x10f290;
485 timing_base = 0x100220;
491 switch (device->card_type) {
507 for(i = 0; i < timing_regs; i++)
508 t->reg[i] = nv_rd32(device, timing_base + (0x04 * i));
511 if (device->card_type < NV_C0) {
512 t->tCWL = ((nv_rd32(device, 0x100228) & 0x0f000000) >> 24) + 1;
513 } else if (device->card_type <= NV_D0) {
514 t->tCWL = ((nv_rd32(device, 0x10f294) & 0x00000f80) >> 7);
517 t->mr[0] = nv_rd32(device, mr_base);
518 t->mr[1] = nv_rd32(device, mr_base + 0x04);
519 t->mr[2] = nv_rd32(device, mr_base + 0x20);
520 t->mr[3] = nv_rd32(device, mr_base + 0x24);
523 t->drive_strength = 0;
525 switch (pfb->ram.type) {
526 case NV_MEM_TYPE_DDR3:
527 t->odt |= (t->mr[1] & 0x200) >> 7;
528 case NV_MEM_TYPE_DDR2:
529 t->odt |= (t->mr[1] & 0x04) >> 2 |
530 (t->mr[1] & 0x40) >> 5;
532 case NV_MEM_TYPE_GDDR3:
533 case NV_MEM_TYPE_GDDR5:
534 t->drive_strength = t->mr[1] & 0x03;
535 t->odt = (t->mr[1] & 0x0c) >> 2;
543 nouveau_mem_exec(struct nouveau_mem_exec_func *exec,
544 struct nouveau_pm_level *perflvl)
546 struct nouveau_drm *drm = nouveau_drm(exec->dev);
547 struct nouveau_device *device = nouveau_dev(exec->dev);
548 struct nouveau_fb *pfb = nouveau_fb(device);
549 struct nouveau_pm_memtiming *info = &perflvl->timing;
550 u32 tMRD = 1000, tCKSRE = 0, tCKSRX = 0, tXS = 0, tDLLK = 0;
551 u32 mr[3] = { info->mr[0], info->mr[1], info->mr[2] };
554 switch (pfb->ram.type) {
555 case NV_MEM_TYPE_DDR2:
557 mr1_dlloff = 0x00000001;
559 case NV_MEM_TYPE_DDR3:
563 mr1_dlloff = 0x00000001;
565 case NV_MEM_TYPE_GDDR3:
567 mr1_dlloff = 0x00000040;
570 NV_ERROR(drm, "cannot reclock unsupported memtype\n");
574 /* fetch current MRs */
575 switch (pfb->ram.type) {
576 case NV_MEM_TYPE_GDDR3:
577 case NV_MEM_TYPE_DDR3:
578 mr[2] = exec->mrg(exec, 2);
580 mr[1] = exec->mrg(exec, 1);
581 mr[0] = exec->mrg(exec, 0);
585 /* DLL 'on' -> DLL 'off' mode, disable before entering self-refresh */
586 if (!(mr[1] & mr1_dlloff) && (info->mr[1] & mr1_dlloff)) {
587 exec->precharge(exec);
588 exec->mrs (exec, 1, mr[1] | mr1_dlloff);
589 exec->wait(exec, tMRD);
592 /* enter self-refresh mode */
593 exec->precharge(exec);
596 exec->refresh_auto(exec, false);
597 exec->refresh_self(exec, true);
598 exec->wait(exec, tCKSRE);
600 /* modify input clock frequency */
601 exec->clock_set(exec);
603 /* exit self-refresh mode */
604 exec->wait(exec, tCKSRX);
605 exec->precharge(exec);
606 exec->refresh_self(exec, false);
607 exec->refresh_auto(exec, true);
608 exec->wait(exec, tXS);
609 exec->wait(exec, tXS);
612 if (mr[2] != info->mr[2]) {
613 exec->mrs (exec, 2, info->mr[2]);
614 exec->wait(exec, tMRD);
617 if (mr[1] != info->mr[1]) {
618 /* need to keep DLL off until later, at least on GDDR3 */
619 exec->mrs (exec, 1, info->mr[1] | (mr[1] & mr1_dlloff));
620 exec->wait(exec, tMRD);
623 if (mr[0] != info->mr[0]) {
624 exec->mrs (exec, 0, info->mr[0]);
625 exec->wait(exec, tMRD);
628 /* update PFB timing registers */
629 exec->timing_set(exec);
631 /* DLL (enable + ) reset */
632 if (!(info->mr[1] & mr1_dlloff)) {
633 if (mr[1] & mr1_dlloff) {
634 exec->mrs (exec, 1, info->mr[1]);
635 exec->wait(exec, tMRD);
637 exec->mrs (exec, 0, info->mr[0] | 0x00000100);
638 exec->wait(exec, tMRD);
639 exec->mrs (exec, 0, info->mr[0] | 0x00000000);
640 exec->wait(exec, tMRD);
641 exec->wait(exec, tDLLK);
642 if (pfb->ram.type == NV_MEM_TYPE_GDDR3)
643 exec->precharge(exec);