drivers/gpu/drm/nouveau/nouveau_mem.c

   1 /*
   2  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3  * Copyright 2005 Stephane Marchesin
   4  *
   5  * The Weather Channel (TM) funded Tungsten Graphics to develop the
   6  * initial release of the Radeon 8500 driver under the XFree86 license.
   7  * This notice must be preserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26  * DEALINGS IN THE SOFTWARE.
  27  *
  28  * Authors:
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  */
  31
  32
  33 #include "drmP.h"
  34 #include "drm.h"
  35 #include "drm_sarea.h"
  36
  37 #include "nouveau_drv.h"
  38 #include "nouveau_pm.h"
  39 #include "nouveau_mm.h"
  40
  41 /*
  42  * NV10-NV40 tiling helpers
  43  */
  44
  45 static void
  46 nv10_mem_update_tile_region(struct drm_device *dev,
  47                             struct nouveau_tile_reg *tile, uint32_t addr,
  48                             uint32_t size, uint32_t pitch, uint32_t flags)
  49 {
  50         struct drm_nouveau_private *dev_priv = dev->dev_private;
  51         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
  52         struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
  53         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
  54         int i = tile - dev_priv->tile.reg;
  55         unsigned long save;
  56
  57         nouveau_fence_unref(&tile->fence);
  58
  59         if (tile->pitch)
  60                 pfb->free_tile_region(dev, i);
  61
  62         if (pitch)
  63                 pfb->init_tile_region(dev, i, addr, size, pitch, flags);
  64
  65         spin_lock_irqsave(&dev_priv->context_switch_lock, save);
  66         pfifo->reassign(dev, false);
  67         pfifo->cache_pull(dev, false);
  68
  69         nouveau_wait_for_idle(dev);
  70
  71         pfb->set_tile_region(dev, i);
  72         pgraph->set_tile_region(dev, i);
  73
  74         pfifo->cache_pull(dev, true);
  75         pfifo->reassign(dev, true);
  76         spin_unlock_irqrestore(&dev_priv->context_switch_lock, save);
  77 }
  78
  79 static struct nouveau_tile_reg *
  80 nv10_mem_get_tile_region(struct drm_device *dev, int i)
  81 {
  82         struct drm_nouveau_private *dev_priv = dev->dev_private;
  83         struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
  84
  85         spin_lock(&dev_priv->tile.lock);
  86
  87         if (!tile->used &&
  88             (!tile->fence || nouveau_fence_signalled(tile->fence)))
  89                 tile->used = true;
  90         else
  91                 tile = NULL;
  92
  93         spin_unlock(&dev_priv->tile.lock);
  94         return tile;
  95 }
  96
  97 void
  98 nv10_mem_put_tile_region(struct drm_device *dev, struct nouveau_tile_reg *tile,
  99                          struct nouveau_fence *fence)
 100 {
 101         struct drm_nouveau_private *dev_priv = dev->dev_private;
 102
 103         if (tile) {
 104                 spin_lock(&dev_priv->tile.lock);
 105                 if (fence) {
 106                         /* Mark it as pending. */
 107                         tile->fence = fence;
 108                         nouveau_fence_ref(fence);
 109                 }
 110
 111                 tile->used = false;
 112                 spin_unlock(&dev_priv->tile.lock);
 113         }
 114 }
 115
 116 struct nouveau_tile_reg *
 117 nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
 118                     uint32_t pitch, uint32_t flags)
 119 {
 120         struct drm_nouveau_private *dev_priv = dev->dev_private;
 121         struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
 122         struct nouveau_tile_reg *tile, *found = NULL;
 123         int i;
 124
 125         for (i = 0; i < pfb->num_tiles; i++) {
 126                 tile = nv10_mem_get_tile_region(dev, i);
 127
 128                 if (pitch && !found) {
 129                         found = tile;
 130                         continue;
 131
 132                 } else if (tile && tile->pitch) {
 133                         /* Kill an unused tile region. */
 134                         nv10_mem_update_tile_region(dev, tile, 0, 0, 0, 0);
 135                 }
 136
 137                 nv10_mem_put_tile_region(dev, tile, NULL);
 138         }
 139
 140         if (found)
 141                 nv10_mem_update_tile_region(dev, found, addr, size,
 142                                             pitch, flags);
 143         return found;
 144 }
 145
 146 /*
 147  * NV50 VM helpers
 148  */
 149 int
 150 nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
 151                         uint32_t flags, uint64_t phys)
 152 {
 153         struct drm_nouveau_private *dev_priv = dev->dev_private;
 154         struct nouveau_gpuobj *pgt;
 155         unsigned block;
 156         int i;
 157
 158         virt = ((virt - dev_priv->vm_vram_base) >> 16) << 1;
 159         size = (size >> 16) << 1;
 160
 161         phys |= ((uint64_t)flags << 32);
 162         phys |= 1;
 163         if (dev_priv->vram_sys_base) {
 164                 phys += dev_priv->vram_sys_base;
 165                 phys |= 0x30;
 166         }
 167
 168         while (size) {
 169                 unsigned offset_h = upper_32_bits(phys);
 170                 unsigned offset_l = lower_32_bits(phys);
 171                 unsigned pte, end;
 172
 173                 for (i = 7; i >= 0; i--) {
 174                         block = 1 << (i + 1);
 175                         if (size >= block && !(virt & (block - 1)))
 176                                 break;
 177                 }
 178                 offset_l |= (i << 7);
 179
 180                 phys += block << 15;
 181                 size -= block;
 182
 183                 while (block) {
 184                         pgt = dev_priv->vm_vram_pt[virt >> 14];
 185                         pte = virt & 0x3ffe;
 186
 187                         end = pte + block;
 188                         if (end > 16384)
 189                                 end = 16384;
 190                         block -= (end - pte);
 191                         virt  += (end - pte);
 192
 193                         while (pte < end) {
 194                                 nv_wo32(pgt, (pte * 4) + 0, offset_l);
 195                                 nv_wo32(pgt, (pte * 4) + 4, offset_h);
 196                                 pte += 2;
 197                         }
 198                 }
 199         }
 200
 201         dev_priv->engine.instmem.flush(dev);
 202         dev_priv->engine.fifo.tlb_flush(dev);
 203         dev_priv->engine.graph.tlb_flush(dev);
 204         nv50_vm_flush(dev, 6);
 205         return 0;
 206 }
 207
 208 void
 209 nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size)
 210 {
 211         struct drm_nouveau_private *dev_priv = dev->dev_private;
 212         struct nouveau_gpuobj *pgt;
 213         unsigned pages, pte, end;
 214
 215         virt -= dev_priv->vm_vram_base;
 216         pages = (size >> 16) << 1;
 217
 218         while (pages) {
 219                 pgt = dev_priv->vm_vram_pt[virt >> 29];
 220                 pte = (virt & 0x1ffe0000ULL) >> 15;
 221
 222                 end = pte + pages;
 223                 if (end > 16384)
 224                         end = 16384;
 225                 pages -= (end - pte);
 226                 virt  += (end - pte) << 15;
 227
 228                 while (pte < end) {
 229                         nv_wo32(pgt, (pte * 4), 0);
 230                         pte++;
 231                 }
 232         }
 233
 234         dev_priv->engine.instmem.flush(dev);
 235         dev_priv->engine.fifo.tlb_flush(dev);
 236         dev_priv->engine.graph.tlb_flush(dev);
 237         nv50_vm_flush(dev, 6);
 238 }
 239
 240 /*
 241  * Cleanup everything
 242  */
 243 void
 244 nouveau_mem_vram_fini(struct drm_device *dev)
 245 {
 246         struct drm_nouveau_private *dev_priv = dev->dev_private;
 247
 248         nouveau_bo_unpin(dev_priv->vga_ram);
 249         nouveau_bo_ref(NULL, &dev_priv->vga_ram);
 250
 251         ttm_bo_device_release(&dev_priv->ttm.bdev);
 252
 253         nouveau_ttm_global_release(dev_priv);
 254
 255         if (dev_priv->fb_mtrr >= 0) {
 256                 drm_mtrr_del(dev_priv->fb_mtrr,
 257                              pci_resource_start(dev->pdev, 1),
 258                              pci_resource_len(dev->pdev, 1), DRM_MTRR_WC);
 259                 dev_priv->fb_mtrr = -1;
 260         }
 261 }
 262
 263 void
 264 nouveau_mem_gart_fini(struct drm_device *dev)
 265 {
 266         nouveau_sgdma_takedown(dev);
 267
 268         if (drm_core_has_AGP(dev) && dev->agp) {
 269                 struct drm_agp_mem *entry, *tempe;
 270
 271                 /* Remove AGP resources, but leave dev->agp
 272                    intact until drv_cleanup is called. */
 273                 list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
 274                         if (entry->bound)
 275                                 drm_unbind_agp(entry->memory);
 276                         drm_free_agp(entry->memory, entry->pages);
 277                         kfree(entry);
 278                 }
 279                 INIT_LIST_HEAD(&dev->agp->memory);
 280
 281                 if (dev->agp->acquired)
 282                         drm_agp_release(dev);
 283
 284                 dev->agp->acquired = 0;
 285                 dev->agp->enabled = 0;
 286         }
 287 }
 288
 289 static uint32_t
 290 nouveau_mem_detect_nv04(struct drm_device *dev)
 291 {
 292         uint32_t boot0 = nv_rd32(dev, NV04_PFB_BOOT_0);
 293
 294         if (boot0 & 0x00000100)
 295                 return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;
 296
 297         switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
 298         case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
 299                 return 32 * 1024 * 1024;
 300         case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
 301                 return 16 * 1024 * 1024;
 302         case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
 303                 return 8 * 1024 * 1024;
 304         case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
 305                 return 4 * 1024 * 1024;
 306         }
 307
 308         return 0;
 309 }
 310
 311 static uint32_t
 312 nouveau_mem_detect_nforce(struct drm_device *dev)
 313 {
 314         struct drm_nouveau_private *dev_priv = dev->dev_private;
 315         struct pci_dev *bridge;
 316         uint32_t mem;
 317
 318         bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
 319         if (!bridge) {
 320                 NV_ERROR(dev, "no bridge device\n");
 321                 return 0;
 322         }
 323
 324         if (dev_priv->flags & NV_NFORCE) {
 325                 pci_read_config_dword(bridge, 0x7C, &mem);
 326                 return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024;
 327         } else
 328         if (dev_priv->flags & NV_NFORCE2) {
 329                 pci_read_config_dword(bridge, 0x84, &mem);
 330                 return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024;
 331         }
 332
 333         NV_ERROR(dev, "impossible!\n");
 334         return 0;
 335 }
 336
 337 static int
 338 nouveau_mem_detect(struct drm_device *dev)
 339 {
 340         struct drm_nouveau_private *dev_priv = dev->dev_private;
 341
 342         if (dev_priv->card_type == NV_04) {
 343                 dev_priv->vram_size = nouveau_mem_detect_nv04(dev);
 344         } else
 345         if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) {
 346                 dev_priv->vram_size = nouveau_mem_detect_nforce(dev);
 347         } else
 348         if (dev_priv->card_type < NV_50) {
 349                 dev_priv->vram_size  = nv_rd32(dev, NV04_PFB_FIFO_DATA);
 350                 dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
 351         } else
 352         if (dev_priv->card_type < NV_C0) {
 353                 if (nv50_vram_init(dev))
 354                         return -ENOMEM;
 355         } else {
 356                 dev_priv->vram_size  = nv_rd32(dev, 0x10f20c) << 20;
 357                 dev_priv->vram_size *= nv_rd32(dev, 0x121c74);
 358         }
 359
 360         NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
 361         if (dev_priv->vram_sys_base) {
 362                 NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
 363                         dev_priv->vram_sys_base);
 364         }
 365
 366         if (dev_priv->vram_size)
 367                 return 0;
 368         return -ENOMEM;
 369 }
 370
 371 #if __OS_HAS_AGP
 372 static unsigned long
 373 get_agp_mode(struct drm_device *dev, unsigned long mode)
 374 {
 375         struct drm_nouveau_private *dev_priv = dev->dev_private;
 376
 377         /*
 378          * FW seems to be broken on nv18, it makes the card lock up
 379          * randomly.
 380          */
 381         if (dev_priv->chipset == 0x18)
 382                 mode &= ~PCI_AGP_COMMAND_FW;
 383
 384         /*
 385          * AGP mode set in the command line.
 386          */
 387         if (nouveau_agpmode > 0) {
 388                 bool agpv3 = mode & 0x8;
 389                 int rate = agpv3 ? nouveau_agpmode / 4 : nouveau_agpmode;
 390
 391                 mode = (mode & ~0x7) | (rate & 0x7);
 392         }
 393
 394         return mode;
 395 }
 396 #endif
 397
 398 int
 399 nouveau_mem_reset_agp(struct drm_device *dev)
 400 {
 401 #if __OS_HAS_AGP
 402         uint32_t saved_pci_nv_1, pmc_enable;
 403         int ret;
 404
 405         /* First of all, disable fast writes, otherwise if it's
 406          * already enabled in the AGP bridge and we disable the card's
 407          * AGP controller we might be locking ourselves out of it. */
 408         if ((nv_rd32(dev, NV04_PBUS_PCI_NV_19) |
 409              dev->agp->mode) & PCI_AGP_COMMAND_FW) {
 410                 struct drm_agp_info info;
 411                 struct drm_agp_mode mode;
 412
 413                 ret = drm_agp_info(dev, &info);
 414                 if (ret)
 415                         return ret;
 416
 417                 mode.mode = get_agp_mode(dev, info.mode) & ~PCI_AGP_COMMAND_FW;
 418                 ret = drm_agp_enable(dev, mode);
 419                 if (ret)
 420                         return ret;
 421         }
 422
 423         saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);
 424
 425         /* clear busmaster bit */
 426         nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
 427         /* disable AGP */
 428         nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0);
 429
 430         /* power cycle pgraph, if enabled */
 431         pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
 432         if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
 433                 nv_wr32(dev, NV03_PMC_ENABLE,
 434                                 pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
 435                 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
 436                                 NV_PMC_ENABLE_PGRAPH);
 437         }
 438
 439         /* and restore (gives effect of resetting AGP) */
 440         nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
 441 #endif
 442
 443         return 0;
 444 }
 445
 446 int
 447 nouveau_mem_init_agp(struct drm_device *dev)
 448 {
 449 #if __OS_HAS_AGP
 450         struct drm_nouveau_private *dev_priv = dev->dev_private;
 451         struct drm_agp_info info;
 452         struct drm_agp_mode mode;
 453         int ret;
 454
 455         if (!dev->agp->acquired) {
 456                 ret = drm_agp_acquire(dev);
 457                 if (ret) {
 458                         NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
 459                         return ret;
 460                 }
 461         }
 462
 463         nouveau_mem_reset_agp(dev);
 464
 465         ret = drm_agp_info(dev, &info);
 466         if (ret) {
 467                 NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
 468                 return ret;
 469         }
 470
 471         /* see agp.h for the AGPSTAT_* modes available */
 472         mode.mode = get_agp_mode(dev, info.mode);
 473         ret = drm_agp_enable(dev, mode);
 474         if (ret) {
 475                 NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
 476                 return ret;
 477         }
 478
 479         dev_priv->gart_info.type        = NOUVEAU_GART_AGP;
 480         dev_priv->gart_info.aper_base   = info.aperture_base;
 481         dev_priv->gart_info.aper_size   = info.aperture_size;
 482 #endif
 483         return 0;
 484 }
 485
 486 int
 487 nouveau_mem_vram_init(struct drm_device *dev)
 488 {
 489         struct drm_nouveau_private *dev_priv = dev->dev_private;
 490         struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
 491         int ret, dma_bits;
 492
 493         if (dev_priv->card_type >= NV_50 &&
 494             pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
 495                 dma_bits = 40;
 496         else
 497                 dma_bits = 32;
 498
 499         ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
 500         if (ret)
 501                 return ret;
 502
 503         dev_priv->fb_phys = pci_resource_start(dev->pdev, 1);
 504
 505         ret = nouveau_ttm_global_init(dev_priv);
 506         if (ret)
 507                 return ret;
 508
 509         ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
 510                                  dev_priv->ttm.bo_global_ref.ref.object,
 511                                  &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
 512                                  dma_bits <= 32 ? true : false);
 513         if (ret) {
 514                 NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
 515                 return ret;
 516         }
 517
 518         /* reserve space at end of VRAM for PRAMIN */
 519         if (dev_priv->chipset == 0x40 || dev_priv->chipset == 0x47 ||
 520             dev_priv->chipset == 0x49 || dev_priv->chipset == 0x4b)
 521                 dev_priv->ramin_rsvd_vram = (2 * 1024 * 1024);
 522         else
 523         if (dev_priv->card_type >= NV_40)
 524                 dev_priv->ramin_rsvd_vram = (1 * 1024 * 1024);
 525         else
 526                 dev_priv->ramin_rsvd_vram = (512 * 1024);
 527
 528         /* initialise gpu-specific vram backend */
 529         ret = nouveau_mem_detect(dev);
 530         if (ret)
 531                 return ret;
 532
 533         dev_priv->fb_available_size = dev_priv->vram_size;
 534         dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
 535         if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1))
 536                 dev_priv->fb_mappable_pages = pci_resource_len(dev->pdev, 1);
 537         dev_priv->fb_mappable_pages >>= PAGE_SHIFT;
 538
 539         dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
 540         dev_priv->fb_aper_free = dev_priv->fb_available_size;
 541
 542         /* mappable vram */
 543         ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
 544                              dev_priv->fb_available_size >> PAGE_SHIFT);
 545         if (ret) {
 546                 NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
 547                 return ret;
 548         }
 549
 550         ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM,
 551                              0, 0, true, true, &dev_priv->vga_ram);
 552         if (ret == 0)
 553                 ret = nouveau_bo_pin(dev_priv->vga_ram, TTM_PL_FLAG_VRAM);
 554         if (ret) {
 555                 NV_WARN(dev, "failed to reserve VGA memory\n");
 556                 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
 557         }
 558
 559         dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1),
 560                                          pci_resource_len(dev->pdev, 1),
 561                                          DRM_MTRR_WC);
 562         return 0;
 563 }
 564
 565 int
 566 nouveau_mem_gart_init(struct drm_device *dev)
 567 {
 568         struct drm_nouveau_private *dev_priv = dev->dev_private;
 569         struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
 570         int ret;
 571
 572         dev_priv->gart_info.type = NOUVEAU_GART_NONE;
 573
 574 #if !defined(__powerpc__) && !defined(__ia64__)
 575         if (drm_device_is_agp(dev) && dev->agp && nouveau_agpmode) {
 576                 ret = nouveau_mem_init_agp(dev);
 577                 if (ret)
 578                         NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
 579         }
 580 #endif
 581
 582         if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
 583                 ret = nouveau_sgdma_init(dev);
 584                 if (ret) {
 585                         NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
 586                         return ret;
 587                 }
 588         }
 589
 590         NV_INFO(dev, "%d MiB GART (aperture)\n",
 591                 (int)(dev_priv->gart_info.aper_size >> 20));
 592         dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;
 593
 594         ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
 595                              dev_priv->gart_info.aper_size >> PAGE_SHIFT);
 596         if (ret) {
 597                 NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
 598                 return ret;
 599         }
 600
 601         return 0;
 602 }
 603
 604 void
 605 nouveau_mem_timing_init(struct drm_device *dev)
 606 {
 607         /* cards < NVC0 only */
 608         struct drm_nouveau_private *dev_priv = dev->dev_private;
 609         struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
 610         struct nouveau_pm_memtimings *memtimings = &pm->memtimings;
 611         struct nvbios *bios = &dev_priv->vbios;
 612         struct bit_entry P;
 613         u8 tUNK_0, tUNK_1, tUNK_2;
 614         u8 tRP;         /* Byte 3 */
 615         u8 tRAS;        /* Byte 5 */
 616         u8 tRFC;        /* Byte 7 */
 617         u8 tRC;         /* Byte 9 */
 618         u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14;
 619         u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21;
 620         u8 *mem = NULL, *entry;
 621         int i, recordlen, entries;
 622
 623         if (bios->type == NVBIOS_BIT) {
 624                 if (bit_table(dev, 'P', &P))
 625                         return;
 626
 627                 if (P.version == 1)
 628                         mem = ROMPTR(bios, P.data[4]);
 629                 else
 630                 if (P.version == 2)
 631                         mem = ROMPTR(bios, P.data[8]);
 632                 else {
 633                         NV_WARN(dev, "unknown mem for BIT P %d\n", P.version);
 634                 }
 635         } else {
 636                 NV_DEBUG(dev, "BMP version too old for memory\n");
 637                 return;
 638         }
 639
 640         if (!mem) {
 641                 NV_DEBUG(dev, "memory timing table pointer invalid\n");
 642                 return;
 643         }
 644
 645         if (mem[0] != 0x10) {
 646                 NV_WARN(dev, "memory timing table 0x%02x unknown\n", mem[0]);
 647                 return;
 648         }
 649
 650         /* validate record length */
 651         entries   = mem[2];
 652         recordlen = mem[3];
 653         if (recordlen < 15) {
 654                 NV_ERROR(dev, "mem timing table length unknown: %d\n", mem[3]);
 655                 return;
 656         }
 657
 658         /* parse vbios entries into common format */
 659         memtimings->timing =
 660                 kcalloc(entries, sizeof(*memtimings->timing), GFP_KERNEL);
 661         if (!memtimings->timing)
 662                 return;
 663
 664         entry = mem + mem[1];
 665         for (i = 0; i < entries; i++, entry += recordlen) {
 666                 struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i];
 667                 if (entry[0] == 0)
 668                         continue;
 669
 670                 tUNK_18 = 1;
 671                 tUNK_19 = 1;
 672                 tUNK_20 = 0;
 673                 tUNK_21 = 0;
 674                 switch (min(recordlen, 22)) {
 675                 case 22:
 676                         tUNK_21 = entry[21];
 677                 case 21:
 678                         tUNK_20 = entry[20];
 679                 case 20:
 680                         tUNK_19 = entry[19];
 681                 case 19:
 682                         tUNK_18 = entry[18];
 683                 default:
 684                         tUNK_0  = entry[0];
 685                         tUNK_1  = entry[1];
 686                         tUNK_2  = entry[2];
 687                         tRP     = entry[3];
 688                         tRAS    = entry[5];
 689                         tRFC    = entry[7];
 690                         tRC     = entry[9];
 691                         tUNK_10 = entry[10];
 692                         tUNK_11 = entry[11];
 693                         tUNK_12 = entry[12];
 694                         tUNK_13 = entry[13];
 695                         tUNK_14 = entry[14];
 696                         break;
 697                 }
 698
 699                 timing->reg_100220 = (tRC << 24 | tRFC << 16 | tRAS << 8 | tRP);
 700
 701                 /* XXX: I don't trust the -1's and +1's... they must come
 702                  *      from somewhere! */
 703                 timing->reg_100224 = ((tUNK_0 + tUNK_19 + 1) << 24 |
 704                                       tUNK_18 << 16 |
 705                                       (tUNK_1 + tUNK_19 + 1) << 8 |
 706                                       (tUNK_2 - 1));
 707
 708                 timing->reg_100228 = (tUNK_12 << 16 | tUNK_11 << 8 | tUNK_10);
 709                 if(recordlen > 19) {
 710                         timing->reg_100228 += (tUNK_19 - 1) << 24;
 711                 }/* I cannot back-up this else-statement right now
 712                          else {
 713                         timing->reg_100228 += tUNK_12 << 24;
 714                 }*/
 715
 716                 /* XXX: reg_10022c */
 717                 timing->reg_10022c = tUNK_2 - 1;
 718
 719                 timing->reg_100230 = (tUNK_20 << 24 | tUNK_21 << 16 |
 720                                       tUNK_13 << 8  | tUNK_13);
 721
 722                 /* XXX: +6? */
 723                 timing->reg_100234 = (tRAS << 24 | (tUNK_19 + 6) << 8 | tRC);
 724                 timing->reg_100234 += max(tUNK_10,tUNK_11) << 16;
 725
 726                 /* XXX; reg_100238, reg_10023c
 727                  * reg: 0x00??????
 728                  * reg_10023c:
 729                  *      0 for pre-NV50 cards
 730                  *      0x????0202 for NV50+ cards (empirical evidence) */
 731                 if(dev_priv->card_type >= NV_50) {
 732                         timing->reg_10023c = 0x202;
 733                 }
 734
 735                 NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", i,
 736                          timing->reg_100220, timing->reg_100224,
 737                          timing->reg_100228, timing->reg_10022c);
 738                 NV_DEBUG(dev, "         230: %08x %08x %08x %08x\n",
 739                          timing->reg_100230, timing->reg_100234,
 740                          timing->reg_100238, timing->reg_10023c);
 741         }
 742
 743         memtimings->nr_timing  = entries;
 744         memtimings->supported = true;
 745 }
 746
 747 void
 748 nouveau_mem_timing_fini(struct drm_device *dev)
 749 {
 750         struct drm_nouveau_private *dev_priv = dev->dev_private;
 751         struct nouveau_pm_memtimings *mem = &dev_priv->engine.pm.memtimings;
 752
 753         kfree(mem->timing);
 754 }
 755
 756 static int
 757 nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long p_size)
 758 {
 759         struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
 760         struct nouveau_mm *mm;
 761         u32 b_size;
 762         int ret;
 763
 764         p_size = (p_size << PAGE_SHIFT) >> 12;
 765         b_size = dev_priv->vram_rblock_size >> 12;
 766
 767         ret = nouveau_mm_init(&mm, 0, p_size, b_size);
 768         if (ret)
 769                 return ret;
 770
 771         man->priv = mm;
 772         return 0;
 773 }
 774
 775 static int
 776 nouveau_vram_manager_fini(struct ttm_mem_type_manager *man)
 777 {
 778         struct nouveau_mm *mm = man->priv;
 779         int ret;
 780
 781         ret = nouveau_mm_fini(&mm);
 782         if (ret)
 783                 return ret;
 784
 785         man->priv = NULL;
 786         return 0;
 787 }
 788
 789 static void
 790 nouveau_vram_manager_del(struct ttm_mem_type_manager *man,
 791                          struct ttm_mem_reg *mem)
 792 {
 793         struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
 794         struct drm_device *dev = dev_priv->dev;
 795
 796         nv50_vram_del(dev, (struct nouveau_vram **)&mem->mm_node);
 797 }
 798
 799 static int
 800 nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
 801                          struct ttm_buffer_object *bo,
 802                          struct ttm_placement *placement,
 803                          struct ttm_mem_reg *mem)
 804 {
 805         struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
 806         struct drm_device *dev = dev_priv->dev;
 807         struct nouveau_bo *nvbo = nouveau_bo(bo);
 808         struct nouveau_vram *vram;
 809         int ret;
 810
 811         ret = nv50_vram_new(dev, mem->num_pages << PAGE_SHIFT, 65536, 0,
 812                             (nvbo->tile_flags >> 8) & 0x7f, &vram);
 813         if (ret)
 814                 return ret;
 815
 816         mem->mm_node = vram;
 817         mem->start   = vram->offset >> PAGE_SHIFT;
 818         return 0;
 819 }
 820
 821 void
 822 nouveau_vram_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
 823 {
 824         struct ttm_bo_global *glob = man->bdev->glob;
 825         struct nouveau_mm *mm = man->priv;
 826         struct nouveau_mm_node *r;
 827         u64 total = 0, ttotal[3] = {}, tused[3] = {}, tfree[3] = {};
 828         int i;
 829
 830         mutex_lock(&mm->mutex);
 831         list_for_each_entry(r, &mm->nodes, nl_entry) {
 832                 printk(KERN_DEBUG "%s %s-%d: 0x%010llx 0x%010llx\n",
 833                        prefix, r->free ? "free" : "used", r->type,
 834                        ((u64)r->offset << 12),
 835                        (((u64)r->offset + r->length) << 12));
 836                 total += r->length;
 837                 ttotal[r->type] += r->length;
 838                 if (r->free)
 839                         tfree[r->type] += r->length;
 840                 else
 841                         tused[r->type] += r->length;
 842         }
 843         mutex_unlock(&mm->mutex);
 844
 845         printk(KERN_DEBUG "%s  total: 0x%010llx\n", prefix, total << 12);
 846         for (i = 0; i < 3; i++) {
 847                 printk(KERN_DEBUG "%s type %d: 0x%010llx, "
 848                                   "used 0x%010llx, free 0x%010llx\n", prefix,
 849                        i, ttotal[i] << 12, tused[i] << 12, tfree[i] << 12);
 850         }
 851 }
 852
 853 const struct ttm_mem_type_manager_func nouveau_vram_manager = {
 854         nouveau_vram_manager_init,
 855         nouveau_vram_manager_fini,
 856         nouveau_vram_manager_new,
 857         nouveau_vram_manager_del,
 858         nouveau_vram_manager_debug
 859 };