2 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3 * Copyright 2005 Stephane Marchesin
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
29 * Keith Whitwell <keith@tungstengraphics.com>
35 #include "drm_sarea.h"
37 #include "nouveau_drv.h"
38 #include "nouveau_pm.h"
41 * NV10-NV40 tiling helpers
45 nv10_mem_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
46 uint32_t size, uint32_t pitch)
48 struct drm_nouveau_private *dev_priv = dev->dev_private;
49 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
50 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
51 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
52 struct nouveau_tile_reg *tile = &dev_priv->tile[i];
57 nouveau_fence_unref((void **)&tile->fence);
59 pfifo->reassign(dev, false);
60 pfifo->cache_pull(dev, false);
62 nouveau_wait_for_idle(dev);
64 pgraph->set_region_tiling(dev, i, addr, size, pitch);
65 pfb->set_region_tiling(dev, i, addr, size, pitch);
67 pfifo->cache_pull(dev, true);
68 pfifo->reassign(dev, true);
71 struct nouveau_tile_reg *
72 nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
75 struct drm_nouveau_private *dev_priv = dev->dev_private;
76 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
77 struct nouveau_tile_reg *found = NULL;
78 unsigned long i, flags;
80 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
82 for (i = 0; i < pfb->num_tiles; i++) {
83 struct nouveau_tile_reg *tile = &dev_priv->tile[i];
86 /* Tile region in use. */
90 !nouveau_fence_signalled(tile->fence, NULL))
91 /* Pending tile region. */
94 if (max(tile->addr, addr) <
95 min(tile->addr + tile->size, addr + size))
96 /* Kill an intersecting tile region. */
97 nv10_mem_set_region_tiling(dev, i, 0, 0, 0);
99 if (pitch && !found) {
100 /* Free tile region. */
101 nv10_mem_set_region_tiling(dev, i, addr, size, pitch);
106 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
112 nv10_mem_expire_tiling(struct drm_device *dev, struct nouveau_tile_reg *tile,
113 struct nouveau_fence *fence)
116 /* Mark it as pending. */
118 nouveau_fence_ref(fence);
128 nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
129 uint32_t flags, uint64_t phys)
131 struct drm_nouveau_private *dev_priv = dev->dev_private;
132 struct nouveau_gpuobj *pgt;
136 virt = ((virt - dev_priv->vm_vram_base) >> 16) << 1;
137 size = (size >> 16) << 1;
139 phys |= ((uint64_t)flags << 32);
141 if (dev_priv->vram_sys_base) {
142 phys += dev_priv->vram_sys_base;
147 unsigned offset_h = upper_32_bits(phys);
148 unsigned offset_l = lower_32_bits(phys);
151 for (i = 7; i >= 0; i--) {
152 block = 1 << (i + 1);
153 if (size >= block && !(virt & (block - 1)))
156 offset_l |= (i << 7);
162 pgt = dev_priv->vm_vram_pt[virt >> 14];
168 block -= (end - pte);
172 nv_wo32(pgt, (pte * 4) + 0, offset_l);
173 nv_wo32(pgt, (pte * 4) + 4, offset_h);
179 dev_priv->engine.instmem.flush(dev);
180 dev_priv->engine.fifo.tlb_flush(dev);
181 dev_priv->engine.graph.tlb_flush(dev);
182 nv50_vm_flush(dev, 6);
187 nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size)
189 struct drm_nouveau_private *dev_priv = dev->dev_private;
190 struct nouveau_gpuobj *pgt;
191 unsigned pages, pte, end;
193 virt -= dev_priv->vm_vram_base;
194 pages = (size >> 16) << 1;
197 pgt = dev_priv->vm_vram_pt[virt >> 29];
198 pte = (virt & 0x1ffe0000ULL) >> 15;
203 pages -= (end - pte);
204 virt += (end - pte) << 15;
207 nv_wo32(pgt, (pte * 4), 0);
212 dev_priv->engine.instmem.flush(dev);
213 dev_priv->engine.fifo.tlb_flush(dev);
214 dev_priv->engine.graph.tlb_flush(dev);
215 nv50_vm_flush(dev, 6);
222 nouveau_mem_vram_fini(struct drm_device *dev)
224 struct drm_nouveau_private *dev_priv = dev->dev_private;
226 nouveau_bo_unpin(dev_priv->vga_ram);
227 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
229 ttm_bo_device_release(&dev_priv->ttm.bdev);
231 nouveau_ttm_global_release(dev_priv);
233 if (dev_priv->fb_mtrr >= 0) {
234 drm_mtrr_del(dev_priv->fb_mtrr,
235 pci_resource_start(dev->pdev, 1),
236 pci_resource_len(dev->pdev, 1), DRM_MTRR_WC);
237 dev_priv->fb_mtrr = -1;
242 nouveau_mem_gart_fini(struct drm_device *dev)
244 nouveau_sgdma_takedown(dev);
246 if (drm_core_has_AGP(dev) && dev->agp) {
247 struct drm_agp_mem *entry, *tempe;
249 /* Remove AGP resources, but leave dev->agp
250 intact until drv_cleanup is called. */
251 list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
253 drm_unbind_agp(entry->memory);
254 drm_free_agp(entry->memory, entry->pages);
257 INIT_LIST_HEAD(&dev->agp->memory);
259 if (dev->agp->acquired)
260 drm_agp_release(dev);
262 dev->agp->acquired = 0;
263 dev->agp->enabled = 0;
268 nouveau_mem_detect_nv04(struct drm_device *dev)
270 uint32_t boot0 = nv_rd32(dev, NV04_PFB_BOOT_0);
272 if (boot0 & 0x00000100)
273 return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;
275 switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
276 case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
277 return 32 * 1024 * 1024;
278 case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
279 return 16 * 1024 * 1024;
280 case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
281 return 8 * 1024 * 1024;
282 case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
283 return 4 * 1024 * 1024;
290 nouveau_mem_detect_nforce(struct drm_device *dev)
292 struct drm_nouveau_private *dev_priv = dev->dev_private;
293 struct pci_dev *bridge;
296 bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
298 NV_ERROR(dev, "no bridge device\n");
302 if (dev_priv->flags & NV_NFORCE) {
303 pci_read_config_dword(bridge, 0x7C, &mem);
304 return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024;
306 if (dev_priv->flags & NV_NFORCE2) {
307 pci_read_config_dword(bridge, 0x84, &mem);
308 return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024;
311 NV_ERROR(dev, "impossible!\n");
316 nv50_vram_preinit(struct drm_device *dev)
318 struct drm_nouveau_private *dev_priv = dev->dev_private;
319 int i, parts, colbits, rowbitsa, rowbitsb, banks;
320 u64 rowsize, predicted;
323 r0 = nv_rd32(dev, 0x100200);
324 r4 = nv_rd32(dev, 0x100204);
325 rt = nv_rd32(dev, 0x100250);
326 ru = nv_rd32(dev, 0x001540);
327 NV_DEBUG(dev, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt, ru);
329 for (i = 0, parts = 0; i < 8; i++) {
330 if (ru & (0x00010000 << i))
334 colbits = (r4 & 0x0000f000) >> 12;
335 rowbitsa = ((r4 & 0x000f0000) >> 16) + 8;
336 rowbitsb = ((r4 & 0x00f00000) >> 20) + 8;
337 banks = ((r4 & 0x01000000) ? 8 : 4);
339 rowsize = parts * banks * (1 << colbits) * 8;
340 predicted = rowsize << rowbitsa;
342 predicted += rowsize << rowbitsb;
344 if (predicted != dev_priv->vram_size) {
345 NV_WARN(dev, "memory controller reports %dMiB VRAM\n",
346 (u32)(dev_priv->vram_size >> 20));
347 NV_WARN(dev, "we calculated %dMiB VRAM\n",
348 (u32)(predicted >> 20));
351 dev_priv->vram_rblock_size = rowsize >> 12;
353 dev_priv->vram_rblock_size *= 3;
355 NV_DEBUG(dev, "rblock %lld bytes\n",
356 (u64)dev_priv->vram_rblock_size << 12);
360 nvaa_vram_preinit(struct drm_device *dev)
362 struct drm_nouveau_private *dev_priv = dev->dev_private;
364 /* To our knowledge, there's no large scale reordering of pages
365 * that occurs on IGP chipsets.
367 dev_priv->vram_rblock_size = 1;
371 nouveau_mem_detect(struct drm_device *dev)
373 struct drm_nouveau_private *dev_priv = dev->dev_private;
375 if (dev_priv->card_type == NV_04) {
376 dev_priv->vram_size = nouveau_mem_detect_nv04(dev);
378 if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) {
379 dev_priv->vram_size = nouveau_mem_detect_nforce(dev);
381 if (dev_priv->card_type < NV_50) {
382 dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA);
383 dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
385 if (dev_priv->card_type < NV_C0) {
386 dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA);
387 dev_priv->vram_size |= (dev_priv->vram_size & 0xff) << 32;
388 dev_priv->vram_size &= 0xffffffff00ll;
390 switch (dev_priv->chipset) {
394 dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10);
395 dev_priv->vram_sys_base <<= 12;
396 nvaa_vram_preinit(dev);
399 nv50_vram_preinit(dev);
403 dev_priv->vram_size = nv_rd32(dev, 0x10f20c) << 20;
404 dev_priv->vram_size *= nv_rd32(dev, 0x121c74);
407 NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
408 if (dev_priv->vram_sys_base) {
409 NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
410 dev_priv->vram_sys_base);
413 if (dev_priv->vram_size)
420 get_agp_mode(struct drm_device *dev, unsigned long mode)
422 struct drm_nouveau_private *dev_priv = dev->dev_private;
425 * FW seems to be broken on nv18, it makes the card lock up
428 if (dev_priv->chipset == 0x18)
429 mode &= ~PCI_AGP_COMMAND_FW;
432 * AGP mode set in the command line.
434 if (nouveau_agpmode > 0) {
435 bool agpv3 = mode & 0x8;
436 int rate = agpv3 ? nouveau_agpmode / 4 : nouveau_agpmode;
438 mode = (mode & ~0x7) | (rate & 0x7);
446 nouveau_mem_reset_agp(struct drm_device *dev)
449 uint32_t saved_pci_nv_1, pmc_enable;
452 /* First of all, disable fast writes, otherwise if it's
453 * already enabled in the AGP bridge and we disable the card's
454 * AGP controller we might be locking ourselves out of it. */
455 if ((nv_rd32(dev, NV04_PBUS_PCI_NV_19) |
456 dev->agp->mode) & PCI_AGP_COMMAND_FW) {
457 struct drm_agp_info info;
458 struct drm_agp_mode mode;
460 ret = drm_agp_info(dev, &info);
464 mode.mode = get_agp_mode(dev, info.mode) & ~PCI_AGP_COMMAND_FW;
465 ret = drm_agp_enable(dev, mode);
470 saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);
472 /* clear busmaster bit */
473 nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
475 nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0);
477 /* power cycle pgraph, if enabled */
478 pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
479 if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
480 nv_wr32(dev, NV03_PMC_ENABLE,
481 pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
482 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
483 NV_PMC_ENABLE_PGRAPH);
486 /* and restore (gives effect of resetting AGP) */
487 nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
494 nouveau_mem_init_agp(struct drm_device *dev)
497 struct drm_nouveau_private *dev_priv = dev->dev_private;
498 struct drm_agp_info info;
499 struct drm_agp_mode mode;
502 if (!dev->agp->acquired) {
503 ret = drm_agp_acquire(dev);
505 NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
510 nouveau_mem_reset_agp(dev);
512 ret = drm_agp_info(dev, &info);
514 NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
518 /* see agp.h for the AGPSTAT_* modes available */
519 mode.mode = get_agp_mode(dev, info.mode);
520 ret = drm_agp_enable(dev, mode);
522 NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
526 dev_priv->gart_info.type = NOUVEAU_GART_AGP;
527 dev_priv->gart_info.aper_base = info.aperture_base;
528 dev_priv->gart_info.aper_size = info.aperture_size;
534 nouveau_mem_vram_init(struct drm_device *dev)
536 struct drm_nouveau_private *dev_priv = dev->dev_private;
537 struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
540 if (dev_priv->card_type >= NV_50 &&
541 pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
546 ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
550 ret = nouveau_mem_detect(dev);
554 dev_priv->fb_phys = pci_resource_start(dev->pdev, 1);
556 ret = nouveau_ttm_global_init(dev_priv);
560 ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
561 dev_priv->ttm.bo_global_ref.ref.object,
562 &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
563 dma_bits <= 32 ? true : false);
565 NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
569 dev_priv->fb_available_size = dev_priv->vram_size;
570 dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
571 if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1))
572 dev_priv->fb_mappable_pages =
573 pci_resource_len(dev->pdev, 1);
574 dev_priv->fb_mappable_pages >>= PAGE_SHIFT;
576 /* reserve space at end of VRAM for PRAMIN */
577 if (dev_priv->chipset == 0x40 || dev_priv->chipset == 0x47 ||
578 dev_priv->chipset == 0x49 || dev_priv->chipset == 0x4b)
579 dev_priv->ramin_rsvd_vram = (2 * 1024 * 1024);
581 if (dev_priv->card_type >= NV_40)
582 dev_priv->ramin_rsvd_vram = (1 * 1024 * 1024);
584 dev_priv->ramin_rsvd_vram = (512 * 1024);
586 dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
587 dev_priv->fb_aper_free = dev_priv->fb_available_size;
590 ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
591 dev_priv->fb_available_size >> PAGE_SHIFT);
593 NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
597 ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM,
598 0, 0, true, true, &dev_priv->vga_ram);
600 ret = nouveau_bo_pin(dev_priv->vga_ram, TTM_PL_FLAG_VRAM);
602 NV_WARN(dev, "failed to reserve VGA memory\n");
603 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
606 dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1),
607 pci_resource_len(dev->pdev, 1),
613 nouveau_mem_gart_init(struct drm_device *dev)
615 struct drm_nouveau_private *dev_priv = dev->dev_private;
616 struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
619 dev_priv->gart_info.type = NOUVEAU_GART_NONE;
621 #if !defined(__powerpc__) && !defined(__ia64__)
622 if (drm_device_is_agp(dev) && dev->agp && nouveau_agpmode) {
623 ret = nouveau_mem_init_agp(dev);
625 NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
629 if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
630 ret = nouveau_sgdma_init(dev);
632 NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
637 NV_INFO(dev, "%d MiB GART (aperture)\n",
638 (int)(dev_priv->gart_info.aper_size >> 20));
639 dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;
641 ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
642 dev_priv->gart_info.aper_size >> PAGE_SHIFT);
644 NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
652 nouveau_mem_timing_init(struct drm_device *dev)
654 /* cards < NVC0 only */
655 struct drm_nouveau_private *dev_priv = dev->dev_private;
656 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
657 struct nouveau_pm_memtimings *memtimings = &pm->memtimings;
658 struct nvbios *bios = &dev_priv->vbios;
660 u8 tUNK_0, tUNK_1, tUNK_2;
662 u8 tRAS; /* Byte 5 */
663 u8 tRFC; /* Byte 7 */
665 u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14;
666 u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21;
667 u8 *mem = NULL, *entry;
668 int i, recordlen, entries;
670 if (bios->type == NVBIOS_BIT) {
671 if (bit_table(dev, 'P', &P))
675 mem = ROMPTR(bios, P.data[4]);
678 mem = ROMPTR(bios, P.data[8]);
680 NV_WARN(dev, "unknown mem for BIT P %d\n", P.version);
683 NV_DEBUG(dev, "BMP version too old for memory\n");
688 NV_DEBUG(dev, "memory timing table pointer invalid\n");
692 if (mem[0] != 0x10) {
693 NV_WARN(dev, "memory timing table 0x%02x unknown\n", mem[0]);
697 /* validate record length */
700 if (recordlen < 15) {
701 NV_ERROR(dev, "mem timing table length unknown: %d\n", mem[3]);
705 /* parse vbios entries into common format */
707 kcalloc(entries, sizeof(*memtimings->timing), GFP_KERNEL);
708 if (!memtimings->timing)
711 entry = mem + mem[1];
712 for (i = 0; i < entries; i++, entry += recordlen) {
713 struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i];
721 switch (min(recordlen, 22)) {
746 timing->reg_100220 = (tRC << 24 | tRFC << 16 | tRAS << 8 | tRP);
748 /* XXX: I don't trust the -1's and +1's... they must come
750 timing->reg_100224 = ((tUNK_0 + tUNK_19 + 1) << 24 |
752 (tUNK_1 + tUNK_19 + 1) << 8 |
755 timing->reg_100228 = (tUNK_12 << 16 | tUNK_11 << 8 | tUNK_10);
757 timing->reg_100228 += (tUNK_19 - 1) << 24;
758 }/* I cannot back-up this else-statement right now
760 timing->reg_100228 += tUNK_12 << 24;
763 /* XXX: reg_10022c */
764 timing->reg_10022c = tUNK_2 - 1;
766 timing->reg_100230 = (tUNK_20 << 24 | tUNK_21 << 16 |
767 tUNK_13 << 8 | tUNK_13);
770 timing->reg_100234 = (tRAS << 24 | (tUNK_19 + 6) << 8 | tRC);
771 timing->reg_100234 += max(tUNK_10,tUNK_11) << 16;
773 /* XXX; reg_100238, reg_10023c
776 * 0 for pre-NV50 cards
777 * 0x????0202 for NV50+ cards (empirical evidence) */
778 if(dev_priv->card_type >= NV_50) {
779 timing->reg_10023c = 0x202;
782 NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", i,
783 timing->reg_100220, timing->reg_100224,
784 timing->reg_100228, timing->reg_10022c);
785 NV_DEBUG(dev, " 230: %08x %08x %08x %08x\n",
786 timing->reg_100230, timing->reg_100234,
787 timing->reg_100238, timing->reg_10023c);
790 memtimings->nr_timing = entries;
791 memtimings->supported = true;
795 nouveau_mem_timing_fini(struct drm_device *dev)
797 struct drm_nouveau_private *dev_priv = dev->dev_private;
798 struct nouveau_pm_memtimings *mem = &dev_priv->engine.pm.memtimings;