drivers/gpu/drm/nouveau/nouveau_mem.c

   1 /*
   2  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3  * Copyright 2005 Stephane Marchesin
   4  *
   5  * The Weather Channel (TM) funded Tungsten Graphics to develop the
   6  * initial release of the Radeon 8500 driver under the XFree86 license.
   7  * This notice must be preserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26  * DEALINGS IN THE SOFTWARE.
  27  *
  28  * Authors:
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  */
  31
  32
  33 #include "drmP.h"
  34 #include "drm.h"
  35 #include "drm_sarea.h"
  36 #include "nouveau_drv.h"
  37
  38 /*
  39  * NV10-NV40 tiling helpers
  40  */
  41
  42 static void
  43 nv10_mem_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
  44                            uint32_t size, uint32_t pitch)
  45 {
  46         struct drm_nouveau_private *dev_priv = dev->dev_private;
  47         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
  48         struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
  49         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
  50         struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
  51
  52         tile->addr = addr;
  53         tile->size = size;
  54         tile->used = !!pitch;
  55         nouveau_fence_unref((void **)&tile->fence);
  56
  57         if (!pfifo->cache_flush(dev))
  58                 return;
  59
  60         pfifo->reassign(dev, false);
  61         pfifo->cache_flush(dev);
  62         pfifo->cache_pull(dev, false);
  63
  64         nouveau_wait_for_idle(dev);
  65
  66         pgraph->set_region_tiling(dev, i, addr, size, pitch);
  67         pfb->set_region_tiling(dev, i, addr, size, pitch);
  68
  69         pfifo->cache_pull(dev, true);
  70         pfifo->reassign(dev, true);
  71 }
  72
  73 struct nouveau_tile_reg *
  74 nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
  75                     uint32_t pitch)
  76 {
  77         struct drm_nouveau_private *dev_priv = dev->dev_private;
  78         struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
  79         struct nouveau_tile_reg *tile = dev_priv->tile.reg, *found = NULL;
  80         int i;
  81
  82         spin_lock(&dev_priv->tile.lock);
  83
  84         for (i = 0; i < pfb->num_tiles; i++) {
  85                 if (tile[i].used)
  86                         /* Tile region in use. */
  87                         continue;
  88
  89                 if (tile[i].fence &&
  90                     !nouveau_fence_signalled(tile[i].fence, NULL))
  91                         /* Pending tile region. */
  92                         continue;
  93
  94                 if (max(tile[i].addr, addr) <
  95                     min(tile[i].addr + tile[i].size, addr + size))
  96                         /* Kill an intersecting tile region. */
  97                         nv10_mem_set_region_tiling(dev, i, 0, 0, 0);
  98
  99                 if (pitch && !found) {
 100                         /* Free tile region. */
 101                         nv10_mem_set_region_tiling(dev, i, addr, size, pitch);
 102                         found = &tile[i];
 103                 }
 104         }
 105
 106         spin_unlock(&dev_priv->tile.lock);
 107
 108         return found;
 109 }
 110
 111 void
 112 nv10_mem_expire_tiling(struct drm_device *dev, struct nouveau_tile_reg *tile,
 113                        struct nouveau_fence *fence)
 114 {
 115         if (fence) {
 116                 /* Mark it as pending. */
 117                 tile->fence = fence;
 118                 nouveau_fence_ref(fence);
 119         }
 120
 121         tile->used = false;
 122 }
 123
 124 /*
 125  * NV50 VM helpers
 126  */
 127 int
 128 nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
 129                         uint32_t flags, uint64_t phys)
 130 {
 131         struct drm_nouveau_private *dev_priv = dev->dev_private;
 132         struct nouveau_gpuobj *pgt;
 133         unsigned block;
 134         int i;
 135
 136         virt = ((virt - dev_priv->vm_vram_base) >> 16) << 1;
 137         size = (size >> 16) << 1;
 138
 139         phys |= ((uint64_t)flags << 32);
 140         phys |= 1;
 141         if (dev_priv->vram_sys_base) {
 142                 phys += dev_priv->vram_sys_base;
 143                 phys |= 0x30;
 144         }
 145
 146         while (size) {
 147                 unsigned offset_h = upper_32_bits(phys);
 148                 unsigned offset_l = lower_32_bits(phys);
 149                 unsigned pte, end;
 150
 151                 for (i = 7; i >= 0; i--) {
 152                         block = 1 << (i + 1);
 153                         if (size >= block && !(virt & (block - 1)))
 154                                 break;
 155                 }
 156                 offset_l |= (i << 7);
 157
 158                 phys += block << 15;
 159                 size -= block;
 160
 161                 while (block) {
 162                         pgt = dev_priv->vm_vram_pt[virt >> 14];
 163                         pte = virt & 0x3ffe;
 164
 165                         end = pte + block;
 166                         if (end > 16384)
 167                                 end = 16384;
 168                         block -= (end - pte);
 169                         virt  += (end - pte);
 170
 171                         while (pte < end) {
 172                                 nv_wo32(pgt, (pte * 4) + 0, offset_l);
 173                                 nv_wo32(pgt, (pte * 4) + 4, offset_h);
 174                                 pte += 2;
 175                         }
 176                 }
 177         }
 178         dev_priv->engine.instmem.flush(dev);
 179
 180         nv50_vm_flush(dev, 5);
 181         nv50_vm_flush(dev, 0);
 182         nv50_vm_flush(dev, 4);
 183         nv50_vm_flush(dev, 6);
 184         return 0;
 185 }
 186
 187 void
 188 nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size)
 189 {
 190         struct drm_nouveau_private *dev_priv = dev->dev_private;
 191         struct nouveau_gpuobj *pgt;
 192         unsigned pages, pte, end;
 193
 194         virt -= dev_priv->vm_vram_base;
 195         pages = (size >> 16) << 1;
 196
 197         while (pages) {
 198                 pgt = dev_priv->vm_vram_pt[virt >> 29];
 199                 pte = (virt & 0x1ffe0000ULL) >> 15;
 200
 201                 end = pte + pages;
 202                 if (end > 16384)
 203                         end = 16384;
 204                 pages -= (end - pte);
 205                 virt  += (end - pte) << 15;
 206
 207                 while (pte < end) {
 208                         nv_wo32(pgt, (pte * 4), 0);
 209                         pte++;
 210                 }
 211         }
 212         dev_priv->engine.instmem.flush(dev);
 213
 214         nv50_vm_flush(dev, 5);
 215         nv50_vm_flush(dev, 0);
 216         nv50_vm_flush(dev, 4);
 217         nv50_vm_flush(dev, 6);
 218 }
 219
 220 /*
 221  * Cleanup everything
 222  */
 223 void
 224 nouveau_mem_close(struct drm_device *dev)
 225 {
 226         struct drm_nouveau_private *dev_priv = dev->dev_private;
 227
 228         nouveau_bo_unpin(dev_priv->vga_ram);
 229         nouveau_bo_ref(NULL, &dev_priv->vga_ram);
 230
 231         ttm_bo_device_release(&dev_priv->ttm.bdev);
 232
 233         nouveau_ttm_global_release(dev_priv);
 234
 235         if (drm_core_has_AGP(dev) && dev->agp) {
 236                 struct drm_agp_mem *entry, *tempe;
 237
 238                 /* Remove AGP resources, but leave dev->agp
 239                    intact until drv_cleanup is called. */
 240                 list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
 241                         if (entry->bound)
 242                                 drm_unbind_agp(entry->memory);
 243                         drm_free_agp(entry->memory, entry->pages);
 244                         kfree(entry);
 245                 }
 246                 INIT_LIST_HEAD(&dev->agp->memory);
 247
 248                 if (dev->agp->acquired)
 249                         drm_agp_release(dev);
 250
 251                 dev->agp->acquired = 0;
 252                 dev->agp->enabled = 0;
 253         }
 254
 255         if (dev_priv->fb_mtrr) {
 256                 drm_mtrr_del(dev_priv->fb_mtrr,
 257                              pci_resource_start(dev->pdev, 1),
 258                              pci_resource_len(dev->pdev, 1), DRM_MTRR_WC);
 259                 dev_priv->fb_mtrr = -1;
 260         }
 261 }
 262
 263 static uint32_t
 264 nouveau_mem_detect_nv04(struct drm_device *dev)
 265 {
 266         uint32_t boot0 = nv_rd32(dev, NV04_PFB_BOOT_0);
 267
 268         if (boot0 & 0x00000100)
 269                 return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;
 270
 271         switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
 272         case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
 273                 return 32 * 1024 * 1024;
 274         case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
 275                 return 16 * 1024 * 1024;
 276         case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
 277                 return 8 * 1024 * 1024;
 278         case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
 279                 return 4 * 1024 * 1024;
 280         }
 281
 282         return 0;
 283 }
 284
 285 static uint32_t
 286 nouveau_mem_detect_nforce(struct drm_device *dev)
 287 {
 288         struct drm_nouveau_private *dev_priv = dev->dev_private;
 289         struct pci_dev *bridge;
 290         uint32_t mem;
 291
 292         bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
 293         if (!bridge) {
 294                 NV_ERROR(dev, "no bridge device\n");
 295                 return 0;
 296         }
 297
 298         if (dev_priv->flags & NV_NFORCE) {
 299                 pci_read_config_dword(bridge, 0x7C, &mem);
 300                 return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024;
 301         } else
 302         if (dev_priv->flags & NV_NFORCE2) {
 303                 pci_read_config_dword(bridge, 0x84, &mem);
 304                 return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024;
 305         }
 306
 307         NV_ERROR(dev, "impossible!\n");
 308         return 0;
 309 }
 310
 311 /* returns the amount of FB ram in bytes */
 312 int
 313 nouveau_mem_detect(struct drm_device *dev)
 314 {
 315         struct drm_nouveau_private *dev_priv = dev->dev_private;
 316
 317         if (dev_priv->card_type == NV_04) {
 318                 dev_priv->vram_size = nouveau_mem_detect_nv04(dev);
 319         } else
 320         if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) {
 321                 dev_priv->vram_size = nouveau_mem_detect_nforce(dev);
 322         } else
 323         if (dev_priv->card_type < NV_50) {
 324                 dev_priv->vram_size  = nv_rd32(dev, NV04_PFB_FIFO_DATA);
 325                 dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
 326         } else
 327         if (dev_priv->card_type < NV_C0) {
 328                 dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA);
 329                 dev_priv->vram_size |= (dev_priv->vram_size & 0xff) << 32;
 330                 dev_priv->vram_size &= 0xffffffff00ll;
 331                 if (dev_priv->chipset == 0xaa || dev_priv->chipset == 0xac) {
 332                         dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10);
 333                         dev_priv->vram_sys_base <<= 12;
 334                 }
 335         } else {
 336                 dev_priv->vram_size  = nv_rd32(dev, 0x10f20c) << 20;
 337                 dev_priv->vram_size *= nv_rd32(dev, 0x121c74);
 338         }
 339
 340         NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
 341         if (dev_priv->vram_sys_base) {
 342                 NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
 343                         dev_priv->vram_sys_base);
 344         }
 345
 346         if (dev_priv->vram_size)
 347                 return 0;
 348         return -ENOMEM;
 349 }
 350
 351 int
 352 nouveau_mem_reset_agp(struct drm_device *dev)
 353 {
 354 #if __OS_HAS_AGP
 355         uint32_t saved_pci_nv_1, pmc_enable;
 356         int ret;
 357
 358         /* First of all, disable fast writes, otherwise if it's
 359          * already enabled in the AGP bridge and we disable the card's
 360          * AGP controller we might be locking ourselves out of it. */
 361         if ((nv_rd32(dev, NV04_PBUS_PCI_NV_19) |
 362              dev->agp->mode) & PCI_AGP_COMMAND_FW) {
 363                 struct drm_agp_info info;
 364                 struct drm_agp_mode mode;
 365
 366                 ret = drm_agp_info(dev, &info);
 367                 if (ret)
 368                         return ret;
 369
 370                 mode.mode = info.mode & ~PCI_AGP_COMMAND_FW;
 371                 ret = drm_agp_enable(dev, mode);
 372                 if (ret)
 373                         return ret;
 374         }
 375
 376         saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);
 377
 378         /* clear busmaster bit */
 379         nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
 380         /* disable AGP */
 381         nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0);
 382
 383         /* power cycle pgraph, if enabled */
 384         pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
 385         if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
 386                 nv_wr32(dev, NV03_PMC_ENABLE,
 387                                 pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
 388                 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
 389                                 NV_PMC_ENABLE_PGRAPH);
 390         }
 391
 392         /* and restore (gives effect of resetting AGP) */
 393         nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
 394 #endif
 395
 396         return 0;
 397 }
 398
 399 int
 400 nouveau_mem_init_agp(struct drm_device *dev)
 401 {
 402 #if __OS_HAS_AGP
 403         struct drm_nouveau_private *dev_priv = dev->dev_private;
 404         struct drm_agp_info info;
 405         struct drm_agp_mode mode;
 406         int ret;
 407
 408         if (!dev->agp->acquired) {
 409                 ret = drm_agp_acquire(dev);
 410                 if (ret) {
 411                         NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
 412                         return ret;
 413                 }
 414         }
 415
 416         nouveau_mem_reset_agp(dev);
 417
 418         ret = drm_agp_info(dev, &info);
 419         if (ret) {
 420                 NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
 421                 return ret;
 422         }
 423
 424         /* see agp.h for the AGPSTAT_* modes available */
 425         mode.mode = info.mode;
 426         ret = drm_agp_enable(dev, mode);
 427         if (ret) {
 428                 NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
 429                 return ret;
 430         }
 431
 432         dev_priv->gart_info.type        = NOUVEAU_GART_AGP;
 433         dev_priv->gart_info.aper_base   = info.aperture_base;
 434         dev_priv->gart_info.aper_size   = info.aperture_size;
 435 #endif
 436         return 0;
 437 }
 438
 439 int
 440 nouveau_mem_init(struct drm_device *dev)
 441 {
 442         struct drm_nouveau_private *dev_priv = dev->dev_private;
 443         struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
 444         int ret, dma_bits = 32;
 445
 446         dev_priv->fb_phys = pci_resource_start(dev->pdev, 1);
 447         dev_priv->gart_info.type = NOUVEAU_GART_NONE;
 448
 449         if (dev_priv->card_type >= NV_50 &&
 450             pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
 451                 dma_bits = 40;
 452
 453         ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
 454         if (ret) {
 455                 NV_ERROR(dev, "Error setting DMA mask: %d\n", ret);
 456                 return ret;
 457         }
 458
 459         ret = nouveau_ttm_global_init(dev_priv);
 460         if (ret)
 461                 return ret;
 462
 463         ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
 464                                  dev_priv->ttm.bo_global_ref.ref.object,
 465                                  &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
 466                                  dma_bits <= 32 ? true : false);
 467         if (ret) {
 468                 NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
 469                 return ret;
 470         }
 471
 472         spin_lock_init(&dev_priv->tile.lock);
 473
 474         dev_priv->fb_available_size = dev_priv->vram_size;
 475         dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
 476         if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1))
 477                 dev_priv->fb_mappable_pages =
 478                         pci_resource_len(dev->pdev, 1);
 479         dev_priv->fb_mappable_pages >>= PAGE_SHIFT;
 480
 481         /* remove reserved space at end of vram from available amount */
 482         dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
 483         dev_priv->fb_aper_free = dev_priv->fb_available_size;
 484
 485         /* mappable vram */
 486         ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
 487                              dev_priv->fb_available_size >> PAGE_SHIFT);
 488         if (ret) {
 489                 NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
 490                 return ret;
 491         }
 492
 493         ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM,
 494                              0, 0, true, true, &dev_priv->vga_ram);
 495         if (ret == 0)
 496                 ret = nouveau_bo_pin(dev_priv->vga_ram, TTM_PL_FLAG_VRAM);
 497         if (ret) {
 498                 NV_WARN(dev, "failed to reserve VGA memory\n");
 499                 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
 500         }
 501
 502         /* GART */
 503 #if !defined(__powerpc__) && !defined(__ia64__)
 504         if (drm_device_is_agp(dev) && dev->agp && !nouveau_noagp) {
 505                 ret = nouveau_mem_init_agp(dev);
 506                 if (ret)
 507                         NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
 508         }
 509 #endif
 510
 511         if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
 512                 ret = nouveau_sgdma_init(dev);
 513                 if (ret) {
 514                         NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
 515                         return ret;
 516                 }
 517         }
 518
 519         NV_INFO(dev, "%d MiB GART (aperture)\n",
 520                 (int)(dev_priv->gart_info.aper_size >> 20));
 521         dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;
 522
 523         ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
 524                              dev_priv->gart_info.aper_size >> PAGE_SHIFT);
 525         if (ret) {
 526                 NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
 527                 return ret;
 528         }
 529
 530         dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1),
 531                                          pci_resource_len(dev->pdev, 1),
 532                                          DRM_MTRR_WC);
 533
 534         return 0;
 535 }
 536
 537