2 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3 * Copyright 2005 Stephane Marchesin
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
29 * Keith Whitwell <keith@tungstengraphics.com>
35 #include "drm_sarea.h"
36 #include "nouveau_drv.h"
38 #define MIN(a,b) a < b ? a : b
41 * NV10-NV40 tiling helpers
45 nv10_mem_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
46 uint32_t size, uint32_t pitch)
48 struct drm_nouveau_private *dev_priv = dev->dev_private;
49 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
50 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
51 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
52 struct nouveau_tile_reg *tile = &dev_priv->tile[i];
57 nouveau_fence_unref((void **)&tile->fence);
59 pfifo->reassign(dev, false);
60 pfifo->cache_pull(dev, false);
62 nouveau_wait_for_idle(dev);
64 pgraph->set_region_tiling(dev, i, addr, size, pitch);
65 pfb->set_region_tiling(dev, i, addr, size, pitch);
67 pfifo->cache_pull(dev, true);
68 pfifo->reassign(dev, true);
71 struct nouveau_tile_reg *
72 nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
75 struct drm_nouveau_private *dev_priv = dev->dev_private;
76 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
77 struct nouveau_tile_reg *found = NULL;
78 unsigned long i, flags;
80 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
82 for (i = 0; i < pfb->num_tiles; i++) {
83 struct nouveau_tile_reg *tile = &dev_priv->tile[i];
86 /* Tile region in use. */
90 !nouveau_fence_signalled(tile->fence, NULL))
91 /* Pending tile region. */
94 if (max(tile->addr, addr) <
95 min(tile->addr + tile->size, addr + size))
96 /* Kill an intersecting tile region. */
97 nv10_mem_set_region_tiling(dev, i, 0, 0, 0);
99 if (pitch && !found) {
100 /* Free tile region. */
101 nv10_mem_set_region_tiling(dev, i, addr, size, pitch);
106 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
112 nv10_mem_expire_tiling(struct drm_device *dev, struct nouveau_tile_reg *tile,
113 struct nouveau_fence *fence)
116 /* Mark it as pending. */
118 nouveau_fence_ref(fence);
128 nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
129 uint32_t flags, uint64_t phys)
131 struct drm_nouveau_private *dev_priv = dev->dev_private;
132 struct nouveau_gpuobj *pgt;
136 virt = ((virt - dev_priv->vm_vram_base) >> 16) << 1;
137 size = (size >> 16) << 1;
139 phys |= ((uint64_t)flags << 32);
141 if (dev_priv->vram_sys_base) {
142 phys += dev_priv->vram_sys_base;
147 unsigned offset_h = upper_32_bits(phys);
148 unsigned offset_l = lower_32_bits(phys);
151 for (i = 7; i >= 0; i--) {
152 block = 1 << (i + 1);
153 if (size >= block && !(virt & (block - 1)))
156 offset_l |= (i << 7);
162 pgt = dev_priv->vm_vram_pt[virt >> 14];
168 block -= (end - pte);
172 nv_wo32(pgt, (pte * 4) + 0, offset_l);
173 nv_wo32(pgt, (pte * 4) + 4, offset_h);
178 dev_priv->engine.instmem.flush(dev);
180 nv50_vm_flush(dev, 5);
181 nv50_vm_flush(dev, 0);
182 nv50_vm_flush(dev, 4);
183 nv50_vm_flush(dev, 6);
188 nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size)
190 struct drm_nouveau_private *dev_priv = dev->dev_private;
191 struct nouveau_gpuobj *pgt;
192 unsigned pages, pte, end;
194 virt -= dev_priv->vm_vram_base;
195 pages = (size >> 16) << 1;
198 pgt = dev_priv->vm_vram_pt[virt >> 29];
199 pte = (virt & 0x1ffe0000ULL) >> 15;
204 pages -= (end - pte);
205 virt += (end - pte) << 15;
208 nv_wo32(pgt, (pte * 4), 0);
212 dev_priv->engine.instmem.flush(dev);
214 nv50_vm_flush(dev, 5);
215 nv50_vm_flush(dev, 0);
216 nv50_vm_flush(dev, 4);
217 nv50_vm_flush(dev, 6);
224 nouveau_mem_vram_fini(struct drm_device *dev)
226 struct drm_nouveau_private *dev_priv = dev->dev_private;
228 nouveau_bo_unpin(dev_priv->vga_ram);
229 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
231 ttm_bo_device_release(&dev_priv->ttm.bdev);
233 nouveau_ttm_global_release(dev_priv);
235 if (dev_priv->fb_mtrr >= 0) {
236 drm_mtrr_del(dev_priv->fb_mtrr,
237 pci_resource_start(dev->pdev, 1),
238 pci_resource_len(dev->pdev, 1), DRM_MTRR_WC);
239 dev_priv->fb_mtrr = -1;
244 nouveau_mem_gart_fini(struct drm_device *dev)
246 nouveau_sgdma_takedown(dev);
248 if (drm_core_has_AGP(dev) && dev->agp) {
249 struct drm_agp_mem *entry, *tempe;
251 /* Remove AGP resources, but leave dev->agp
252 intact until drv_cleanup is called. */
253 list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
255 drm_unbind_agp(entry->memory);
256 drm_free_agp(entry->memory, entry->pages);
259 INIT_LIST_HEAD(&dev->agp->memory);
261 if (dev->agp->acquired)
262 drm_agp_release(dev);
264 dev->agp->acquired = 0;
265 dev->agp->enabled = 0;
270 nouveau_mem_detect_nv04(struct drm_device *dev)
272 uint32_t boot0 = nv_rd32(dev, NV04_PFB_BOOT_0);
274 if (boot0 & 0x00000100)
275 return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;
277 switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
278 case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
279 return 32 * 1024 * 1024;
280 case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
281 return 16 * 1024 * 1024;
282 case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
283 return 8 * 1024 * 1024;
284 case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
285 return 4 * 1024 * 1024;
292 nouveau_mem_detect_nforce(struct drm_device *dev)
294 struct drm_nouveau_private *dev_priv = dev->dev_private;
295 struct pci_dev *bridge;
298 bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
300 NV_ERROR(dev, "no bridge device\n");
304 if (dev_priv->flags & NV_NFORCE) {
305 pci_read_config_dword(bridge, 0x7C, &mem);
306 return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024;
308 if (dev_priv->flags & NV_NFORCE2) {
309 pci_read_config_dword(bridge, 0x84, &mem);
310 return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024;
313 NV_ERROR(dev, "impossible!\n");
318 nv50_vram_preinit(struct drm_device *dev)
320 struct drm_nouveau_private *dev_priv = dev->dev_private;
321 int i, parts, colbits, rowbitsa, rowbitsb, banks;
322 u64 rowsize, predicted;
325 r0 = nv_rd32(dev, 0x100200);
326 r4 = nv_rd32(dev, 0x100204);
327 rt = nv_rd32(dev, 0x100250);
328 ru = nv_rd32(dev, 0x001540);
329 NV_DEBUG(dev, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt, ru);
331 for (i = 0, parts = 0; i < 8; i++) {
332 if (ru & (0x00010000 << i))
336 colbits = (r4 & 0x0000f000) >> 12;
337 rowbitsa = ((r4 & 0x000f0000) >> 16) + 8;
338 rowbitsb = ((r4 & 0x00f00000) >> 20) + 8;
339 banks = ((r4 & 0x01000000) ? 8 : 4);
341 rowsize = parts * banks * (1 << colbits) * 8;
342 predicted = rowsize << rowbitsa;
344 predicted += rowsize << rowbitsb;
346 if (predicted != dev_priv->vram_size) {
347 NV_WARN(dev, "memory controller reports %dMiB VRAM\n",
348 (u32)(dev_priv->vram_size >> 20));
349 NV_WARN(dev, "we calculated %dMiB VRAM\n",
350 (u32)(predicted >> 20));
353 dev_priv->vram_rblock_size = rowsize >> 12;
355 dev_priv->vram_rblock_size *= 3;
357 NV_DEBUG(dev, "rblock %lld bytes\n",
358 (u64)dev_priv->vram_rblock_size << 12);
362 nvaa_vram_preinit(struct drm_device *dev)
364 struct drm_nouveau_private *dev_priv = dev->dev_private;
366 /* To our knowledge, there's no large scale reordering of pages
367 * that occurs on IGP chipsets.
369 dev_priv->vram_rblock_size = 1;
373 nouveau_mem_detect(struct drm_device *dev)
375 struct drm_nouveau_private *dev_priv = dev->dev_private;
377 if (dev_priv->card_type == NV_04) {
378 dev_priv->vram_size = nouveau_mem_detect_nv04(dev);
380 if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) {
381 dev_priv->vram_size = nouveau_mem_detect_nforce(dev);
383 if (dev_priv->card_type < NV_50) {
384 dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA);
385 dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
387 if (dev_priv->card_type < NV_C0) {
388 dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA);
389 dev_priv->vram_size |= (dev_priv->vram_size & 0xff) << 32;
390 dev_priv->vram_size &= 0xffffffff00ll;
392 switch (dev_priv->chipset) {
396 dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10);
397 dev_priv->vram_sys_base <<= 12;
398 nvaa_vram_preinit(dev);
401 nv50_vram_preinit(dev);
405 dev_priv->vram_size = nv_rd32(dev, 0x10f20c) << 20;
406 dev_priv->vram_size *= nv_rd32(dev, 0x121c74);
409 NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
410 if (dev_priv->vram_sys_base) {
411 NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
412 dev_priv->vram_sys_base);
415 if (dev_priv->vram_size)
422 get_agp_mode(struct drm_device *dev, unsigned long mode)
424 struct drm_nouveau_private *dev_priv = dev->dev_private;
427 * FW seems to be broken on nv18, it makes the card lock up
430 if (dev_priv->chipset == 0x18)
431 mode &= ~PCI_AGP_COMMAND_FW;
434 * AGP mode set in the command line.
436 if (nouveau_agpmode > 0) {
437 bool agpv3 = mode & 0x8;
438 int rate = agpv3 ? nouveau_agpmode / 4 : nouveau_agpmode;
440 mode = (mode & ~0x7) | (rate & 0x7);
448 nouveau_mem_reset_agp(struct drm_device *dev)
451 uint32_t saved_pci_nv_1, pmc_enable;
454 /* First of all, disable fast writes, otherwise if it's
455 * already enabled in the AGP bridge and we disable the card's
456 * AGP controller we might be locking ourselves out of it. */
457 if ((nv_rd32(dev, NV04_PBUS_PCI_NV_19) |
458 dev->agp->mode) & PCI_AGP_COMMAND_FW) {
459 struct drm_agp_info info;
460 struct drm_agp_mode mode;
462 ret = drm_agp_info(dev, &info);
466 mode.mode = get_agp_mode(dev, info.mode) & ~PCI_AGP_COMMAND_FW;
467 ret = drm_agp_enable(dev, mode);
472 saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);
474 /* clear busmaster bit */
475 nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
477 nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0);
479 /* power cycle pgraph, if enabled */
480 pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
481 if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
482 nv_wr32(dev, NV03_PMC_ENABLE,
483 pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
484 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
485 NV_PMC_ENABLE_PGRAPH);
488 /* and restore (gives effect of resetting AGP) */
489 nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
496 nouveau_mem_init_agp(struct drm_device *dev)
499 struct drm_nouveau_private *dev_priv = dev->dev_private;
500 struct drm_agp_info info;
501 struct drm_agp_mode mode;
504 if (!dev->agp->acquired) {
505 ret = drm_agp_acquire(dev);
507 NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
512 nouveau_mem_reset_agp(dev);
514 ret = drm_agp_info(dev, &info);
516 NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
520 /* see agp.h for the AGPSTAT_* modes available */
521 mode.mode = get_agp_mode(dev, info.mode);
522 ret = drm_agp_enable(dev, mode);
524 NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
528 dev_priv->gart_info.type = NOUVEAU_GART_AGP;
529 dev_priv->gart_info.aper_base = info.aperture_base;
530 dev_priv->gart_info.aper_size = info.aperture_size;
536 nouveau_mem_vram_init(struct drm_device *dev)
538 struct drm_nouveau_private *dev_priv = dev->dev_private;
539 struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
542 if (dev_priv->card_type >= NV_50 &&
543 pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
548 ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
552 ret = nouveau_mem_detect(dev);
556 dev_priv->fb_phys = pci_resource_start(dev->pdev, 1);
558 ret = nouveau_ttm_global_init(dev_priv);
562 ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
563 dev_priv->ttm.bo_global_ref.ref.object,
564 &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
565 dma_bits <= 32 ? true : false);
567 NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
571 dev_priv->fb_available_size = dev_priv->vram_size;
572 dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
573 if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1))
574 dev_priv->fb_mappable_pages =
575 pci_resource_len(dev->pdev, 1);
576 dev_priv->fb_mappable_pages >>= PAGE_SHIFT;
578 /* reserve space at end of VRAM for PRAMIN */
579 if (dev_priv->chipset == 0x40 || dev_priv->chipset == 0x47 ||
580 dev_priv->chipset == 0x49 || dev_priv->chipset == 0x4b)
581 dev_priv->ramin_rsvd_vram = (2 * 1024 * 1024);
583 if (dev_priv->card_type >= NV_40)
584 dev_priv->ramin_rsvd_vram = (1 * 1024 * 1024);
586 dev_priv->ramin_rsvd_vram = (512 * 1024);
588 dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
589 dev_priv->fb_aper_free = dev_priv->fb_available_size;
592 ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
593 dev_priv->fb_available_size >> PAGE_SHIFT);
595 NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
599 ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM,
600 0, 0, true, true, &dev_priv->vga_ram);
602 ret = nouveau_bo_pin(dev_priv->vga_ram, TTM_PL_FLAG_VRAM);
604 NV_WARN(dev, "failed to reserve VGA memory\n");
605 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
608 dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1),
609 pci_resource_len(dev->pdev, 1),
615 nouveau_mem_gart_init(struct drm_device *dev)
617 struct drm_nouveau_private *dev_priv = dev->dev_private;
618 struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
621 dev_priv->gart_info.type = NOUVEAU_GART_NONE;
623 #if !defined(__powerpc__) && !defined(__ia64__)
624 if (drm_device_is_agp(dev) && dev->agp && nouveau_agpmode) {
625 ret = nouveau_mem_init_agp(dev);
627 NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
631 if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
632 ret = nouveau_sgdma_init(dev);
634 NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
639 NV_INFO(dev, "%d MiB GART (aperture)\n",
640 (int)(dev_priv->gart_info.aper_size >> 20));
641 dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;
643 ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
644 dev_priv->gart_info.aper_size >> PAGE_SHIFT);
646 NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
654 nouveau_mem_timing_init(struct drm_device *dev)
656 struct drm_nouveau_private *dev_priv = dev->dev_private;
657 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
658 struct nouveau_pm_memtimings *memtimings = &pm->memtimings;
659 struct nvbios *bios = &dev_priv->vbios;
661 u8 tUNK_0, tUNK_1, tUNK_2;
663 u8 tRAS; /* Byte 5 */
664 u8 tRFC; /* Byte 7 */
666 u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14;
667 u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21;
668 u8 *mem = NULL, *entry;
669 int i, recordlen, entries;
671 if (bios->type == NVBIOS_BIT) {
672 if (bit_table(dev, 'P', &P))
676 mem = ROMPTR(bios, P.data[4]);
679 mem = ROMPTR(bios, P.data[8]);
681 NV_WARN(dev, "unknown mem for BIT P %d\n", P.version);
684 NV_DEBUG(dev, "BMP version too old for memory\n");
689 NV_DEBUG(dev, "memory timing table pointer invalid\n");
693 if (mem[0] != 0x10) {
694 NV_WARN(dev, "memory timing table 0x%02x unknown\n", mem[0]);
698 /* validate record length */
701 if (recordlen < 15) {
702 NV_ERROR(dev, "mem timing table length unknown: %d\n", mem[3]);
706 /* parse vbios entries into common format */
708 kcalloc(entries, sizeof(*memtimings->timing), GFP_KERNEL);
709 if (!memtimings->timing)
712 entry = mem + mem[1];
713 for (i = 0; i < entries; i++, entry += recordlen) {
714 struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i];
722 switch (MIN(recordlen,21)) {
747 timing->reg_100220 = (tRC << 24 | tRFC << 16 | tRAS << 8 | tRP);
749 /* XXX: I don't trust the -1's and +1's... they must come
751 timing->reg_100224 = ((tUNK_0 + tUNK_19 + 1) << 24 |
753 (tUNK_1 + tUNK_19 + 1) << 8 |
756 timing->reg_100228 = (tUNK_12 << 16 | tUNK_11 << 8 | tUNK_10);
758 timing->reg_100228 += (tUNK_19 - 1) << 24;
760 timing->reg_100228 += tUNK_12 << 24;
763 /* XXX: reg_10022c */
765 timing->reg_100230 = (tUNK_20 << 24 | tUNK_21 << 16 |
766 tUNK_13 << 8 | tUNK_13);
769 timing->reg_100234 = (tRAS << 24 | (tUNK_19 + 6) << 8 | tRC);
770 if(tUNK_10 > tUNK_11) {
771 timing->reg_100234 += tUNK_10 << 16;
773 timing->reg_100234 += tUNK_11 << 16;
776 /* XXX; reg_100238, reg_10023c */
777 NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", i,
778 timing->reg_100220, timing->reg_100224,
779 timing->reg_100228, timing->reg_10022c);
780 NV_DEBUG(dev, " 230: %08x %08x %08x %08x\n",
781 timing->reg_100230, timing->reg_100234,
782 timing->reg_100238, timing->reg_10023c);
785 memtimings->nr_timing = entries;
786 memtimings->supported = true;
790 nouveau_mem_timing_fini(struct drm_device *dev)
792 struct drm_nouveau_private *dev_priv = dev->dev_private;
793 struct nouveau_pm_memtimings *mem = &dev_priv->engine.pm.memtimings;