drivers/gpu/drm/nouveau/nouveau_object.c

   1 /*
   2  * Copyright (C) 2006 Ben Skeggs.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 /*
  29  * Authors:
  30  *   Ben Skeggs <darktama@iinet.net.au>
  31  */
  32
  33 #include "drmP.h"
  34 #include "drm.h"
  35 #include "nouveau_drv.h"
  36 #include "nouveau_drm.h"
  37 #include "nouveau_ramht.h"
  38
  39 struct nouveau_gpuobj_method {
  40         struct list_head head;
  41         u32 mthd;
  42         int (*exec)(struct nouveau_channel *, u32 class, u32 mthd, u32 data);
  43 };
  44
  45 struct nouveau_gpuobj_class {
  46         struct list_head head;
  47         struct list_head methods;
  48         u32 id;
  49         u32 engine;
  50 };
  51
  52 int
  53 nouveau_gpuobj_class_new(struct drm_device *dev, u32 class, u32 engine)
  54 {
  55         struct drm_nouveau_private *dev_priv = dev->dev_private;
  56         struct nouveau_gpuobj_class *oc;
  57
  58         oc = kzalloc(sizeof(*oc), GFP_KERNEL);
  59         if (!oc)
  60                 return -ENOMEM;
  61
  62         INIT_LIST_HEAD(&oc->methods);
  63         oc->id = class;
  64         oc->engine = engine;
  65         list_add(&oc->head, &dev_priv->classes);
  66         return 0;
  67 }
  68
  69 int
  70 nouveau_gpuobj_mthd_new(struct drm_device *dev, u32 class, u32 mthd,
  71                         int (*exec)(struct nouveau_channel *, u32, u32, u32))
  72 {
  73         struct drm_nouveau_private *dev_priv = dev->dev_private;
  74         struct nouveau_gpuobj_method *om;
  75         struct nouveau_gpuobj_class *oc;
  76
  77         list_for_each_entry(oc, &dev_priv->classes, head) {
  78                 if (oc->id == class)
  79                         goto found;
  80         }
  81
  82         return -EINVAL;
  83
  84 found:
  85         om = kzalloc(sizeof(*om), GFP_KERNEL);
  86         if (!om)
  87                 return -ENOMEM;
  88
  89         om->mthd = mthd;
  90         om->exec = exec;
  91         list_add(&om->head, &oc->methods);
  92         return 0;
  93 }
  94
  95 int
  96 nouveau_gpuobj_mthd_call(struct nouveau_channel *chan,
  97                          u32 class, u32 mthd, u32 data)
  98 {
  99         struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
 100         struct nouveau_gpuobj_method *om;
 101         struct nouveau_gpuobj_class *oc;
 102
 103         list_for_each_entry(oc, &dev_priv->classes, head) {
 104                 if (oc->id != class)
 105                         continue;
 106
 107                 list_for_each_entry(om, &oc->methods, head) {
 108                         if (om->mthd == mthd)
 109                                 return om->exec(chan, class, mthd, data);
 110                 }
 111         }
 112
 113         return -ENOENT;
 114 }
 115
 116 /* NVidia uses context objects to drive drawing operations.
 117
 118    Context objects can be selected into 8 subchannels in the FIFO,
 119    and then used via DMA command buffers.
 120
 121    A context object is referenced by a user defined handle (CARD32). The HW
 122    looks up graphics objects in a hash table in the instance RAM.
 123
 124    An entry in the hash table consists of 2 CARD32. The first CARD32 contains
 125    the handle, the second one a bitfield, that contains the address of the
 126    object in instance RAM.
 127
 128    The format of the second CARD32 seems to be:
 129
 130    NV4 to NV30:
 131
 132    15: 0  instance_addr >> 4
 133    17:16  engine (here uses 1 = graphics)
 134    28:24  channel id (here uses 0)
 135    31     valid (use 1)
 136
 137    NV40:
 138
 139    15: 0  instance_addr >> 4   (maybe 19-0)
 140    21:20  engine (here uses 1 = graphics)
 141    I'm unsure about the other bits, but using 0 seems to work.
 142
 143    The key into the hash table depends on the object handle and channel id and
 144    is given as:
 145 */
 146
 147 int
 148 nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan,
 149                    uint32_t size, int align, uint32_t flags,
 150                    struct nouveau_gpuobj **gpuobj_ret)
 151 {
 152         struct drm_nouveau_private *dev_priv = dev->dev_private;
 153         struct nouveau_engine *engine = &dev_priv->engine;
 154         struct nouveau_gpuobj *gpuobj;
 155         struct drm_mm_node *ramin = NULL;
 156         int ret;
 157
 158         NV_DEBUG(dev, "ch%d size=%u align=%d flags=0x%08x\n",
 159                  chan ? chan->id : -1, size, align, flags);
 160
 161         if (!dev_priv || !gpuobj_ret || *gpuobj_ret != NULL)
 162                 return -EINVAL;
 163
 164         gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);
 165         if (!gpuobj)
 166                 return -ENOMEM;
 167         NV_DEBUG(dev, "gpuobj %p\n", gpuobj);
 168         gpuobj->dev = dev;
 169         gpuobj->flags = flags;
 170         kref_init(&gpuobj->refcount);
 171         gpuobj->size = size;
 172
 173         spin_lock(&dev_priv->ramin_lock);
 174         list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
 175         spin_unlock(&dev_priv->ramin_lock);
 176
 177         if (chan) {
 178                 NV_DEBUG(dev, "channel heap\n");
 179
 180                 ramin = drm_mm_search_free(&chan->ramin_heap, size, align, 0);
 181                 if (ramin)
 182                         ramin = drm_mm_get_block(ramin, size, align);
 183
 184                 if (!ramin) {
 185                         nouveau_gpuobj_ref(NULL, &gpuobj);
 186                         return -ENOMEM;
 187                 }
 188         } else {
 189                 NV_DEBUG(dev, "global heap\n");
 190
 191                 /* allocate backing pages, sets vinst */
 192                 ret = engine->instmem.populate(dev, gpuobj, &size, align);
 193                 if (ret) {
 194                         nouveau_gpuobj_ref(NULL, &gpuobj);
 195                         return ret;
 196                 }
 197
 198                 /* try and get aperture space */
 199                 do {
 200                         if (drm_mm_pre_get(&dev_priv->ramin_heap))
 201                                 return -ENOMEM;
 202
 203                         spin_lock(&dev_priv->ramin_lock);
 204                         ramin = drm_mm_search_free(&dev_priv->ramin_heap, size,
 205                                                    align, 0);
 206                         if (ramin == NULL) {
 207                                 spin_unlock(&dev_priv->ramin_lock);
 208                                 nouveau_gpuobj_ref(NULL, &gpuobj);
 209                                 return -ENOMEM;
 210                         }
 211
 212                         ramin = drm_mm_get_block_atomic(ramin, size, align);
 213                         spin_unlock(&dev_priv->ramin_lock);
 214                 } while (ramin == NULL);
 215
 216                 /* on nv50 it's ok to fail, we have a fallback path */
 217                 if (!ramin && dev_priv->card_type < NV_50) {
 218                         nouveau_gpuobj_ref(NULL, &gpuobj);
 219                         return -ENOMEM;
 220                 }
 221         }
 222
 223         /* if we got a chunk of the aperture, map pages into it */
 224         gpuobj->im_pramin = ramin;
 225         if (!chan && gpuobj->im_pramin && dev_priv->ramin_available) {
 226                 ret = engine->instmem.bind(dev, gpuobj);
 227                 if (ret) {
 228                         nouveau_gpuobj_ref(NULL, &gpuobj);
 229                         return ret;
 230                 }
 231         }
 232
 233         /* calculate the various different addresses for the object */
 234         if (chan) {
 235                 gpuobj->pinst = chan->ramin->pinst;
 236                 if (gpuobj->pinst != ~0)
 237                         gpuobj->pinst += gpuobj->im_pramin->start;
 238
 239                 if (dev_priv->card_type < NV_50) {
 240                         gpuobj->cinst = gpuobj->pinst;
 241                 } else {
 242                         gpuobj->cinst = gpuobj->im_pramin->start;
 243                         gpuobj->vinst = gpuobj->im_pramin->start +
 244                                         chan->ramin->vinst;
 245                 }
 246         } else {
 247                 if (gpuobj->im_pramin)
 248                         gpuobj->pinst = gpuobj->im_pramin->start;
 249                 else
 250                         gpuobj->pinst = ~0;
 251                 gpuobj->cinst = 0xdeadbeef;
 252         }
 253
 254         if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {
 255                 int i;
 256
 257                 for (i = 0; i < gpuobj->size; i += 4)
 258                         nv_wo32(gpuobj, i, 0);
 259                 engine->instmem.flush(dev);
 260         }
 261
 262
 263         *gpuobj_ret = gpuobj;
 264         return 0;
 265 }
 266
 267 int
 268 nouveau_gpuobj_init(struct drm_device *dev)
 269 {
 270         struct drm_nouveau_private *dev_priv = dev->dev_private;
 271
 272         NV_DEBUG(dev, "\n");
 273
 274         INIT_LIST_HEAD(&dev_priv->gpuobj_list);
 275         INIT_LIST_HEAD(&dev_priv->classes);
 276         spin_lock_init(&dev_priv->ramin_lock);
 277         dev_priv->ramin_base = ~0;
 278
 279         return 0;
 280 }
 281
 282 void
 283 nouveau_gpuobj_takedown(struct drm_device *dev)
 284 {
 285         struct drm_nouveau_private *dev_priv = dev->dev_private;
 286         struct nouveau_gpuobj_method *om, *tm;
 287         struct nouveau_gpuobj_class *oc, *tc;
 288
 289         NV_DEBUG(dev, "\n");
 290
 291         list_for_each_entry_safe(oc, tc, &dev_priv->classes, head) {
 292                 list_for_each_entry_safe(om, tm, &oc->methods, head) {
 293                         list_del(&om->head);
 294                         kfree(om);
 295                 }
 296                 list_del(&oc->head);
 297                 kfree(oc);
 298         }
 299
 300         BUG_ON(!list_empty(&dev_priv->gpuobj_list));
 301 }
 302
 303
 304 static void
 305 nouveau_gpuobj_del(struct kref *ref)
 306 {
 307         struct nouveau_gpuobj *gpuobj =
 308                 container_of(ref, struct nouveau_gpuobj, refcount);
 309         struct drm_device *dev = gpuobj->dev;
 310         struct drm_nouveau_private *dev_priv = dev->dev_private;
 311         struct nouveau_engine *engine = &dev_priv->engine;
 312         int i;
 313
 314         NV_DEBUG(dev, "gpuobj %p\n", gpuobj);
 315
 316         if (gpuobj->im_pramin && (gpuobj->flags & NVOBJ_FLAG_ZERO_FREE)) {
 317                 for (i = 0; i < gpuobj->size; i += 4)
 318                         nv_wo32(gpuobj, i, 0);
 319                 engine->instmem.flush(dev);
 320         }
 321
 322         if (gpuobj->dtor)
 323                 gpuobj->dtor(dev, gpuobj);
 324
 325         if (gpuobj->im_backing)
 326                 engine->instmem.clear(dev, gpuobj);
 327
 328         spin_lock(&dev_priv->ramin_lock);
 329         if (gpuobj->im_pramin)
 330                 drm_mm_put_block(gpuobj->im_pramin);
 331         list_del(&gpuobj->list);
 332         spin_unlock(&dev_priv->ramin_lock);
 333
 334         kfree(gpuobj);
 335 }
 336
 337 void
 338 nouveau_gpuobj_ref(struct nouveau_gpuobj *ref, struct nouveau_gpuobj **ptr)
 339 {
 340         if (ref)
 341                 kref_get(&ref->refcount);
 342
 343         if (*ptr)
 344                 kref_put(&(*ptr)->refcount, nouveau_gpuobj_del);
 345
 346         *ptr = ref;
 347 }
 348
 349 int
 350 nouveau_gpuobj_new_fake(struct drm_device *dev, u32 pinst, u64 vinst,
 351                         u32 size, u32 flags, struct nouveau_gpuobj **pgpuobj)
 352 {
 353         struct drm_nouveau_private *dev_priv = dev->dev_private;
 354         struct nouveau_gpuobj *gpuobj = NULL;
 355         int i;
 356
 357         NV_DEBUG(dev,
 358                  "pinst=0x%08x vinst=0x%010llx size=0x%08x flags=0x%08x\n",
 359                  pinst, vinst, size, flags);
 360
 361         gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);
 362         if (!gpuobj)
 363                 return -ENOMEM;
 364         NV_DEBUG(dev, "gpuobj %p\n", gpuobj);
 365         gpuobj->dev = dev;
 366         gpuobj->flags = flags;
 367         kref_init(&gpuobj->refcount);
 368         gpuobj->size  = size;
 369         gpuobj->pinst = pinst;
 370         gpuobj->cinst = 0xdeadbeef;
 371         gpuobj->vinst = vinst;
 372
 373         if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {
 374                 for (i = 0; i < gpuobj->size; i += 4)
 375                         nv_wo32(gpuobj, i, 0);
 376                 dev_priv->engine.instmem.flush(dev);
 377         }
 378
 379         spin_lock(&dev_priv->ramin_lock);
 380         list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
 381         spin_unlock(&dev_priv->ramin_lock);
 382         *pgpuobj = gpuobj;
 383         return 0;
 384 }
 385
 386
 387 static uint32_t
 388 nouveau_gpuobj_class_instmem_size(struct drm_device *dev, int class)
 389 {
 390         struct drm_nouveau_private *dev_priv = dev->dev_private;
 391
 392         /*XXX: dodgy hack for now */
 393         if (dev_priv->card_type >= NV_50)
 394                 return 24;
 395         if (dev_priv->card_type >= NV_40)
 396                 return 32;
 397         return 16;
 398 }
 399
 400 /*
 401    DMA objects are used to reference a piece of memory in the
 402    framebuffer, PCI or AGP address space. Each object is 16 bytes big
 403    and looks as follows:
 404
 405    entry[0]
 406    11:0  class (seems like I can always use 0 here)
 407    12    page table present?
 408    13    page entry linear?
 409    15:14 access: 0 rw, 1 ro, 2 wo
 410    17:16 target: 0 NV memory, 1 NV memory tiled, 2 PCI, 3 AGP
 411    31:20 dma adjust (bits 0-11 of the address)
 412    entry[1]
 413    dma limit (size of transfer)
 414    entry[X]
 415    1     0 readonly, 1 readwrite
 416    31:12 dma frame address of the page (bits 12-31 of the address)
 417    entry[N]
 418    page table terminator, same value as the first pte, as does nvidia
 419    rivatv uses 0xffffffff
 420
 421    Non linear page tables need a list of frame addresses afterwards,
 422    the rivatv project has some info on this.
 423
 424    The method below creates a DMA object in instance RAM and returns a handle
 425    to it that can be used to set up context objects.
 426 */
 427 int
 428 nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class,
 429                        uint64_t offset, uint64_t size, int access,
 430                        int target, struct nouveau_gpuobj **gpuobj)
 431 {
 432         struct drm_device *dev = chan->dev;
 433         struct drm_nouveau_private *dev_priv = dev->dev_private;
 434         struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
 435         int ret;
 436
 437         NV_DEBUG(dev, "ch%d class=0x%04x offset=0x%llx size=0x%llx\n",
 438                  chan->id, class, offset, size);
 439         NV_DEBUG(dev, "access=%d target=%d\n", access, target);
 440
 441         switch (target) {
 442         case NV_DMA_TARGET_AGP:
 443                 offset += dev_priv->gart_info.aper_base;
 444                 break;
 445         default:
 446                 break;
 447         }
 448
 449         ret = nouveau_gpuobj_new(dev, chan,
 450                                  nouveau_gpuobj_class_instmem_size(dev, class),
 451                                  16, NVOBJ_FLAG_ZERO_ALLOC |
 452                                  NVOBJ_FLAG_ZERO_FREE, gpuobj);
 453         if (ret) {
 454                 NV_ERROR(dev, "Error creating gpuobj: %d\n", ret);
 455                 return ret;
 456         }
 457
 458         if (dev_priv->card_type < NV_50) {
 459                 uint32_t frame, adjust, pte_flags = 0;
 460
 461                 if (access != NV_DMA_ACCESS_RO)
 462                         pte_flags |= (1<<1);
 463                 adjust = offset &  0x00000fff;
 464                 frame  = offset & ~0x00000fff;
 465
 466                 nv_wo32(*gpuobj,  0, ((1<<12) | (1<<13) | (adjust << 20) |
 467                                       (access << 14) | (target << 16) |
 468                                       class));
 469                 nv_wo32(*gpuobj,  4, size - 1);
 470                 nv_wo32(*gpuobj,  8, frame | pte_flags);
 471                 nv_wo32(*gpuobj, 12, frame | pte_flags);
 472         } else {
 473                 uint64_t limit = offset + size - 1;
 474                 uint32_t flags0, flags5;
 475
 476                 if (target == NV_DMA_TARGET_VIDMEM) {
 477                         flags0 = 0x00190000;
 478                         flags5 = 0x00010000;
 479                 } else {
 480                         flags0 = 0x7fc00000;
 481                         flags5 = 0x00080000;
 482                 }
 483
 484                 nv_wo32(*gpuobj,  0, flags0 | class);
 485                 nv_wo32(*gpuobj,  4, lower_32_bits(limit));
 486                 nv_wo32(*gpuobj,  8, lower_32_bits(offset));
 487                 nv_wo32(*gpuobj, 12, ((upper_32_bits(limit) & 0xff) << 24) |
 488                                       (upper_32_bits(offset) & 0xff));
 489                 nv_wo32(*gpuobj, 20, flags5);
 490         }
 491
 492         instmem->flush(dev);
 493
 494         (*gpuobj)->engine = NVOBJ_ENGINE_SW;
 495         (*gpuobj)->class  = class;
 496         return 0;
 497 }
 498
 499 int
 500 nouveau_gpuobj_gart_dma_new(struct nouveau_channel *chan,
 501                             uint64_t offset, uint64_t size, int access,
 502                             struct nouveau_gpuobj **gpuobj,
 503                             uint32_t *o_ret)
 504 {
 505         struct drm_device *dev = chan->dev;
 506         struct drm_nouveau_private *dev_priv = dev->dev_private;
 507         int ret;
 508
 509         if (dev_priv->gart_info.type == NOUVEAU_GART_AGP ||
 510             (dev_priv->card_type >= NV_50 &&
 511              dev_priv->gart_info.type == NOUVEAU_GART_SGDMA)) {
 512                 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
 513                                              offset + dev_priv->vm_gart_base,
 514                                              size, access, NV_DMA_TARGET_AGP,
 515                                              gpuobj);
 516                 if (o_ret)
 517                         *o_ret = 0;
 518         } else
 519         if (dev_priv->gart_info.type == NOUVEAU_GART_SGDMA) {
 520                 nouveau_gpuobj_ref(dev_priv->gart_info.sg_ctxdma, gpuobj);
 521                 if (offset & ~0xffffffffULL) {
 522                         NV_ERROR(dev, "obj offset exceeds 32-bits\n");
 523                         return -EINVAL;
 524                 }
 525                 if (o_ret)
 526                         *o_ret = (uint32_t)offset;
 527                 ret = (*gpuobj != NULL) ? 0 : -EINVAL;
 528         } else {
 529                 NV_ERROR(dev, "Invalid GART type %d\n", dev_priv->gart_info.type);
 530                 return -EINVAL;
 531         }
 532
 533         return ret;
 534 }
 535
 536 /* Context objects in the instance RAM have the following structure.
 537  * On NV40 they are 32 byte long, on NV30 and smaller 16 bytes.
 538
 539    NV4 - NV30:
 540
 541    entry[0]
 542    11:0 class
 543    12   chroma key enable
 544    13   user clip enable
 545    14   swizzle enable
 546    17:15 patch config:
 547        scrcopy_and, rop_and, blend_and, scrcopy, srccopy_pre, blend_pre
 548    18   synchronize enable
 549    19   endian: 1 big, 0 little
 550    21:20 dither mode
 551    23    single step enable
 552    24    patch status: 0 invalid, 1 valid
 553    25    context_surface 0: 1 valid
 554    26    context surface 1: 1 valid
 555    27    context pattern: 1 valid
 556    28    context rop: 1 valid
 557    29,30 context beta, beta4
 558    entry[1]
 559    7:0   mono format
 560    15:8  color format
 561    31:16 notify instance address
 562    entry[2]
 563    15:0  dma 0 instance address
 564    31:16 dma 1 instance address
 565    entry[3]
 566    dma method traps
 567
 568    NV40:
 569    No idea what the exact format is. Here's what can be deducted:
 570
 571    entry[0]:
 572    11:0  class  (maybe uses more bits here?)
 573    17    user clip enable
 574    21:19 patch config
 575    25    patch status valid ?
 576    entry[1]:
 577    15:0  DMA notifier  (maybe 20:0)
 578    entry[2]:
 579    15:0  DMA 0 instance (maybe 20:0)
 580    24    big endian
 581    entry[3]:
 582    15:0  DMA 1 instance (maybe 20:0)
 583    entry[4]:
 584    entry[5]:
 585    set to 0?
 586 */
 587 static int
 588 nouveau_gpuobj_sw_new(struct nouveau_channel *chan, int class,
 589                       struct nouveau_gpuobj **gpuobj_ret)
 590 {
 591         struct drm_nouveau_private *dev_priv;
 592         struct nouveau_gpuobj *gpuobj;
 593
 594         if (!chan || !gpuobj_ret || *gpuobj_ret != NULL)
 595                 return -EINVAL;
 596         dev_priv = chan->dev->dev_private;
 597
 598         gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);
 599         if (!gpuobj)
 600                 return -ENOMEM;
 601         gpuobj->dev = chan->dev;
 602         gpuobj->engine = NVOBJ_ENGINE_SW;
 603         gpuobj->class = class;
 604         kref_init(&gpuobj->refcount);
 605         gpuobj->cinst = 0x40;
 606
 607         spin_lock(&dev_priv->ramin_lock);
 608         list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
 609         spin_unlock(&dev_priv->ramin_lock);
 610         *gpuobj_ret = gpuobj;
 611         return 0;
 612 }
 613
 614 int
 615 nouveau_gpuobj_gr_new(struct nouveau_channel *chan, int class,
 616                       struct nouveau_gpuobj **gpuobj)
 617 {
 618         struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
 619         struct drm_device *dev = chan->dev;
 620         struct nouveau_gpuobj_class *oc;
 621         int ret;
 622
 623         NV_DEBUG(dev, "ch%d class=0x%04x\n", chan->id, class);
 624
 625         list_for_each_entry(oc, &dev_priv->classes, head) {
 626                 if (oc->id == class)
 627                         goto found;
 628         }
 629
 630         NV_ERROR(dev, "illegal object class: 0x%x\n", class);
 631         return -EINVAL;
 632
 633 found:
 634         if (oc->engine == NVOBJ_ENGINE_SW)
 635                 return nouveau_gpuobj_sw_new(chan, class, gpuobj);
 636
 637         switch (oc->engine) {
 638         case NVOBJ_ENGINE_GR:
 639                 if (dev_priv->card_type >= NV_50 && !chan->ramin_grctx) {
 640                         struct nouveau_pgraph_engine *pgraph =
 641                                 &dev_priv->engine.graph;
 642
 643                         ret = pgraph->create_context(chan);
 644                         if (ret)
 645                                 return ret;
 646                 }
 647                 break;
 648         case NVOBJ_ENGINE_CRYPT:
 649                 if (!chan->crypt_ctx) {
 650                         struct nouveau_crypt_engine *pcrypt =
 651                                 &dev_priv->engine.crypt;
 652
 653                         ret = pcrypt->create_context(chan);
 654                         if (ret)
 655                                 return ret;
 656                 }
 657                 break;
 658         }
 659
 660         ret = nouveau_gpuobj_new(dev, chan,
 661                                  nouveau_gpuobj_class_instmem_size(dev, class),
 662                                  16,
 663                                  NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE,
 664                                  gpuobj);
 665         if (ret) {
 666                 NV_ERROR(dev, "error creating gpuobj: %d\n", ret);
 667                 return ret;
 668         }
 669
 670         if (dev_priv->card_type >= NV_50) {
 671                 nv_wo32(*gpuobj,  0, class);
 672                 nv_wo32(*gpuobj, 20, 0x00010000);
 673         } else {
 674                 switch (class) {
 675                 case NV_CLASS_NULL:
 676                         nv_wo32(*gpuobj, 0, 0x00001030);
 677                         nv_wo32(*gpuobj, 4, 0xFFFFFFFF);
 678                         break;
 679                 default:
 680                         if (dev_priv->card_type >= NV_40) {
 681                                 nv_wo32(*gpuobj, 0, class);
 682 #ifdef __BIG_ENDIAN
 683                                 nv_wo32(*gpuobj, 8, 0x01000000);
 684 #endif
 685                         } else {
 686 #ifdef __BIG_ENDIAN
 687                                 nv_wo32(*gpuobj, 0, class | 0x00080000);
 688 #else
 689                                 nv_wo32(*gpuobj, 0, class);
 690 #endif
 691                         }
 692                 }
 693         }
 694         dev_priv->engine.instmem.flush(dev);
 695
 696         (*gpuobj)->engine = oc->engine;
 697         (*gpuobj)->class  = oc->id;
 698         return 0;
 699 }
 700
 701 static int
 702 nouveau_gpuobj_channel_init_pramin(struct nouveau_channel *chan)
 703 {
 704         struct drm_device *dev = chan->dev;
 705         struct drm_nouveau_private *dev_priv = dev->dev_private;
 706         uint32_t size;
 707         uint32_t base;
 708         int ret;
 709
 710         NV_DEBUG(dev, "ch%d\n", chan->id);
 711
 712         /* Base amount for object storage (4KiB enough?) */
 713         size = 0x2000;
 714         base = 0;
 715
 716         /* PGRAPH context */
 717         size += dev_priv->engine.graph.grctx_size;
 718
 719         if (dev_priv->card_type == NV_50) {
 720                 /* Various fixed table thingos */
 721                 size += 0x1400; /* mostly unknown stuff */
 722                 size += 0x4000; /* vm pd */
 723                 base  = 0x6000;
 724                 /* RAMHT, not sure about setting size yet, 32KiB to be safe */
 725                 size += 0x8000;
 726                 /* RAMFC */
 727                 size += 0x1000;
 728         }
 729
 730         ret = nouveau_gpuobj_new(dev, NULL, size, 0x1000, 0, &chan->ramin);
 731         if (ret) {
 732                 NV_ERROR(dev, "Error allocating channel PRAMIN: %d\n", ret);
 733                 return ret;
 734         }
 735
 736         ret = drm_mm_init(&chan->ramin_heap, base, size);
 737         if (ret) {
 738                 NV_ERROR(dev, "Error creating PRAMIN heap: %d\n", ret);
 739                 nouveau_gpuobj_ref(NULL, &chan->ramin);
 740                 return ret;
 741         }
 742
 743         return 0;
 744 }
 745
 746 int
 747 nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
 748                             uint32_t vram_h, uint32_t tt_h)
 749 {
 750         struct drm_device *dev = chan->dev;
 751         struct drm_nouveau_private *dev_priv = dev->dev_private;
 752         struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
 753         struct nouveau_gpuobj *vram = NULL, *tt = NULL;
 754         int ret, i;
 755
 756         NV_DEBUG(dev, "ch%d vram=0x%08x tt=0x%08x\n", chan->id, vram_h, tt_h);
 757
 758         /* Allocate a chunk of memory for per-channel object storage */
 759         ret = nouveau_gpuobj_channel_init_pramin(chan);
 760         if (ret) {
 761                 NV_ERROR(dev, "init pramin\n");
 762                 return ret;
 763         }
 764
 765         /* NV50 VM
 766          *  - Allocate per-channel page-directory
 767          *  - Map GART and VRAM into the channel's address space at the
 768          *    locations determined during init.
 769          */
 770         if (dev_priv->card_type >= NV_50) {
 771                 u32 pgd_offs = (dev_priv->chipset == 0x50) ? 0x1400 : 0x0200;
 772                 u64 vm_vinst = chan->ramin->vinst + pgd_offs;
 773                 u32 vm_pinst = chan->ramin->pinst;
 774                 u32 pde;
 775
 776                 if (vm_pinst != ~0)
 777                         vm_pinst += pgd_offs;
 778
 779                 ret = nouveau_gpuobj_new_fake(dev, vm_pinst, vm_vinst, 0x4000,
 780                                               0, &chan->vm_pd);
 781                 if (ret)
 782                         return ret;
 783                 for (i = 0; i < 0x4000; i += 8) {
 784                         nv_wo32(chan->vm_pd, i + 0, 0x00000000);
 785                         nv_wo32(chan->vm_pd, i + 4, 0xdeadcafe);
 786                 }
 787
 788                 nouveau_gpuobj_ref(dev_priv->gart_info.sg_ctxdma,
 789                                    &chan->vm_gart_pt);
 790                 pde = (dev_priv->vm_gart_base / (512*1024*1024)) * 8;
 791                 nv_wo32(chan->vm_pd, pde + 0, chan->vm_gart_pt->vinst | 3);
 792                 nv_wo32(chan->vm_pd, pde + 4, 0x00000000);
 793
 794                 pde = (dev_priv->vm_vram_base / (512*1024*1024)) * 8;
 795                 for (i = 0; i < dev_priv->vm_vram_pt_nr; i++) {
 796                         nouveau_gpuobj_ref(dev_priv->vm_vram_pt[i],
 797                                            &chan->vm_vram_pt[i]);
 798
 799                         nv_wo32(chan->vm_pd, pde + 0,
 800                                 chan->vm_vram_pt[i]->vinst | 0x61);
 801                         nv_wo32(chan->vm_pd, pde + 4, 0x00000000);
 802                         pde += 8;
 803                 }
 804
 805                 instmem->flush(dev);
 806         }
 807
 808         /* RAMHT */
 809         if (dev_priv->card_type < NV_50) {
 810                 nouveau_ramht_ref(dev_priv->ramht, &chan->ramht, NULL);
 811         } else {
 812                 struct nouveau_gpuobj *ramht = NULL;
 813
 814                 ret = nouveau_gpuobj_new(dev, chan, 0x8000, 16,
 815                                          NVOBJ_FLAG_ZERO_ALLOC, &ramht);
 816                 if (ret)
 817                         return ret;
 818
 819                 ret = nouveau_ramht_new(dev, ramht, &chan->ramht);
 820                 nouveau_gpuobj_ref(NULL, &ramht);
 821                 if (ret)
 822                         return ret;
 823         }
 824
 825         /* VRAM ctxdma */
 826         if (dev_priv->card_type >= NV_50) {
 827                 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
 828                                              0, dev_priv->vm_end,
 829                                              NV_DMA_ACCESS_RW,
 830                                              NV_DMA_TARGET_AGP, &vram);
 831                 if (ret) {
 832                         NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret);
 833                         return ret;
 834                 }
 835         } else {
 836                 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
 837                                              0, dev_priv->fb_available_size,
 838                                              NV_DMA_ACCESS_RW,
 839                                              NV_DMA_TARGET_VIDMEM, &vram);
 840                 if (ret) {
 841                         NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret);
 842                         return ret;
 843                 }
 844         }
 845
 846         ret = nouveau_ramht_insert(chan, vram_h, vram);
 847         nouveau_gpuobj_ref(NULL, &vram);
 848         if (ret) {
 849                 NV_ERROR(dev, "Error adding VRAM ctxdma to RAMHT: %d\n", ret);
 850                 return ret;
 851         }
 852
 853         /* TT memory ctxdma */
 854         if (dev_priv->card_type >= NV_50) {
 855                 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
 856                                              0, dev_priv->vm_end,
 857                                              NV_DMA_ACCESS_RW,
 858                                              NV_DMA_TARGET_AGP, &tt);
 859                 if (ret) {
 860                         NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret);
 861                         return ret;
 862                 }
 863         } else
 864         if (dev_priv->gart_info.type != NOUVEAU_GART_NONE) {
 865                 ret = nouveau_gpuobj_gart_dma_new(chan, 0,
 866                                                   dev_priv->gart_info.aper_size,
 867                                                   NV_DMA_ACCESS_RW, &tt, NULL);
 868         } else {
 869                 NV_ERROR(dev, "Invalid GART type %d\n", dev_priv->gart_info.type);
 870                 ret = -EINVAL;
 871         }
 872
 873         if (ret) {
 874                 NV_ERROR(dev, "Error creating TT ctxdma: %d\n", ret);
 875                 return ret;
 876         }
 877
 878         ret = nouveau_ramht_insert(chan, tt_h, tt);
 879         nouveau_gpuobj_ref(NULL, &tt);
 880         if (ret) {
 881                 NV_ERROR(dev, "Error adding TT ctxdma to RAMHT: %d\n", ret);
 882                 return ret;
 883         }
 884
 885         return 0;
 886 }
 887
 888 void
 889 nouveau_gpuobj_channel_takedown(struct nouveau_channel *chan)
 890 {
 891         struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
 892         struct drm_device *dev = chan->dev;
 893         int i;
 894
 895         NV_DEBUG(dev, "ch%d\n", chan->id);
 896
 897         if (!chan->ramht)
 898                 return;
 899
 900         nouveau_ramht_ref(NULL, &chan->ramht, chan);
 901
 902         nouveau_gpuobj_ref(NULL, &chan->vm_pd);
 903         nouveau_gpuobj_ref(NULL, &chan->vm_gart_pt);
 904         for (i = 0; i < dev_priv->vm_vram_pt_nr; i++)
 905                 nouveau_gpuobj_ref(NULL, &chan->vm_vram_pt[i]);
 906
 907         if (chan->ramin_heap.free_stack.next)
 908                 drm_mm_takedown(&chan->ramin_heap);
 909         nouveau_gpuobj_ref(NULL, &chan->ramin);
 910 }
 911
 912 int
 913 nouveau_gpuobj_suspend(struct drm_device *dev)
 914 {
 915         struct drm_nouveau_private *dev_priv = dev->dev_private;
 916         struct nouveau_gpuobj *gpuobj;
 917         int i;
 918
 919         if (dev_priv->card_type < NV_50) {
 920                 dev_priv->susres.ramin_copy = vmalloc(dev_priv->ramin_rsvd_vram);
 921                 if (!dev_priv->susres.ramin_copy)
 922                         return -ENOMEM;
 923
 924                 for (i = 0; i < dev_priv->ramin_rsvd_vram; i += 4)
 925                         dev_priv->susres.ramin_copy[i/4] = nv_ri32(dev, i);
 926                 return 0;
 927         }
 928
 929         list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) {
 930                 if (!gpuobj->im_backing)
 931                         continue;
 932
 933                 gpuobj->im_backing_suspend = vmalloc(gpuobj->size);
 934                 if (!gpuobj->im_backing_suspend) {
 935                         nouveau_gpuobj_resume(dev);
 936                         return -ENOMEM;
 937                 }
 938
 939                 for (i = 0; i < gpuobj->size; i += 4)
 940                         gpuobj->im_backing_suspend[i/4] = nv_ro32(gpuobj, i);
 941         }
 942
 943         return 0;
 944 }
 945
 946 void
 947 nouveau_gpuobj_suspend_cleanup(struct drm_device *dev)
 948 {
 949         struct drm_nouveau_private *dev_priv = dev->dev_private;
 950         struct nouveau_gpuobj *gpuobj;
 951
 952         if (dev_priv->card_type < NV_50) {
 953                 vfree(dev_priv->susres.ramin_copy);
 954                 dev_priv->susres.ramin_copy = NULL;
 955                 return;
 956         }
 957
 958         list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) {
 959                 if (!gpuobj->im_backing_suspend)
 960                         continue;
 961
 962                 vfree(gpuobj->im_backing_suspend);
 963                 gpuobj->im_backing_suspend = NULL;
 964         }
 965 }
 966
 967 void
 968 nouveau_gpuobj_resume(struct drm_device *dev)
 969 {
 970         struct drm_nouveau_private *dev_priv = dev->dev_private;
 971         struct nouveau_gpuobj *gpuobj;
 972         int i;
 973
 974         if (dev_priv->card_type < NV_50) {
 975                 for (i = 0; i < dev_priv->ramin_rsvd_vram; i += 4)
 976                         nv_wi32(dev, i, dev_priv->susres.ramin_copy[i/4]);
 977                 nouveau_gpuobj_suspend_cleanup(dev);
 978                 return;
 979         }
 980
 981         list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) {
 982                 if (!gpuobj->im_backing_suspend)
 983                         continue;
 984
 985                 for (i = 0; i < gpuobj->size; i += 4)
 986                         nv_wo32(gpuobj, i, gpuobj->im_backing_suspend[i/4]);
 987                 dev_priv->engine.instmem.flush(dev);
 988         }
 989
 990         nouveau_gpuobj_suspend_cleanup(dev);
 991 }
 992
 993 int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data,
 994                               struct drm_file *file_priv)
 995 {
 996         struct drm_nouveau_grobj_alloc *init = data;
 997         struct nouveau_gpuobj *gr = NULL;
 998         struct nouveau_channel *chan;
 999         int ret;
1000
1001         if (init->handle == ~0)
1002                 return -EINVAL;
1003
1004         chan = nouveau_channel_get(dev, file_priv, init->channel);
1005         if (IS_ERR(chan))
1006                 return PTR_ERR(chan);
1007
1008         if (nouveau_ramht_find(chan, init->handle)) {
1009                 ret = -EEXIST;
1010                 goto out;
1011         }
1012
1013         ret = nouveau_gpuobj_gr_new(chan, init->class, &gr);
1014         if (ret) {
1015                 NV_ERROR(dev, "Error creating object: %d (%d/0x%08x)\n",
1016                          ret, init->channel, init->handle);
1017                 goto out;
1018         }
1019
1020         ret = nouveau_ramht_insert(chan, init->handle, gr);
1021         nouveau_gpuobj_ref(NULL, &gr);
1022         if (ret) {
1023                 NV_ERROR(dev, "Error referencing object: %d (%d/0x%08x)\n",
1024                          ret, init->channel, init->handle);
1025         }
1026
1027 out:
1028         nouveau_channel_put(&chan);
1029         return ret;
1030 }
1031
1032 int nouveau_ioctl_gpuobj_free(struct drm_device *dev, void *data,
1033                               struct drm_file *file_priv)
1034 {
1035         struct drm_nouveau_gpuobj_free *objfree = data;
1036         struct nouveau_channel *chan;
1037         int ret;
1038
1039         chan = nouveau_channel_get(dev, file_priv, objfree->channel);
1040         if (IS_ERR(chan))
1041                 return PTR_ERR(chan);
1042
1043         ret = nouveau_ramht_remove(chan, objfree->handle);
1044         nouveau_channel_put(&chan);
1045         return ret;
1046 }
1047
1048 u32
1049 nv_ro32(struct nouveau_gpuobj *gpuobj, u32 offset)
1050 {
1051         struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private;
1052         struct drm_device *dev = gpuobj->dev;
1053
1054         if (gpuobj->pinst == ~0 || !dev_priv->ramin_available) {
1055                 u64  ptr = gpuobj->vinst + offset;
1056                 u32 base = ptr >> 16;
1057                 u32  val;
1058
1059                 spin_lock(&dev_priv->ramin_lock);
1060                 if (dev_priv->ramin_base != base) {
1061                         dev_priv->ramin_base = base;
1062                         nv_wr32(dev, 0x001700, dev_priv->ramin_base);
1063                 }
1064                 val = nv_rd32(dev, 0x700000 + (ptr & 0xffff));
1065                 spin_unlock(&dev_priv->ramin_lock);
1066                 return val;
1067         }
1068
1069         return nv_ri32(dev, gpuobj->pinst + offset);
1070 }
1071
1072 void
1073 nv_wo32(struct nouveau_gpuobj *gpuobj, u32 offset, u32 val)
1074 {
1075         struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private;
1076         struct drm_device *dev = gpuobj->dev;
1077
1078         if (gpuobj->pinst == ~0 || !dev_priv->ramin_available) {
1079                 u64  ptr = gpuobj->vinst + offset;
1080                 u32 base = ptr >> 16;
1081
1082                 spin_lock(&dev_priv->ramin_lock);
1083                 if (dev_priv->ramin_base != base) {
1084                         dev_priv->ramin_base = base;
1085                         nv_wr32(dev, 0x001700, dev_priv->ramin_base);
1086                 }
1087                 nv_wr32(dev, 0x700000 + (ptr & 0xffff), val);
1088                 spin_unlock(&dev_priv->ramin_lock);
1089                 return;
1090         }
1091
1092         nv_wi32(dev, gpuobj->pinst + offset, val);
1093 }