2 * Copyright (C) 2006 Ben Skeggs.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 * Ben Skeggs <darktama@iinet.net.au>
35 #include "nouveau_drv.h"
36 #include "nouveau_drm.h"
37 #include "nouveau_ramht.h"
38 #include "nouveau_vm.h"
39 #include "nv50_display.h"
41 struct nouveau_gpuobj_method {
42 struct list_head head;
44 int (*exec)(struct nouveau_channel *, u32 class, u32 mthd, u32 data);
47 struct nouveau_gpuobj_class {
48 struct list_head head;
49 struct list_head methods;
55 nouveau_gpuobj_class_new(struct drm_device *dev, u32 class, u32 engine)
57 struct drm_nouveau_private *dev_priv = dev->dev_private;
58 struct nouveau_gpuobj_class *oc;
60 oc = kzalloc(sizeof(*oc), GFP_KERNEL);
64 INIT_LIST_HEAD(&oc->methods);
67 list_add(&oc->head, &dev_priv->classes);
72 nouveau_gpuobj_mthd_new(struct drm_device *dev, u32 class, u32 mthd,
73 int (*exec)(struct nouveau_channel *, u32, u32, u32))
75 struct drm_nouveau_private *dev_priv = dev->dev_private;
76 struct nouveau_gpuobj_method *om;
77 struct nouveau_gpuobj_class *oc;
79 list_for_each_entry(oc, &dev_priv->classes, head) {
87 om = kzalloc(sizeof(*om), GFP_KERNEL);
93 list_add(&om->head, &oc->methods);
98 nouveau_gpuobj_mthd_call(struct nouveau_channel *chan,
99 u32 class, u32 mthd, u32 data)
101 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
102 struct nouveau_gpuobj_method *om;
103 struct nouveau_gpuobj_class *oc;
105 list_for_each_entry(oc, &dev_priv->classes, head) {
109 list_for_each_entry(om, &oc->methods, head) {
110 if (om->mthd == mthd)
111 return om->exec(chan, class, mthd, data);
119 nouveau_gpuobj_mthd_call2(struct drm_device *dev, int chid,
120 u32 class, u32 mthd, u32 data)
122 struct drm_nouveau_private *dev_priv = dev->dev_private;
123 struct nouveau_channel *chan = NULL;
127 spin_lock_irqsave(&dev_priv->channels.lock, flags);
128 if (chid > 0 && chid < dev_priv->engine.fifo.channels)
129 chan = dev_priv->channels.ptr[chid];
131 ret = nouveau_gpuobj_mthd_call(chan, class, mthd, data);
132 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
136 /* NVidia uses context objects to drive drawing operations.
138 Context objects can be selected into 8 subchannels in the FIFO,
139 and then used via DMA command buffers.
141 A context object is referenced by a user defined handle (CARD32). The HW
142 looks up graphics objects in a hash table in the instance RAM.
144 An entry in the hash table consists of 2 CARD32. The first CARD32 contains
145 the handle, the second one a bitfield, that contains the address of the
146 object in instance RAM.
148 The format of the second CARD32 seems to be:
152 15: 0 instance_addr >> 4
153 17:16 engine (here uses 1 = graphics)
154 28:24 channel id (here uses 0)
159 15: 0 instance_addr >> 4 (maybe 19-0)
160 21:20 engine (here uses 1 = graphics)
161 I'm unsure about the other bits, but using 0 seems to work.
163 The key into the hash table depends on the object handle and channel id and
168 nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan,
169 uint32_t size, int align, uint32_t flags,
170 struct nouveau_gpuobj **gpuobj_ret)
172 struct drm_nouveau_private *dev_priv = dev->dev_private;
173 struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
174 struct nouveau_gpuobj *gpuobj;
175 struct drm_mm_node *ramin = NULL;
178 NV_DEBUG(dev, "ch%d size=%u align=%d flags=0x%08x\n",
179 chan ? chan->id : -1, size, align, flags);
181 gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);
184 NV_DEBUG(dev, "gpuobj %p\n", gpuobj);
186 gpuobj->flags = flags;
187 kref_init(&gpuobj->refcount);
190 spin_lock(&dev_priv->ramin_lock);
191 list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
192 spin_unlock(&dev_priv->ramin_lock);
195 ramin = drm_mm_search_free(&chan->ramin_heap, size, align, 0);
197 ramin = drm_mm_get_block(ramin, size, align);
199 nouveau_gpuobj_ref(NULL, &gpuobj);
203 gpuobj->pinst = chan->ramin->pinst;
204 if (gpuobj->pinst != ~0)
205 gpuobj->pinst += ramin->start;
207 gpuobj->cinst = ramin->start;
208 gpuobj->vinst = ramin->start + chan->ramin->vinst;
209 gpuobj->node = ramin;
211 ret = instmem->get(gpuobj, size, align);
213 nouveau_gpuobj_ref(NULL, &gpuobj);
218 if (!(flags & NVOBJ_FLAG_DONT_MAP))
219 ret = instmem->map(gpuobj);
223 gpuobj->cinst = NVOBJ_CINST_GLOBAL;
226 if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {
227 for (i = 0; i < gpuobj->size; i += 4)
228 nv_wo32(gpuobj, i, 0);
233 *gpuobj_ret = gpuobj;
238 nouveau_gpuobj_init(struct drm_device *dev)
240 struct drm_nouveau_private *dev_priv = dev->dev_private;
244 INIT_LIST_HEAD(&dev_priv->gpuobj_list);
245 INIT_LIST_HEAD(&dev_priv->classes);
246 spin_lock_init(&dev_priv->ramin_lock);
247 dev_priv->ramin_base = ~0;
253 nouveau_gpuobj_takedown(struct drm_device *dev)
255 struct drm_nouveau_private *dev_priv = dev->dev_private;
256 struct nouveau_gpuobj_method *om, *tm;
257 struct nouveau_gpuobj_class *oc, *tc;
261 list_for_each_entry_safe(oc, tc, &dev_priv->classes, head) {
262 list_for_each_entry_safe(om, tm, &oc->methods, head) {
270 BUG_ON(!list_empty(&dev_priv->gpuobj_list));
275 nouveau_gpuobj_del(struct kref *ref)
277 struct nouveau_gpuobj *gpuobj =
278 container_of(ref, struct nouveau_gpuobj, refcount);
279 struct drm_device *dev = gpuobj->dev;
280 struct drm_nouveau_private *dev_priv = dev->dev_private;
281 struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
284 NV_DEBUG(dev, "gpuobj %p\n", gpuobj);
286 if (gpuobj->node && (gpuobj->flags & NVOBJ_FLAG_ZERO_FREE)) {
287 for (i = 0; i < gpuobj->size; i += 4)
288 nv_wo32(gpuobj, i, 0);
293 gpuobj->dtor(dev, gpuobj);
295 if (gpuobj->cinst == NVOBJ_CINST_GLOBAL) {
297 instmem->unmap(gpuobj);
298 instmem->put(gpuobj);
302 spin_lock(&dev_priv->ramin_lock);
303 drm_mm_put_block(gpuobj->node);
304 spin_unlock(&dev_priv->ramin_lock);
308 spin_lock(&dev_priv->ramin_lock);
309 list_del(&gpuobj->list);
310 spin_unlock(&dev_priv->ramin_lock);
316 nouveau_gpuobj_ref(struct nouveau_gpuobj *ref, struct nouveau_gpuobj **ptr)
319 kref_get(&ref->refcount);
322 kref_put(&(*ptr)->refcount, nouveau_gpuobj_del);
328 nouveau_gpuobj_new_fake(struct drm_device *dev, u32 pinst, u64 vinst,
329 u32 size, u32 flags, struct nouveau_gpuobj **pgpuobj)
331 struct drm_nouveau_private *dev_priv = dev->dev_private;
332 struct nouveau_gpuobj *gpuobj = NULL;
336 "pinst=0x%08x vinst=0x%010llx size=0x%08x flags=0x%08x\n",
337 pinst, vinst, size, flags);
339 gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);
342 NV_DEBUG(dev, "gpuobj %p\n", gpuobj);
344 gpuobj->flags = flags;
345 kref_init(&gpuobj->refcount);
347 gpuobj->pinst = pinst;
348 gpuobj->cinst = NVOBJ_CINST_GLOBAL;
349 gpuobj->vinst = vinst;
351 if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {
352 for (i = 0; i < gpuobj->size; i += 4)
353 nv_wo32(gpuobj, i, 0);
354 dev_priv->engine.instmem.flush(dev);
357 spin_lock(&dev_priv->ramin_lock);
358 list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
359 spin_unlock(&dev_priv->ramin_lock);
366 nouveau_gpuobj_class_instmem_size(struct drm_device *dev, int class)
368 struct drm_nouveau_private *dev_priv = dev->dev_private;
370 /*XXX: dodgy hack for now */
371 if (dev_priv->card_type >= NV_50)
373 if (dev_priv->card_type >= NV_40)
379 DMA objects are used to reference a piece of memory in the
380 framebuffer, PCI or AGP address space. Each object is 16 bytes big
381 and looks as follows:
384 11:0 class (seems like I can always use 0 here)
385 12 page table present?
386 13 page entry linear?
387 15:14 access: 0 rw, 1 ro, 2 wo
388 17:16 target: 0 NV memory, 1 NV memory tiled, 2 PCI, 3 AGP
389 31:20 dma adjust (bits 0-11 of the address)
391 dma limit (size of transfer)
393 1 0 readonly, 1 readwrite
394 31:12 dma frame address of the page (bits 12-31 of the address)
396 page table terminator, same value as the first pte, as does nvidia
397 rivatv uses 0xffffffff
399 Non linear page tables need a list of frame addresses afterwards,
400 the rivatv project has some info on this.
402 The method below creates a DMA object in instance RAM and returns a handle
403 to it that can be used to set up context objects.
407 nv50_gpuobj_dma_init(struct nouveau_gpuobj *obj, u32 offset, int class,
408 u64 base, u64 size, int target, int access,
411 struct drm_nouveau_private *dev_priv = obj->dev->dev_private;
412 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
415 flags0 = (comp << 29) | (type << 22) | class;
416 flags0 |= 0x00100000;
419 case NV_MEM_ACCESS_RO: flags0 |= 0x00040000; break;
420 case NV_MEM_ACCESS_RW:
421 case NV_MEM_ACCESS_WO: flags0 |= 0x00080000; break;
427 case NV_MEM_TARGET_VRAM:
428 flags0 |= 0x00010000;
430 case NV_MEM_TARGET_PCI:
431 flags0 |= 0x00020000;
433 case NV_MEM_TARGET_PCI_NOSNOOP:
434 flags0 |= 0x00030000;
436 case NV_MEM_TARGET_GART:
437 base += dev_priv->gart_info.aper_base;
439 flags0 &= ~0x00100000;
443 /* convert to base + limit */
444 size = (base + size) - 1;
446 nv_wo32(obj, offset + 0x00, flags0);
447 nv_wo32(obj, offset + 0x04, lower_32_bits(size));
448 nv_wo32(obj, offset + 0x08, lower_32_bits(base));
449 nv_wo32(obj, offset + 0x0c, upper_32_bits(size) << 24 |
450 upper_32_bits(base));
451 nv_wo32(obj, offset + 0x10, 0x00000000);
452 nv_wo32(obj, offset + 0x14, 0x00000000);
454 pinstmem->flush(obj->dev);
458 nv50_gpuobj_dma_new(struct nouveau_channel *chan, int class, u64 base, u64 size,
459 int target, int access, u32 type, u32 comp,
460 struct nouveau_gpuobj **pobj)
462 struct drm_device *dev = chan->dev;
465 ret = nouveau_gpuobj_new(dev, chan, 24, 16, NVOBJ_FLAG_ZERO_FREE, pobj);
469 nv50_gpuobj_dma_init(*pobj, 0, class, base, size, target,
475 nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class, u64 base,
476 u64 size, int access, int target,
477 struct nouveau_gpuobj **pobj)
479 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
480 struct drm_device *dev = chan->dev;
481 struct nouveau_gpuobj *obj;
485 if (dev_priv->card_type >= NV_50) {
486 u32 comp = (target == NV_MEM_TARGET_VM) ? NV_MEM_COMP_VM : 0;
487 u32 type = (target == NV_MEM_TARGET_VM) ? NV_MEM_TYPE_VM : 0;
489 return nv50_gpuobj_dma_new(chan, class, base, size,
490 target, access, type, comp, pobj);
493 if (target == NV_MEM_TARGET_GART) {
494 struct nouveau_gpuobj *gart = dev_priv->gart_info.sg_ctxdma;
496 if (dev_priv->gart_info.type == NOUVEAU_GART_PDMA) {
498 nouveau_gpuobj_ref(gart, pobj);
502 base = nouveau_sgdma_get_physical(dev, base);
503 target = NV_MEM_TARGET_PCI;
505 base += dev_priv->gart_info.aper_base;
506 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP)
507 target = NV_MEM_TARGET_PCI_NOSNOOP;
509 target = NV_MEM_TARGET_PCI;
514 flags0 |= 0x00003000; /* PT present, PT linear */
518 case NV_MEM_TARGET_PCI:
519 flags0 |= 0x00020000;
521 case NV_MEM_TARGET_PCI_NOSNOOP:
522 flags0 |= 0x00030000;
529 case NV_MEM_ACCESS_RO:
530 flags0 |= 0x00004000;
532 case NV_MEM_ACCESS_WO:
533 flags0 |= 0x00008000;
535 flags2 |= 0x00000002;
539 flags0 |= (base & 0x00000fff) << 20;
540 flags2 |= (base & 0xfffff000);
542 ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
546 nv_wo32(obj, 0x00, flags0);
547 nv_wo32(obj, 0x04, size - 1);
548 nv_wo32(obj, 0x08, flags2);
549 nv_wo32(obj, 0x0c, flags2);
551 obj->engine = NVOBJ_ENGINE_SW;
557 /* Context objects in the instance RAM have the following structure.
558 * On NV40 they are 32 byte long, on NV30 and smaller 16 bytes.
568 scrcopy_and, rop_and, blend_and, scrcopy, srccopy_pre, blend_pre
569 18 synchronize enable
570 19 endian: 1 big, 0 little
572 23 single step enable
573 24 patch status: 0 invalid, 1 valid
574 25 context_surface 0: 1 valid
575 26 context surface 1: 1 valid
576 27 context pattern: 1 valid
577 28 context rop: 1 valid
578 29,30 context beta, beta4
582 31:16 notify instance address
584 15:0 dma 0 instance address
585 31:16 dma 1 instance address
590 No idea what the exact format is. Here's what can be deducted:
593 11:0 class (maybe uses more bits here?)
596 25 patch status valid ?
598 15:0 DMA notifier (maybe 20:0)
600 15:0 DMA 0 instance (maybe 20:0)
603 15:0 DMA 1 instance (maybe 20:0)
609 nouveau_gpuobj_sw_new(struct nouveau_channel *chan, int class,
610 struct nouveau_gpuobj **gpuobj_ret)
612 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
613 struct nouveau_gpuobj *gpuobj;
615 gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);
618 gpuobj->dev = chan->dev;
619 gpuobj->engine = NVOBJ_ENGINE_SW;
620 gpuobj->class = class;
621 kref_init(&gpuobj->refcount);
622 gpuobj->cinst = 0x40;
624 spin_lock(&dev_priv->ramin_lock);
625 list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
626 spin_unlock(&dev_priv->ramin_lock);
627 *gpuobj_ret = gpuobj;
632 nouveau_gpuobj_gr_new(struct nouveau_channel *chan, u32 handle, int class)
634 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
635 struct drm_device *dev = chan->dev;
636 struct nouveau_gpuobj_class *oc;
637 struct nouveau_gpuobj *gpuobj;
640 NV_DEBUG(dev, "ch%d class=0x%04x\n", chan->id, class);
642 list_for_each_entry(oc, &dev_priv->classes, head) {
647 NV_ERROR(dev, "illegal object class: 0x%x\n", class);
651 switch (oc->engine) {
652 case NVOBJ_ENGINE_SW:
653 if (dev_priv->card_type < NV_C0) {
654 ret = nouveau_gpuobj_sw_new(chan, class, &gpuobj);
660 case NVOBJ_ENGINE_GR:
661 if ((dev_priv->card_type >= NV_20 && !chan->ramin_grctx) ||
662 (dev_priv->card_type < NV_20 && !chan->pgraph_ctx)) {
663 struct nouveau_pgraph_engine *pgraph =
664 &dev_priv->engine.graph;
666 ret = pgraph->create_context(chan);
671 case NVOBJ_ENGINE_CRYPT:
672 if (!chan->crypt_ctx) {
673 struct nouveau_crypt_engine *pcrypt =
674 &dev_priv->engine.crypt;
676 ret = pcrypt->create_context(chan);
683 /* we're done if this is fermi */
684 if (dev_priv->card_type >= NV_C0)
687 ret = nouveau_gpuobj_new(dev, chan,
688 nouveau_gpuobj_class_instmem_size(dev, class),
690 NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE,
693 NV_ERROR(dev, "error creating gpuobj: %d\n", ret);
697 if (dev_priv->card_type >= NV_50) {
698 nv_wo32(gpuobj, 0, class);
699 nv_wo32(gpuobj, 20, 0x00010000);
703 nv_wo32(gpuobj, 0, 0x00001030);
704 nv_wo32(gpuobj, 4, 0xFFFFFFFF);
707 if (dev_priv->card_type >= NV_40) {
708 nv_wo32(gpuobj, 0, class);
710 nv_wo32(gpuobj, 8, 0x01000000);
714 nv_wo32(gpuobj, 0, class | 0x00080000);
716 nv_wo32(gpuobj, 0, class);
721 dev_priv->engine.instmem.flush(dev);
723 gpuobj->engine = oc->engine;
724 gpuobj->class = oc->id;
727 ret = nouveau_ramht_insert(chan, handle, gpuobj);
729 NV_ERROR(dev, "error adding gpuobj to RAMHT: %d\n", ret);
730 nouveau_gpuobj_ref(NULL, &gpuobj);
735 nouveau_gpuobj_channel_init_pramin(struct nouveau_channel *chan)
737 struct drm_device *dev = chan->dev;
738 struct drm_nouveau_private *dev_priv = dev->dev_private;
743 NV_DEBUG(dev, "ch%d\n", chan->id);
745 /* Base amount for object storage (4KiB enough?) */
750 size += dev_priv->engine.graph.grctx_size;
752 if (dev_priv->card_type == NV_50) {
753 /* Various fixed table thingos */
754 size += 0x1400; /* mostly unknown stuff */
755 size += 0x4000; /* vm pd */
757 /* RAMHT, not sure about setting size yet, 32KiB to be safe */
763 ret = nouveau_gpuobj_new(dev, NULL, size, 0x1000, 0, &chan->ramin);
765 NV_ERROR(dev, "Error allocating channel PRAMIN: %d\n", ret);
769 ret = drm_mm_init(&chan->ramin_heap, base, size);
771 NV_ERROR(dev, "Error creating PRAMIN heap: %d\n", ret);
772 nouveau_gpuobj_ref(NULL, &chan->ramin);
780 nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
781 uint32_t vram_h, uint32_t tt_h)
783 struct drm_device *dev = chan->dev;
784 struct drm_nouveau_private *dev_priv = dev->dev_private;
785 struct nouveau_gpuobj *vram = NULL, *tt = NULL;
788 NV_DEBUG(dev, "ch%d vram=0x%08x tt=0x%08x\n", chan->id, vram_h, tt_h);
790 if (dev_priv->card_type == NV_C0) {
791 struct nouveau_vm *vm = dev_priv->chan_vm;
792 struct nouveau_vm_pgd *vpgd;
794 ret = nouveau_gpuobj_new(dev, NULL, 4096, 0x1000, 0,
799 nouveau_vm_ref(vm, &chan->vm, NULL);
801 vpgd = list_first_entry(&vm->pgd_list, struct nouveau_vm_pgd, head);
802 nv_wo32(chan->ramin, 0x0200, lower_32_bits(vpgd->obj->vinst));
803 nv_wo32(chan->ramin, 0x0204, upper_32_bits(vpgd->obj->vinst));
804 nv_wo32(chan->ramin, 0x0208, 0xffffffff);
805 nv_wo32(chan->ramin, 0x020c, 0x000000ff);
809 /* Allocate a chunk of memory for per-channel object storage */
810 ret = nouveau_gpuobj_channel_init_pramin(chan);
812 NV_ERROR(dev, "init pramin\n");
817 * - Allocate per-channel page-directory
818 * - Link with shared channel VM
820 if (dev_priv->chan_vm) {
821 u32 pgd_offs = (dev_priv->chipset == 0x50) ? 0x1400 : 0x0200;
822 u64 vm_vinst = chan->ramin->vinst + pgd_offs;
823 u32 vm_pinst = chan->ramin->pinst;
826 vm_pinst += pgd_offs;
828 ret = nouveau_gpuobj_new_fake(dev, vm_pinst, vm_vinst, 0x4000,
833 nouveau_vm_ref(dev_priv->chan_vm, &chan->vm, chan->vm_pd);
837 if (dev_priv->card_type < NV_50) {
838 nouveau_ramht_ref(dev_priv->ramht, &chan->ramht, NULL);
840 struct nouveau_gpuobj *ramht = NULL;
842 ret = nouveau_gpuobj_new(dev, chan, 0x8000, 16,
843 NVOBJ_FLAG_ZERO_ALLOC, &ramht);
847 ret = nouveau_ramht_new(dev, ramht, &chan->ramht);
848 nouveau_gpuobj_ref(NULL, &ramht);
852 /* dma objects for display sync channel semaphore blocks */
853 for (i = 0; i < 2; i++) {
854 struct nouveau_gpuobj *sem = NULL;
855 struct nv50_display_crtc *dispc =
856 &nv50_display(dev)->crtc[i];
857 u64 offset = dispc->sem.bo->bo.mem.start << PAGE_SHIFT;
859 ret = nouveau_gpuobj_dma_new(chan, 0x3d, offset, 0xfff,
861 NV_MEM_TARGET_VRAM, &sem);
865 ret = nouveau_ramht_insert(chan, NvEvoSema0 + i, sem);
866 nouveau_gpuobj_ref(NULL, &sem);
873 if (dev_priv->card_type >= NV_50) {
874 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
875 0, (1ULL << 40), NV_MEM_ACCESS_RW,
876 NV_MEM_TARGET_VM, &vram);
878 NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret);
882 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
883 0, dev_priv->fb_available_size,
885 NV_MEM_TARGET_VRAM, &vram);
887 NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret);
892 ret = nouveau_ramht_insert(chan, vram_h, vram);
893 nouveau_gpuobj_ref(NULL, &vram);
895 NV_ERROR(dev, "Error adding VRAM ctxdma to RAMHT: %d\n", ret);
899 /* TT memory ctxdma */
900 if (dev_priv->card_type >= NV_50) {
901 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
902 0, (1ULL << 40), NV_MEM_ACCESS_RW,
903 NV_MEM_TARGET_VM, &tt);
905 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
906 0, dev_priv->gart_info.aper_size,
908 NV_MEM_TARGET_GART, &tt);
912 NV_ERROR(dev, "Error creating TT ctxdma: %d\n", ret);
916 ret = nouveau_ramht_insert(chan, tt_h, tt);
917 nouveau_gpuobj_ref(NULL, &tt);
919 NV_ERROR(dev, "Error adding TT ctxdma to RAMHT: %d\n", ret);
927 nouveau_gpuobj_channel_takedown(struct nouveau_channel *chan)
929 struct drm_device *dev = chan->dev;
931 NV_DEBUG(dev, "ch%d\n", chan->id);
933 nouveau_ramht_ref(NULL, &chan->ramht, chan);
935 nouveau_vm_ref(NULL, &chan->vm, chan->vm_pd);
936 nouveau_gpuobj_ref(NULL, &chan->vm_pd);
938 if (drm_mm_initialized(&chan->ramin_heap))
939 drm_mm_takedown(&chan->ramin_heap);
940 nouveau_gpuobj_ref(NULL, &chan->ramin);
944 nouveau_gpuobj_suspend(struct drm_device *dev)
946 struct drm_nouveau_private *dev_priv = dev->dev_private;
947 struct nouveau_gpuobj *gpuobj;
950 list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) {
951 if (gpuobj->cinst != NVOBJ_CINST_GLOBAL)
954 gpuobj->suspend = vmalloc(gpuobj->size);
955 if (!gpuobj->suspend) {
956 nouveau_gpuobj_resume(dev);
960 for (i = 0; i < gpuobj->size; i += 4)
961 gpuobj->suspend[i/4] = nv_ro32(gpuobj, i);
968 nouveau_gpuobj_resume(struct drm_device *dev)
970 struct drm_nouveau_private *dev_priv = dev->dev_private;
971 struct nouveau_gpuobj *gpuobj;
974 list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) {
975 if (!gpuobj->suspend)
978 for (i = 0; i < gpuobj->size; i += 4)
979 nv_wo32(gpuobj, i, gpuobj->suspend[i/4]);
981 vfree(gpuobj->suspend);
982 gpuobj->suspend = NULL;
985 dev_priv->engine.instmem.flush(dev);
988 int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data,
989 struct drm_file *file_priv)
991 struct drm_nouveau_grobj_alloc *init = data;
992 struct nouveau_channel *chan;
995 if (init->handle == ~0)
998 chan = nouveau_channel_get(dev, file_priv, init->channel);
1000 return PTR_ERR(chan);
1002 if (nouveau_ramht_find(chan, init->handle)) {
1007 ret = nouveau_gpuobj_gr_new(chan, init->handle, init->class);
1009 NV_ERROR(dev, "Error creating object: %d (%d/0x%08x)\n",
1010 ret, init->channel, init->handle);
1014 nouveau_channel_put(&chan);
1018 int nouveau_ioctl_gpuobj_free(struct drm_device *dev, void *data,
1019 struct drm_file *file_priv)
1021 struct drm_nouveau_gpuobj_free *objfree = data;
1022 struct nouveau_channel *chan;
1025 chan = nouveau_channel_get(dev, file_priv, objfree->channel);
1027 return PTR_ERR(chan);
1029 /* Synchronize with the user channel */
1030 nouveau_channel_idle(chan);
1032 ret = nouveau_ramht_remove(chan, objfree->handle);
1033 nouveau_channel_put(&chan);
1038 nv_ro32(struct nouveau_gpuobj *gpuobj, u32 offset)
1040 struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private;
1041 struct drm_device *dev = gpuobj->dev;
1042 unsigned long flags;
1044 if (gpuobj->pinst == ~0 || !dev_priv->ramin_available) {
1045 u64 ptr = gpuobj->vinst + offset;
1046 u32 base = ptr >> 16;
1049 spin_lock_irqsave(&dev_priv->vm_lock, flags);
1050 if (dev_priv->ramin_base != base) {
1051 dev_priv->ramin_base = base;
1052 nv_wr32(dev, 0x001700, dev_priv->ramin_base);
1054 val = nv_rd32(dev, 0x700000 + (ptr & 0xffff));
1055 spin_unlock_irqrestore(&dev_priv->vm_lock, flags);
1059 return nv_ri32(dev, gpuobj->pinst + offset);
1063 nv_wo32(struct nouveau_gpuobj *gpuobj, u32 offset, u32 val)
1065 struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private;
1066 struct drm_device *dev = gpuobj->dev;
1067 unsigned long flags;
1069 if (gpuobj->pinst == ~0 || !dev_priv->ramin_available) {
1070 u64 ptr = gpuobj->vinst + offset;
1071 u32 base = ptr >> 16;
1073 spin_lock_irqsave(&dev_priv->vm_lock, flags);
1074 if (dev_priv->ramin_base != base) {
1075 dev_priv->ramin_base = base;
1076 nv_wr32(dev, 0x001700, dev_priv->ramin_base);
1078 nv_wr32(dev, 0x700000 + (ptr & 0xffff), val);
1079 spin_unlock_irqrestore(&dev_priv->vm_lock, flags);
1083 nv_wi32(dev, gpuobj->pinst + offset, val);