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27 #include "nouveau_drv.h"
28 #include "nouveau_pm.h"
31 legacy_perf_init(struct drm_device *dev)
33 struct drm_nouveau_private *dev_priv = dev->dev_private;
34 struct nvbios *bios = &dev_priv->vbios;
35 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
36 char *perf, *entry, *bmp = &bios->data[bios->offset];
37 int headerlen, use_straps;
39 if (bmp[5] < 0x5 || bmp[6] < 0x14) {
40 NV_DEBUG(dev, "BMP version too old for perf\n");
44 perf = ROMPTR(bios, bmp[0x73]);
46 NV_DEBUG(dev, "No memclock table pointer found.\n");
58 use_straps = perf[1] & 1;
59 headerlen = (use_straps ? 8 : 2);
62 NV_WARN(dev, "Unknown memclock table version %x.\n", perf[0]);
66 entry = perf + headerlen;
68 entry += (nv_rd32(dev, NV_PEXTDEV_BOOT_0) & 0x3c) >> 1;
70 sprintf(pm->perflvl[0].name, "performance_level_0");
71 pm->perflvl[0].memory = ROM16(entry[0]) * 20;
75 static struct nouveau_pm_memtiming *
76 nouveau_perf_timing(struct drm_device *dev, struct bit_entry *P,
77 u16 memclk, u8 *entry, u8 recordlen, u8 entries)
79 struct drm_nouveau_private *dev_priv = dev->dev_private;
80 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
81 struct nvbios *bios = &dev_priv->vbios;
85 /* perf v2 has a separate "timing map" table, we have to match
86 * the target memory clock to a specific entry, *then* use
87 * ramcfg to select the correct subentry
89 if (P->version == 2) {
90 u8 *tmap = ROMPTR(bios, P->data[4]);
92 NV_DEBUG(dev, "no timing map pointer\n");
96 if (tmap[0] != 0x10) {
97 NV_WARN(dev, "timing map 0x%02x unknown\n", tmap[0]);
101 entry = tmap + tmap[1];
102 recordlen = tmap[2] + (tmap[4] * tmap[3]);
103 for (i = 0; i < tmap[5]; i++, entry += recordlen) {
104 if (memclk >= ROM16(entry[0]) &&
105 memclk <= ROM16(entry[2]))
110 NV_WARN(dev, "no match in timing map table\n");
119 ramcfg = (nv_rd32(dev, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
120 if (bios->ram_restrict_tbl_ptr)
121 ramcfg = bios->data[bios->ram_restrict_tbl_ptr + ramcfg];
123 if (ramcfg >= entries) {
124 NV_WARN(dev, "ramcfg strap out of bounds!\n");
128 entry += ramcfg * recordlen;
129 if (entry[1] >= pm->memtimings.nr_timing) {
130 NV_WARN(dev, "timingset %d does not exist\n", entry[1]);
134 return &pm->memtimings.timing[entry[1]];
138 nouveau_perf_init(struct drm_device *dev)
140 struct drm_nouveau_private *dev_priv = dev->dev_private;
141 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
142 struct nvbios *bios = &dev_priv->vbios;
144 u8 version, headerlen, recordlen, entries;
148 if (bios->type == NVBIOS_BIT) {
149 if (bit_table(dev, 'P', &P))
152 if (P.version != 1 && P.version != 2) {
153 NV_WARN(dev, "unknown perf for BIT P %d\n", P.version);
157 perf = ROMPTR(bios, P.data[0]);
160 if (version < 0x40) {
161 recordlen = perf[3] + (perf[4] * perf[5]);
164 recordlen = perf[2] + (perf[3] * perf[4]);
168 if (bios->data[bios->offset + 6] < 0x25) {
169 legacy_perf_init(dev);
173 perf = ROMPTR(bios, bios->data[bios->offset + 0x94]);
175 NV_DEBUG(dev, "perf table pointer invalid\n");
185 entry = perf + headerlen;
186 for (i = 0; i < entries; i++) {
187 struct nouveau_pm_level *perflvl = &pm->perflvl[pm->nr_perflvl];
189 perflvl->timing = NULL;
191 if (entry[0] == 0xff) {
200 perflvl->fanspeed = entry[55];
201 perflvl->voltage = (recordlen > 56) ? entry[56] : 0;
202 perflvl->core = ROM32(entry[1]) * 10;
203 perflvl->memory = ROM32(entry[5]) * 20;
208 perflvl->fanspeed = entry[4];
209 perflvl->voltage = entry[5];
210 perflvl->core = ROM16(entry[6]) * 1000;
212 if (dev_priv->chipset == 0x49 ||
213 dev_priv->chipset == 0x4b)
214 perflvl->memory = ROM16(entry[11]) * 1000;
216 perflvl->memory = ROM16(entry[11]) * 2000;
220 perflvl->fanspeed = entry[4];
221 perflvl->voltage = entry[5];
222 perflvl->core = ROM16(entry[6]) * 1000;
223 perflvl->shader = ROM16(entry[10]) * 1000;
224 perflvl->memory = ROM16(entry[12]) * 1000;
227 perflvl->memscript = ROM16(entry[2]);
229 perflvl->fanspeed = entry[6];
230 perflvl->voltage = entry[7];
231 perflvl->core = ROM16(entry[8]) * 1000;
232 perflvl->shader = ROM16(entry[10]) * 1000;
233 perflvl->memory = ROM16(entry[12]) * 1000;
234 /*XXX: confirm on 0x35 */
235 perflvl->unk05 = ROM16(entry[16]) * 1000;
238 #define subent(n) entry[perf[2] + ((n) * perf[3])]
239 perflvl->fanspeed = 0; /*XXX*/
240 perflvl->voltage = entry[2];
241 if (dev_priv->card_type == NV_50) {
242 perflvl->core = ROM16(subent(0)) & 0xfff;
243 perflvl->shader = ROM16(subent(1)) & 0xfff;
244 perflvl->memory = ROM16(subent(2)) & 0xfff;
246 perflvl->shader = ROM16(subent(3)) & 0xfff;
247 perflvl->core = perflvl->shader / 2;
248 perflvl->unk0a = ROM16(subent(4)) & 0xfff;
249 perflvl->memory = ROM16(subent(5)) & 0xfff;
252 perflvl->core *= 1000;
253 perflvl->shader *= 1000;
254 perflvl->memory *= 1000;
255 perflvl->unk0a *= 1000;
259 /* make sure vid is valid */
260 if (pm->voltage.supported && perflvl->voltage) {
261 vid = nouveau_volt_vid_lookup(dev, perflvl->voltage);
263 NV_DEBUG(dev, "drop perflvl %d, bad vid\n", i);
269 /* get the corresponding memory timings */
270 if (version > 0x15) {
271 /* last 3 args are for < 0x40, ignored for >= 0x40 */
273 nouveau_perf_timing(dev, &P,
274 perflvl->memory / 1000,
279 snprintf(perflvl->name, sizeof(perflvl->name),
280 "performance_level_%d", i);
289 nouveau_perf_fini(struct drm_device *dev)