2 * Copyright 2010 Red Hat Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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27 #include "nouveau_drv.h"
28 #include "nouveau_ramht.h"
31 nouveau_ramht_hash_handle(struct drm_device *dev, int channel, uint32_t handle)
33 struct drm_nouveau_private *dev_priv = dev->dev_private;
37 NV_DEBUG(dev, "ch%d handle=0x%08x\n", channel, handle);
39 for (i = 32; i > 0; i -= dev_priv->ramht_bits) {
40 hash ^= (handle & ((1 << dev_priv->ramht_bits) - 1));
41 handle >>= dev_priv->ramht_bits;
44 if (dev_priv->card_type < NV_50)
45 hash ^= channel << (dev_priv->ramht_bits - 4);
48 NV_DEBUG(dev, "hash=0x%08x\n", hash);
53 nouveau_ramht_entry_valid(struct drm_device *dev, struct nouveau_gpuobj *ramht,
56 struct drm_nouveau_private *dev_priv = dev->dev_private;
57 uint32_t ctx = nv_ro32(dev, ramht, (offset + 4)/4);
59 if (dev_priv->card_type < NV_40)
60 return ((ctx & NV_RAMHT_CONTEXT_VALID) != 0);
65 nouveau_ramht_insert(struct drm_device *dev, struct nouveau_gpuobj_ref *ref)
67 struct drm_nouveau_private *dev_priv = dev->dev_private;
68 struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
69 struct nouveau_channel *chan = ref->channel;
70 struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL;
74 NV_ERROR(dev, "No hash table!\n");
78 if (dev_priv->card_type < NV_40) {
79 ctx = NV_RAMHT_CONTEXT_VALID | (ref->instance >> 4) |
80 (chan->id << NV_RAMHT_CONTEXT_CHANNEL_SHIFT) |
81 (ref->gpuobj->engine << NV_RAMHT_CONTEXT_ENGINE_SHIFT);
83 if (dev_priv->card_type < NV_50) {
84 ctx = (ref->instance >> 4) |
85 (chan->id << NV40_RAMHT_CONTEXT_CHANNEL_SHIFT) |
86 (ref->gpuobj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT);
88 if (ref->gpuobj->engine == NVOBJ_ENGINE_DISPLAY) {
89 ctx = (ref->instance << 10) | 2;
91 ctx = (ref->instance >> 4) |
92 ((ref->gpuobj->engine <<
93 NV40_RAMHT_CONTEXT_ENGINE_SHIFT));
97 co = ho = nouveau_ramht_hash_handle(dev, chan->id, ref->handle);
99 if (!nouveau_ramht_entry_valid(dev, ramht, co)) {
101 "insert ch%d 0x%08x: h=0x%08x, c=0x%08x\n",
102 chan->id, co, ref->handle, ctx);
103 nv_wo32(dev, ramht, (co + 0)/4, ref->handle);
104 nv_wo32(dev, ramht, (co + 4)/4, ctx);
106 list_add_tail(&ref->list, &chan->ramht_refs);
110 NV_DEBUG(dev, "collision ch%d 0x%08x: h=0x%08x\n",
111 chan->id, co, nv_ro32(dev, ramht, co/4));
114 if (co >= dev_priv->ramht_size)
118 NV_ERROR(dev, "RAMHT space exhausted. ch=%d\n", chan->id);
123 nouveau_ramht_remove(struct drm_device *dev, struct nouveau_gpuobj_ref *ref)
125 struct drm_nouveau_private *dev_priv = dev->dev_private;
126 struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
127 struct nouveau_channel *chan = ref->channel;
128 struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL;
132 NV_ERROR(dev, "No hash table!\n");
136 co = ho = nouveau_ramht_hash_handle(dev, chan->id, ref->handle);
138 if (nouveau_ramht_entry_valid(dev, ramht, co) &&
139 (ref->handle == nv_ro32(dev, ramht, (co/4)))) {
141 "remove ch%d 0x%08x: h=0x%08x, c=0x%08x\n",
142 chan->id, co, ref->handle,
143 nv_ro32(dev, ramht, (co + 4)));
144 nv_wo32(dev, ramht, (co + 0)/4, 0x00000000);
145 nv_wo32(dev, ramht, (co + 4)/4, 0x00000000);
147 list_del(&ref->list);
153 if (co >= dev_priv->ramht_size)
156 list_del(&ref->list);
158 NV_ERROR(dev, "RAMHT entry not found. ch=%d, handle=0x%08x\n",
159 chan->id, ref->handle);