2 #include "nouveau_drv.h"
3 #include <linux/pagemap.h>
4 #include <linux/slab.h>
6 #define NV_CTXDMA_PAGE_SHIFT 12
7 #define NV_CTXDMA_PAGE_SIZE (1 << NV_CTXDMA_PAGE_SHIFT)
8 #define NV_CTXDMA_PAGE_MASK (NV_CTXDMA_PAGE_SIZE - 1)
10 struct nouveau_sgdma_be {
11 struct ttm_backend backend;
12 struct drm_device *dev;
22 nouveau_sgdma_populate(struct ttm_backend *be, unsigned long num_pages,
23 struct page **pages, struct page *dummy_read_page)
25 struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
26 struct drm_device *dev = nvbe->dev;
28 NV_DEBUG(nvbe->dev, "num_pages = %ld\n", num_pages);
33 nvbe->pages = kmalloc(sizeof(dma_addr_t) * num_pages, GFP_KERNEL);
39 nvbe->pages[nvbe->nr_pages] =
40 pci_map_page(dev->pdev, pages[nvbe->nr_pages], 0,
41 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
42 if (pci_dma_mapping_error(dev->pdev,
43 nvbe->pages[nvbe->nr_pages])) {
55 nouveau_sgdma_clear(struct ttm_backend *be)
57 struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
58 struct drm_device *dev;
60 if (nvbe && nvbe->pages) {
67 while (nvbe->nr_pages--) {
68 pci_unmap_page(dev->pdev, nvbe->pages[nvbe->nr_pages],
69 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
77 static inline unsigned
78 nouveau_sgdma_pte(struct drm_device *dev, uint64_t offset)
80 struct drm_nouveau_private *dev_priv = dev->dev_private;
81 unsigned pte = (offset >> NV_CTXDMA_PAGE_SHIFT);
83 if (dev_priv->card_type < NV_50)
90 nouveau_sgdma_bind(struct ttm_backend *be, struct ttm_mem_reg *mem)
92 struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
93 struct drm_device *dev = nvbe->dev;
94 struct drm_nouveau_private *dev_priv = dev->dev_private;
95 struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma;
98 NV_DEBUG(dev, "pg=0x%lx\n", mem->mm_node->start);
100 pte = nouveau_sgdma_pte(nvbe->dev, mem->mm_node->start << PAGE_SHIFT);
101 nvbe->pte_start = pte;
102 for (i = 0; i < nvbe->nr_pages; i++) {
103 dma_addr_t dma_offset = nvbe->pages[i];
104 uint32_t offset_l = lower_32_bits(dma_offset);
105 uint32_t offset_h = upper_32_bits(dma_offset);
107 for (j = 0; j < PAGE_SIZE / NV_CTXDMA_PAGE_SIZE; j++) {
108 if (dev_priv->card_type < NV_50)
109 nv_wo32(dev, gpuobj, pte++, offset_l | 3);
111 nv_wo32(dev, gpuobj, pte++, offset_l | 0x21);
112 nv_wo32(dev, gpuobj, pte++, offset_h & 0xff);
115 dma_offset += NV_CTXDMA_PAGE_SIZE;
118 dev_priv->engine.instmem.flush(nvbe->dev);
120 if (dev_priv->card_type == NV_50) {
121 nv50_vm_flush(dev, 5); /* PGRAPH */
122 nv50_vm_flush(dev, 0); /* PFIFO */
130 nouveau_sgdma_unbind(struct ttm_backend *be)
132 struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
133 struct drm_device *dev = nvbe->dev;
134 struct drm_nouveau_private *dev_priv = dev->dev_private;
135 struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma;
143 pte = nvbe->pte_start;
144 for (i = 0; i < nvbe->nr_pages; i++) {
145 dma_addr_t dma_offset = dev_priv->gart_info.sg_dummy_bus;
147 for (j = 0; j < PAGE_SIZE / NV_CTXDMA_PAGE_SIZE; j++) {
148 if (dev_priv->card_type < NV_50)
149 nv_wo32(dev, gpuobj, pte++, dma_offset | 3);
151 nv_wo32(dev, gpuobj, pte++, dma_offset | 0x21);
152 nv_wo32(dev, gpuobj, pte++, 0x00000000);
155 dma_offset += NV_CTXDMA_PAGE_SIZE;
158 dev_priv->engine.instmem.flush(nvbe->dev);
160 if (dev_priv->card_type == NV_50) {
161 nv50_vm_flush(dev, 5);
162 nv50_vm_flush(dev, 0);
170 nouveau_sgdma_destroy(struct ttm_backend *be)
172 struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
175 NV_DEBUG(nvbe->dev, "\n");
185 static struct ttm_backend_func nouveau_sgdma_backend = {
186 .populate = nouveau_sgdma_populate,
187 .clear = nouveau_sgdma_clear,
188 .bind = nouveau_sgdma_bind,
189 .unbind = nouveau_sgdma_unbind,
190 .destroy = nouveau_sgdma_destroy
194 nouveau_sgdma_init_ttm(struct drm_device *dev)
196 struct drm_nouveau_private *dev_priv = dev->dev_private;
197 struct nouveau_sgdma_be *nvbe;
199 if (!dev_priv->gart_info.sg_ctxdma)
202 nvbe = kzalloc(sizeof(*nvbe), GFP_KERNEL);
208 nvbe->backend.func = &nouveau_sgdma_backend;
210 return &nvbe->backend;
214 nouveau_sgdma_init(struct drm_device *dev)
216 struct drm_nouveau_private *dev_priv = dev->dev_private;
217 struct pci_dev *pdev = dev->pdev;
218 struct nouveau_gpuobj *gpuobj = NULL;
219 uint32_t aper_size, obj_size;
222 if (dev_priv->card_type < NV_50) {
223 aper_size = (64 * 1024 * 1024);
224 obj_size = (aper_size >> NV_CTXDMA_PAGE_SHIFT) * 4;
225 obj_size += 8; /* ctxdma header */
227 /* 1 entire VM page table */
228 aper_size = (512 * 1024 * 1024);
229 obj_size = (aper_size >> NV_CTXDMA_PAGE_SHIFT) * 8;
232 ret = nouveau_gpuobj_new(dev, NULL, obj_size, 16,
233 NVOBJ_FLAG_ALLOW_NO_REFS |
234 NVOBJ_FLAG_ZERO_ALLOC |
235 NVOBJ_FLAG_ZERO_FREE, &gpuobj);
237 NV_ERROR(dev, "Error creating sgdma object: %d\n", ret);
241 dev_priv->gart_info.sg_dummy_page =
242 alloc_page(GFP_KERNEL|__GFP_DMA32);
243 if (!dev_priv->gart_info.sg_dummy_page) {
244 nouveau_gpuobj_del(dev, &gpuobj);
248 set_bit(PG_locked, &dev_priv->gart_info.sg_dummy_page->flags);
249 dev_priv->gart_info.sg_dummy_bus =
250 pci_map_page(pdev, dev_priv->gart_info.sg_dummy_page, 0,
251 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
252 if (pci_dma_mapping_error(pdev, dev_priv->gart_info.sg_dummy_bus)) {
253 nouveau_gpuobj_del(dev, &gpuobj);
257 if (dev_priv->card_type < NV_50) {
258 /* Maybe use NV_DMA_TARGET_AGP for PCIE? NVIDIA do this, and
259 * confirmed to work on c51. Perhaps means NV_DMA_TARGET_PCIE
261 nv_wo32(dev, gpuobj, 0, NV_CLASS_DMA_IN_MEMORY |
262 (1 << 12) /* PT present */ |
263 (0 << 13) /* PT *not* linear */ |
264 (NV_DMA_ACCESS_RW << 14) |
265 (NV_DMA_TARGET_PCI << 16));
266 nv_wo32(dev, gpuobj, 1, aper_size - 1);
267 for (i = 2; i < 2 + (aper_size >> 12); i++) {
268 nv_wo32(dev, gpuobj, i,
269 dev_priv->gart_info.sg_dummy_bus | 3);
272 for (i = 0; i < obj_size; i += 8) {
273 nv_wo32(dev, gpuobj, (i+0)/4,
274 dev_priv->gart_info.sg_dummy_bus | 0x21);
275 nv_wo32(dev, gpuobj, (i+4)/4, 0);
278 dev_priv->engine.instmem.flush(dev);
280 dev_priv->gart_info.type = NOUVEAU_GART_SGDMA;
281 dev_priv->gart_info.aper_base = 0;
282 dev_priv->gart_info.aper_size = aper_size;
283 dev_priv->gart_info.sg_ctxdma = gpuobj;
288 nouveau_sgdma_takedown(struct drm_device *dev)
290 struct drm_nouveau_private *dev_priv = dev->dev_private;
292 if (dev_priv->gart_info.sg_dummy_page) {
293 pci_unmap_page(dev->pdev, dev_priv->gart_info.sg_dummy_bus,
294 NV_CTXDMA_PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
295 unlock_page(dev_priv->gart_info.sg_dummy_page);
296 __free_page(dev_priv->gart_info.sg_dummy_page);
297 dev_priv->gart_info.sg_dummy_page = NULL;
298 dev_priv->gart_info.sg_dummy_bus = 0;
301 nouveau_gpuobj_del(dev, &dev_priv->gart_info.sg_ctxdma);
305 nouveau_sgdma_get_page(struct drm_device *dev, uint32_t offset, uint32_t *page)
307 struct drm_nouveau_private *dev_priv = dev->dev_private;
308 struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma;
311 pte = (offset >> NV_CTXDMA_PAGE_SHIFT);
312 if (dev_priv->card_type < NV_50) {
313 *page = nv_ro32(dev, gpuobj, (pte + 2)) & ~NV_CTXDMA_PAGE_MASK;
317 NV_ERROR(dev, "Unimplemented on NV50\n");