drivers/gpu/drm/nouveau/nouveau_state.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin
   3  * Copyright 2008 Stuart Bennett
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include <linux/swab.h>
  27 #include <linux/slab.h>
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "drm_sarea.h"
  31 #include "drm_crtc_helper.h"
  32 #include <linux/vgaarb.h>
  33 #include <linux/vga_switcheroo.h>
  34
  35 #include "nouveau_drv.h"
  36 #include "nouveau_drm.h"
  37 #include "nouveau_fbcon.h"
  38 #include "nouveau_ramht.h"
  39 #include "nouveau_pm.h"
  40 #include "nv50_display.h"
  41
  42 static void nouveau_stub_takedown(struct drm_device *dev) {}
  43 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
  44
  45 static int nouveau_init_engine_ptrs(struct drm_device *dev)
  46 {
  47         struct drm_nouveau_private *dev_priv = dev->dev_private;
  48         struct nouveau_engine *engine = &dev_priv->engine;
  49
  50         switch (dev_priv->chipset & 0xf0) {
  51         case 0x00:
  52                 engine->instmem.init            = nv04_instmem_init;
  53                 engine->instmem.takedown        = nv04_instmem_takedown;
  54                 engine->instmem.suspend         = nv04_instmem_suspend;
  55                 engine->instmem.resume          = nv04_instmem_resume;
  56                 engine->instmem.populate        = nv04_instmem_populate;
  57                 engine->instmem.clear           = nv04_instmem_clear;
  58                 engine->instmem.bind            = nv04_instmem_bind;
  59                 engine->instmem.unbind          = nv04_instmem_unbind;
  60                 engine->instmem.flush           = nv04_instmem_flush;
  61                 engine->mc.init                 = nv04_mc_init;
  62                 engine->mc.takedown             = nv04_mc_takedown;
  63                 engine->timer.init              = nv04_timer_init;
  64                 engine->timer.read              = nv04_timer_read;
  65                 engine->timer.takedown          = nv04_timer_takedown;
  66                 engine->fb.init                 = nv04_fb_init;
  67                 engine->fb.takedown             = nv04_fb_takedown;
  68                 engine->graph.grclass           = nv04_graph_grclass;
  69                 engine->graph.init              = nv04_graph_init;
  70                 engine->graph.takedown          = nv04_graph_takedown;
  71                 engine->graph.fifo_access       = nv04_graph_fifo_access;
  72                 engine->graph.channel           = nv04_graph_channel;
  73                 engine->graph.create_context    = nv04_graph_create_context;
  74                 engine->graph.destroy_context   = nv04_graph_destroy_context;
  75                 engine->graph.load_context      = nv04_graph_load_context;
  76                 engine->graph.unload_context    = nv04_graph_unload_context;
  77                 engine->fifo.channels           = 16;
  78                 engine->fifo.init               = nv04_fifo_init;
  79                 engine->fifo.takedown           = nouveau_stub_takedown;
  80                 engine->fifo.disable            = nv04_fifo_disable;
  81                 engine->fifo.enable             = nv04_fifo_enable;
  82                 engine->fifo.reassign           = nv04_fifo_reassign;
  83                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
  84                 engine->fifo.channel_id         = nv04_fifo_channel_id;
  85                 engine->fifo.create_context     = nv04_fifo_create_context;
  86                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
  87                 engine->fifo.load_context       = nv04_fifo_load_context;
  88                 engine->fifo.unload_context     = nv04_fifo_unload_context;
  89                 engine->display.early_init      = nv04_display_early_init;
  90                 engine->display.late_takedown   = nv04_display_late_takedown;
  91                 engine->display.create          = nv04_display_create;
  92                 engine->display.init            = nv04_display_init;
  93                 engine->display.destroy         = nv04_display_destroy;
  94                 engine->gpio.init               = nouveau_stub_init;
  95                 engine->gpio.takedown           = nouveau_stub_takedown;
  96                 engine->gpio.get                = NULL;
  97                 engine->gpio.set                = NULL;
  98                 engine->gpio.irq_enable         = NULL;
  99                 engine->pm.clock_get            = nv04_pm_clock_get;
 100                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 101                 engine->pm.clock_set            = nv04_pm_clock_set;
 102                 break;
 103         case 0x10:
 104                 engine->instmem.init            = nv04_instmem_init;
 105                 engine->instmem.takedown        = nv04_instmem_takedown;
 106                 engine->instmem.suspend         = nv04_instmem_suspend;
 107                 engine->instmem.resume          = nv04_instmem_resume;
 108                 engine->instmem.populate        = nv04_instmem_populate;
 109                 engine->instmem.clear           = nv04_instmem_clear;
 110                 engine->instmem.bind            = nv04_instmem_bind;
 111                 engine->instmem.unbind          = nv04_instmem_unbind;
 112                 engine->instmem.flush           = nv04_instmem_flush;
 113                 engine->mc.init                 = nv04_mc_init;
 114                 engine->mc.takedown             = nv04_mc_takedown;
 115                 engine->timer.init              = nv04_timer_init;
 116                 engine->timer.read              = nv04_timer_read;
 117                 engine->timer.takedown          = nv04_timer_takedown;
 118                 engine->fb.init                 = nv10_fb_init;
 119                 engine->fb.takedown             = nv10_fb_takedown;
 120                 engine->fb.set_region_tiling    = nv10_fb_set_region_tiling;
 121                 engine->graph.grclass           = nv10_graph_grclass;
 122                 engine->graph.init              = nv10_graph_init;
 123                 engine->graph.takedown          = nv10_graph_takedown;
 124                 engine->graph.channel           = nv10_graph_channel;
 125                 engine->graph.create_context    = nv10_graph_create_context;
 126                 engine->graph.destroy_context   = nv10_graph_destroy_context;
 127                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 128                 engine->graph.load_context      = nv10_graph_load_context;
 129                 engine->graph.unload_context    = nv10_graph_unload_context;
 130                 engine->graph.set_region_tiling = nv10_graph_set_region_tiling;
 131                 engine->fifo.channels           = 32;
 132                 engine->fifo.init               = nv10_fifo_init;
 133                 engine->fifo.takedown           = nouveau_stub_takedown;
 134                 engine->fifo.disable            = nv04_fifo_disable;
 135                 engine->fifo.enable             = nv04_fifo_enable;
 136                 engine->fifo.reassign           = nv04_fifo_reassign;
 137                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 138                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 139                 engine->fifo.create_context     = nv10_fifo_create_context;
 140                 engine->fifo.destroy_context    = nv10_fifo_destroy_context;
 141                 engine->fifo.load_context       = nv10_fifo_load_context;
 142                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 143                 engine->display.early_init      = nv04_display_early_init;
 144                 engine->display.late_takedown   = nv04_display_late_takedown;
 145                 engine->display.create          = nv04_display_create;
 146                 engine->display.init            = nv04_display_init;
 147                 engine->display.destroy         = nv04_display_destroy;
 148                 engine->gpio.init               = nouveau_stub_init;
 149                 engine->gpio.takedown           = nouveau_stub_takedown;
 150                 engine->gpio.get                = nv10_gpio_get;
 151                 engine->gpio.set                = nv10_gpio_set;
 152                 engine->gpio.irq_enable         = NULL;
 153                 engine->pm.clock_get            = nv04_pm_clock_get;
 154                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 155                 engine->pm.clock_set            = nv04_pm_clock_set;
 156                 break;
 157         case 0x20:
 158                 engine->instmem.init            = nv04_instmem_init;
 159                 engine->instmem.takedown        = nv04_instmem_takedown;
 160                 engine->instmem.suspend         = nv04_instmem_suspend;
 161                 engine->instmem.resume          = nv04_instmem_resume;
 162                 engine->instmem.populate        = nv04_instmem_populate;
 163                 engine->instmem.clear           = nv04_instmem_clear;
 164                 engine->instmem.bind            = nv04_instmem_bind;
 165                 engine->instmem.unbind          = nv04_instmem_unbind;
 166                 engine->instmem.flush           = nv04_instmem_flush;
 167                 engine->mc.init                 = nv04_mc_init;
 168                 engine->mc.takedown             = nv04_mc_takedown;
 169                 engine->timer.init              = nv04_timer_init;
 170                 engine->timer.read              = nv04_timer_read;
 171                 engine->timer.takedown          = nv04_timer_takedown;
 172                 engine->fb.init                 = nv10_fb_init;
 173                 engine->fb.takedown             = nv10_fb_takedown;
 174                 engine->fb.set_region_tiling    = nv10_fb_set_region_tiling;
 175                 engine->graph.grclass           = nv20_graph_grclass;
 176                 engine->graph.init              = nv20_graph_init;
 177                 engine->graph.takedown          = nv20_graph_takedown;
 178                 engine->graph.channel           = nv10_graph_channel;
 179                 engine->graph.create_context    = nv20_graph_create_context;
 180                 engine->graph.destroy_context   = nv20_graph_destroy_context;
 181                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 182                 engine->graph.load_context      = nv20_graph_load_context;
 183                 engine->graph.unload_context    = nv20_graph_unload_context;
 184                 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
 185                 engine->fifo.channels           = 32;
 186                 engine->fifo.init               = nv10_fifo_init;
 187                 engine->fifo.takedown           = nouveau_stub_takedown;
 188                 engine->fifo.disable            = nv04_fifo_disable;
 189                 engine->fifo.enable             = nv04_fifo_enable;
 190                 engine->fifo.reassign           = nv04_fifo_reassign;
 191                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 192                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 193                 engine->fifo.create_context     = nv10_fifo_create_context;
 194                 engine->fifo.destroy_context    = nv10_fifo_destroy_context;
 195                 engine->fifo.load_context       = nv10_fifo_load_context;
 196                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 197                 engine->display.early_init      = nv04_display_early_init;
 198                 engine->display.late_takedown   = nv04_display_late_takedown;
 199                 engine->display.create          = nv04_display_create;
 200                 engine->display.init            = nv04_display_init;
 201                 engine->display.destroy         = nv04_display_destroy;
 202                 engine->gpio.init               = nouveau_stub_init;
 203                 engine->gpio.takedown           = nouveau_stub_takedown;
 204                 engine->gpio.get                = nv10_gpio_get;
 205                 engine->gpio.set                = nv10_gpio_set;
 206                 engine->gpio.irq_enable         = NULL;
 207                 engine->pm.clock_get            = nv04_pm_clock_get;
 208                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 209                 engine->pm.clock_set            = nv04_pm_clock_set;
 210                 break;
 211         case 0x30:
 212                 engine->instmem.init            = nv04_instmem_init;
 213                 engine->instmem.takedown        = nv04_instmem_takedown;
 214                 engine->instmem.suspend         = nv04_instmem_suspend;
 215                 engine->instmem.resume          = nv04_instmem_resume;
 216                 engine->instmem.populate        = nv04_instmem_populate;
 217                 engine->instmem.clear           = nv04_instmem_clear;
 218                 engine->instmem.bind            = nv04_instmem_bind;
 219                 engine->instmem.unbind          = nv04_instmem_unbind;
 220                 engine->instmem.flush           = nv04_instmem_flush;
 221                 engine->mc.init                 = nv04_mc_init;
 222                 engine->mc.takedown             = nv04_mc_takedown;
 223                 engine->timer.init              = nv04_timer_init;
 224                 engine->timer.read              = nv04_timer_read;
 225                 engine->timer.takedown          = nv04_timer_takedown;
 226                 engine->fb.init                 = nv30_fb_init;
 227                 engine->fb.takedown             = nv30_fb_takedown;
 228                 engine->fb.set_region_tiling    = nv10_fb_set_region_tiling;
 229                 engine->graph.grclass           = nv30_graph_grclass;
 230                 engine->graph.init              = nv30_graph_init;
 231                 engine->graph.takedown          = nv20_graph_takedown;
 232                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 233                 engine->graph.channel           = nv10_graph_channel;
 234                 engine->graph.create_context    = nv20_graph_create_context;
 235                 engine->graph.destroy_context   = nv20_graph_destroy_context;
 236                 engine->graph.load_context      = nv20_graph_load_context;
 237                 engine->graph.unload_context    = nv20_graph_unload_context;
 238                 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
 239                 engine->fifo.channels           = 32;
 240                 engine->fifo.init               = nv10_fifo_init;
 241                 engine->fifo.takedown           = nouveau_stub_takedown;
 242                 engine->fifo.disable            = nv04_fifo_disable;
 243                 engine->fifo.enable             = nv04_fifo_enable;
 244                 engine->fifo.reassign           = nv04_fifo_reassign;
 245                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 246                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 247                 engine->fifo.create_context     = nv10_fifo_create_context;
 248                 engine->fifo.destroy_context    = nv10_fifo_destroy_context;
 249                 engine->fifo.load_context       = nv10_fifo_load_context;
 250                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 251                 engine->display.early_init      = nv04_display_early_init;
 252                 engine->display.late_takedown   = nv04_display_late_takedown;
 253                 engine->display.create          = nv04_display_create;
 254                 engine->display.init            = nv04_display_init;
 255                 engine->display.destroy         = nv04_display_destroy;
 256                 engine->gpio.init               = nouveau_stub_init;
 257                 engine->gpio.takedown           = nouveau_stub_takedown;
 258                 engine->gpio.get                = nv10_gpio_get;
 259                 engine->gpio.set                = nv10_gpio_set;
 260                 engine->gpio.irq_enable         = NULL;
 261                 engine->pm.clock_get            = nv04_pm_clock_get;
 262                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 263                 engine->pm.clock_set            = nv04_pm_clock_set;
 264                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 265                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 266                 break;
 267         case 0x40:
 268         case 0x60:
 269                 engine->instmem.init            = nv04_instmem_init;
 270                 engine->instmem.takedown        = nv04_instmem_takedown;
 271                 engine->instmem.suspend         = nv04_instmem_suspend;
 272                 engine->instmem.resume          = nv04_instmem_resume;
 273                 engine->instmem.populate        = nv04_instmem_populate;
 274                 engine->instmem.clear           = nv04_instmem_clear;
 275                 engine->instmem.bind            = nv04_instmem_bind;
 276                 engine->instmem.unbind          = nv04_instmem_unbind;
 277                 engine->instmem.flush           = nv04_instmem_flush;
 278                 engine->mc.init                 = nv40_mc_init;
 279                 engine->mc.takedown             = nv40_mc_takedown;
 280                 engine->timer.init              = nv04_timer_init;
 281                 engine->timer.read              = nv04_timer_read;
 282                 engine->timer.takedown          = nv04_timer_takedown;
 283                 engine->fb.init                 = nv40_fb_init;
 284                 engine->fb.takedown             = nv40_fb_takedown;
 285                 engine->fb.set_region_tiling    = nv40_fb_set_region_tiling;
 286                 engine->graph.grclass           = nv40_graph_grclass;
 287                 engine->graph.init              = nv40_graph_init;
 288                 engine->graph.takedown          = nv40_graph_takedown;
 289                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 290                 engine->graph.channel           = nv40_graph_channel;
 291                 engine->graph.create_context    = nv40_graph_create_context;
 292                 engine->graph.destroy_context   = nv40_graph_destroy_context;
 293                 engine->graph.load_context      = nv40_graph_load_context;
 294                 engine->graph.unload_context    = nv40_graph_unload_context;
 295                 engine->graph.set_region_tiling = nv40_graph_set_region_tiling;
 296                 engine->fifo.channels           = 32;
 297                 engine->fifo.init               = nv40_fifo_init;
 298                 engine->fifo.takedown           = nouveau_stub_takedown;
 299                 engine->fifo.disable            = nv04_fifo_disable;
 300                 engine->fifo.enable             = nv04_fifo_enable;
 301                 engine->fifo.reassign           = nv04_fifo_reassign;
 302                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 303                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 304                 engine->fifo.create_context     = nv40_fifo_create_context;
 305                 engine->fifo.destroy_context    = nv40_fifo_destroy_context;
 306                 engine->fifo.load_context       = nv40_fifo_load_context;
 307                 engine->fifo.unload_context     = nv40_fifo_unload_context;
 308                 engine->display.early_init      = nv04_display_early_init;
 309                 engine->display.late_takedown   = nv04_display_late_takedown;
 310                 engine->display.create          = nv04_display_create;
 311                 engine->display.init            = nv04_display_init;
 312                 engine->display.destroy         = nv04_display_destroy;
 313                 engine->gpio.init               = nouveau_stub_init;
 314                 engine->gpio.takedown           = nouveau_stub_takedown;
 315                 engine->gpio.get                = nv10_gpio_get;
 316                 engine->gpio.set                = nv10_gpio_set;
 317                 engine->gpio.irq_enable         = NULL;
 318                 engine->pm.clock_get            = nv04_pm_clock_get;
 319                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 320                 engine->pm.clock_set            = nv04_pm_clock_set;
 321                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 322                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 323                 engine->pm.temp_get             = nv40_temp_get;
 324                 break;
 325         case 0x50:
 326         case 0x80: /* gotta love NVIDIA's consistency.. */
 327         case 0x90:
 328         case 0xA0:
 329                 engine->instmem.init            = nv50_instmem_init;
 330                 engine->instmem.takedown        = nv50_instmem_takedown;
 331                 engine->instmem.suspend         = nv50_instmem_suspend;
 332                 engine->instmem.resume          = nv50_instmem_resume;
 333                 engine->instmem.populate        = nv50_instmem_populate;
 334                 engine->instmem.clear           = nv50_instmem_clear;
 335                 engine->instmem.bind            = nv50_instmem_bind;
 336                 engine->instmem.unbind          = nv50_instmem_unbind;
 337                 if (dev_priv->chipset == 0x50)
 338                         engine->instmem.flush   = nv50_instmem_flush;
 339                 else
 340                         engine->instmem.flush   = nv84_instmem_flush;
 341                 engine->mc.init                 = nv50_mc_init;
 342                 engine->mc.takedown             = nv50_mc_takedown;
 343                 engine->timer.init              = nv04_timer_init;
 344                 engine->timer.read              = nv04_timer_read;
 345                 engine->timer.takedown          = nv04_timer_takedown;
 346                 engine->fb.init                 = nv50_fb_init;
 347                 engine->fb.takedown             = nv50_fb_takedown;
 348                 engine->graph.grclass           = nv50_graph_grclass;
 349                 engine->graph.init              = nv50_graph_init;
 350                 engine->graph.takedown          = nv50_graph_takedown;
 351                 engine->graph.fifo_access       = nv50_graph_fifo_access;
 352                 engine->graph.channel           = nv50_graph_channel;
 353                 engine->graph.create_context    = nv50_graph_create_context;
 354                 engine->graph.destroy_context   = nv50_graph_destroy_context;
 355                 engine->graph.load_context      = nv50_graph_load_context;
 356                 engine->graph.unload_context    = nv50_graph_unload_context;
 357                 if (dev_priv->chipset != 0x86)
 358                         engine->graph.tlb_flush = nv50_graph_tlb_flush;
 359                 else {
 360                         /* from what i can see nvidia do this on every
 361                          * pre-NVA3 board except NVAC, but, we've only
 362                          * ever seen problems on NV86
 363                          */
 364                         engine->graph.tlb_flush = nv86_graph_tlb_flush;
 365                 }
 366                 engine->fifo.channels           = 128;
 367                 engine->fifo.init               = nv50_fifo_init;
 368                 engine->fifo.takedown           = nv50_fifo_takedown;
 369                 engine->fifo.disable            = nv04_fifo_disable;
 370                 engine->fifo.enable             = nv04_fifo_enable;
 371                 engine->fifo.reassign           = nv04_fifo_reassign;
 372                 engine->fifo.channel_id         = nv50_fifo_channel_id;
 373                 engine->fifo.create_context     = nv50_fifo_create_context;
 374                 engine->fifo.destroy_context    = nv50_fifo_destroy_context;
 375                 engine->fifo.load_context       = nv50_fifo_load_context;
 376                 engine->fifo.unload_context     = nv50_fifo_unload_context;
 377                 engine->fifo.tlb_flush          = nv50_fifo_tlb_flush;
 378                 engine->display.early_init      = nv50_display_early_init;
 379                 engine->display.late_takedown   = nv50_display_late_takedown;
 380                 engine->display.create          = nv50_display_create;
 381                 engine->display.init            = nv50_display_init;
 382                 engine->display.destroy         = nv50_display_destroy;
 383                 engine->gpio.init               = nv50_gpio_init;
 384                 engine->gpio.takedown           = nouveau_stub_takedown;
 385                 engine->gpio.get                = nv50_gpio_get;
 386                 engine->gpio.set                = nv50_gpio_set;
 387                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 388                 switch (dev_priv->chipset) {
 389                 case 0xa3:
 390                 case 0xa5:
 391                 case 0xa8:
 392                 case 0xaf:
 393                         engine->pm.clock_get    = nva3_pm_clock_get;
 394                         engine->pm.clock_pre    = nva3_pm_clock_pre;
 395                         engine->pm.clock_set    = nva3_pm_clock_set;
 396                         break;
 397                 default:
 398                         engine->pm.clock_get    = nv50_pm_clock_get;
 399                         engine->pm.clock_pre    = nv50_pm_clock_pre;
 400                         engine->pm.clock_set    = nv50_pm_clock_set;
 401                         break;
 402                 }
 403                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 404                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 405                 if (dev_priv->chipset >= 0x84)
 406                         engine->pm.temp_get     = nv84_temp_get;
 407                 else
 408                         engine->pm.temp_get     = nv40_temp_get;
 409                 break;
 410         case 0xC0:
 411                 engine->instmem.init            = nvc0_instmem_init;
 412                 engine->instmem.takedown        = nvc0_instmem_takedown;
 413                 engine->instmem.suspend         = nvc0_instmem_suspend;
 414                 engine->instmem.resume          = nvc0_instmem_resume;
 415                 engine->instmem.populate        = nvc0_instmem_populate;
 416                 engine->instmem.clear           = nvc0_instmem_clear;
 417                 engine->instmem.bind            = nvc0_instmem_bind;
 418                 engine->instmem.unbind          = nvc0_instmem_unbind;
 419                 engine->instmem.flush           = nvc0_instmem_flush;
 420                 engine->mc.init                 = nv50_mc_init;
 421                 engine->mc.takedown             = nv50_mc_takedown;
 422                 engine->timer.init              = nv04_timer_init;
 423                 engine->timer.read              = nv04_timer_read;
 424                 engine->timer.takedown          = nv04_timer_takedown;
 425                 engine->fb.init                 = nvc0_fb_init;
 426                 engine->fb.takedown             = nvc0_fb_takedown;
 427                 engine->graph.grclass           = NULL;  //nvc0_graph_grclass;
 428                 engine->graph.init              = nvc0_graph_init;
 429                 engine->graph.takedown          = nvc0_graph_takedown;
 430                 engine->graph.fifo_access       = nvc0_graph_fifo_access;
 431                 engine->graph.channel           = nvc0_graph_channel;
 432                 engine->graph.create_context    = nvc0_graph_create_context;
 433                 engine->graph.destroy_context   = nvc0_graph_destroy_context;
 434                 engine->graph.load_context      = nvc0_graph_load_context;
 435                 engine->graph.unload_context    = nvc0_graph_unload_context;
 436                 engine->fifo.channels           = 128;
 437                 engine->fifo.init               = nvc0_fifo_init;
 438                 engine->fifo.takedown           = nvc0_fifo_takedown;
 439                 engine->fifo.disable            = nvc0_fifo_disable;
 440                 engine->fifo.enable             = nvc0_fifo_enable;
 441                 engine->fifo.reassign           = nvc0_fifo_reassign;
 442                 engine->fifo.channel_id         = nvc0_fifo_channel_id;
 443                 engine->fifo.create_context     = nvc0_fifo_create_context;
 444                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
 445                 engine->fifo.load_context       = nvc0_fifo_load_context;
 446                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
 447                 engine->display.early_init      = nv50_display_early_init;
 448                 engine->display.late_takedown   = nv50_display_late_takedown;
 449                 engine->display.create          = nv50_display_create;
 450                 engine->display.init            = nv50_display_init;
 451                 engine->display.destroy         = nv50_display_destroy;
 452                 engine->gpio.init               = nv50_gpio_init;
 453                 engine->gpio.takedown           = nouveau_stub_takedown;
 454                 engine->gpio.get                = nv50_gpio_get;
 455                 engine->gpio.set                = nv50_gpio_set;
 456                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 457                 break;
 458         default:
 459                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
 460                 return 1;
 461         }
 462
 463         return 0;
 464 }
 465
 466 static unsigned int
 467 nouveau_vga_set_decode(void *priv, bool state)
 468 {
 469         struct drm_device *dev = priv;
 470         struct drm_nouveau_private *dev_priv = dev->dev_private;
 471
 472         if (dev_priv->chipset >= 0x40)
 473                 nv_wr32(dev, 0x88054, state);
 474         else
 475                 nv_wr32(dev, 0x1854, state);
 476
 477         if (state)
 478                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 479                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 480         else
 481                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 482 }
 483
 484 static int
 485 nouveau_card_init_channel(struct drm_device *dev)
 486 {
 487         struct drm_nouveau_private *dev_priv = dev->dev_private;
 488         struct nouveau_gpuobj *gpuobj = NULL;
 489         int ret;
 490
 491         ret = nouveau_channel_alloc(dev, &dev_priv->channel,
 492                                     (struct drm_file *)-2, NvDmaFB, NvDmaTT);
 493         if (ret)
 494                 return ret;
 495
 496         ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
 497                                      0, dev_priv->vram_size,
 498                                      NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
 499                                      &gpuobj);
 500         if (ret)
 501                 goto out_err;
 502
 503         ret = nouveau_ramht_insert(dev_priv->channel, NvDmaVRAM, gpuobj);
 504         nouveau_gpuobj_ref(NULL, &gpuobj);
 505         if (ret)
 506                 goto out_err;
 507
 508         ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0,
 509                                           dev_priv->gart_info.aper_size,
 510                                           NV_DMA_ACCESS_RW, &gpuobj, NULL);
 511         if (ret)
 512                 goto out_err;
 513
 514         ret = nouveau_ramht_insert(dev_priv->channel, NvDmaGART, gpuobj);
 515         nouveau_gpuobj_ref(NULL, &gpuobj);
 516         if (ret)
 517                 goto out_err;
 518
 519         return 0;
 520
 521 out_err:
 522         nouveau_channel_free(dev_priv->channel);
 523         dev_priv->channel = NULL;
 524         return ret;
 525 }
 526
 527 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
 528                                          enum vga_switcheroo_state state)
 529 {
 530         struct drm_device *dev = pci_get_drvdata(pdev);
 531         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 532         if (state == VGA_SWITCHEROO_ON) {
 533                 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
 534                 nouveau_pci_resume(pdev);
 535                 drm_kms_helper_poll_enable(dev);
 536         } else {
 537                 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
 538                 drm_kms_helper_poll_disable(dev);
 539                 nouveau_pci_suspend(pdev, pmm);
 540         }
 541 }
 542
 543 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
 544 {
 545         struct drm_device *dev = pci_get_drvdata(pdev);
 546         bool can_switch;
 547
 548         spin_lock(&dev->count_lock);
 549         can_switch = (dev->open_count == 0);
 550         spin_unlock(&dev->count_lock);
 551         return can_switch;
 552 }
 553
 554 int
 555 nouveau_card_init(struct drm_device *dev)
 556 {
 557         struct drm_nouveau_private *dev_priv = dev->dev_private;
 558         struct nouveau_engine *engine;
 559         int ret;
 560
 561         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
 562         vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
 563                                        nouveau_switcheroo_can_switch);
 564
 565         /* Initialise internal driver API hooks */
 566         ret = nouveau_init_engine_ptrs(dev);
 567         if (ret)
 568                 goto out;
 569         engine = &dev_priv->engine;
 570         spin_lock_init(&dev_priv->context_switch_lock);
 571
 572         /* Make the CRTCs and I2C buses accessible */
 573         ret = engine->display.early_init(dev);
 574         if (ret)
 575                 goto out;
 576
 577         /* Parse BIOS tables / Run init tables if card not POSTed */
 578         ret = nouveau_bios_init(dev);
 579         if (ret)
 580                 goto out_display_early;
 581
 582         nouveau_pm_init(dev);
 583
 584         ret = nouveau_mem_vram_init(dev);
 585         if (ret)
 586                 goto out_bios;
 587
 588         ret = nouveau_gpuobj_init(dev);
 589         if (ret)
 590                 goto out_vram;
 591
 592         ret = engine->instmem.init(dev);
 593         if (ret)
 594                 goto out_gpuobj;
 595
 596         ret = nouveau_mem_gart_init(dev);
 597         if (ret)
 598                 goto out_instmem;
 599
 600         /* PMC */
 601         ret = engine->mc.init(dev);
 602         if (ret)
 603                 goto out_gart;
 604
 605         /* PGPIO */
 606         ret = engine->gpio.init(dev);
 607         if (ret)
 608                 goto out_mc;
 609
 610         /* PTIMER */
 611         ret = engine->timer.init(dev);
 612         if (ret)
 613                 goto out_gpio;
 614
 615         /* PFB */
 616         ret = engine->fb.init(dev);
 617         if (ret)
 618                 goto out_timer;
 619
 620         if (nouveau_noaccel)
 621                 engine->graph.accel_blocked = true;
 622         else {
 623                 /* PGRAPH */
 624                 ret = engine->graph.init(dev);
 625                 if (ret)
 626                         goto out_fb;
 627
 628                 /* PFIFO */
 629                 ret = engine->fifo.init(dev);
 630                 if (ret)
 631                         goto out_graph;
 632         }
 633
 634         ret = engine->display.create(dev);
 635         if (ret)
 636                 goto out_fifo;
 637
 638         /* this call irq_preinstall, register irq handler and
 639          * call irq_postinstall
 640          */
 641         ret = drm_irq_install(dev);
 642         if (ret)
 643                 goto out_display;
 644
 645         ret = drm_vblank_init(dev, 0);
 646         if (ret)
 647                 goto out_irq;
 648
 649         /* what about PVIDEO/PCRTC/PRAMDAC etc? */
 650
 651         if (!engine->graph.accel_blocked) {
 652                 ret = nouveau_fence_init(dev);
 653                 if (ret)
 654                         goto out_irq;
 655
 656                 ret = nouveau_card_init_channel(dev);
 657                 if (ret)
 658                         goto out_fence;
 659         }
 660
 661         ret = nouveau_backlight_init(dev);
 662         if (ret)
 663                 NV_ERROR(dev, "Error %d registering backlight\n", ret);
 664
 665         nouveau_fbcon_init(dev);
 666         drm_kms_helper_poll_init(dev);
 667         return 0;
 668
 669 out_fence:
 670         nouveau_fence_fini(dev);
 671 out_irq:
 672         drm_irq_uninstall(dev);
 673 out_display:
 674         engine->display.destroy(dev);
 675 out_fifo:
 676         if (!nouveau_noaccel)
 677                 engine->fifo.takedown(dev);
 678 out_graph:
 679         if (!nouveau_noaccel)
 680                 engine->graph.takedown(dev);
 681 out_fb:
 682         engine->fb.takedown(dev);
 683 out_timer:
 684         engine->timer.takedown(dev);
 685 out_gpio:
 686         engine->gpio.takedown(dev);
 687 out_mc:
 688         engine->mc.takedown(dev);
 689 out_gart:
 690         nouveau_mem_gart_fini(dev);
 691 out_instmem:
 692         engine->instmem.takedown(dev);
 693 out_gpuobj:
 694         nouveau_gpuobj_takedown(dev);
 695 out_vram:
 696         nouveau_mem_vram_fini(dev);
 697 out_bios:
 698         nouveau_pm_fini(dev);
 699         nouveau_bios_takedown(dev);
 700 out_display_early:
 701         engine->display.late_takedown(dev);
 702 out:
 703         vga_client_register(dev->pdev, NULL, NULL, NULL);
 704         return ret;
 705 }
 706
 707 static void nouveau_card_takedown(struct drm_device *dev)
 708 {
 709         struct drm_nouveau_private *dev_priv = dev->dev_private;
 710         struct nouveau_engine *engine = &dev_priv->engine;
 711
 712         nouveau_backlight_exit(dev);
 713
 714         if (!engine->graph.accel_blocked) {
 715                 nouveau_fence_fini(dev);
 716                 nouveau_channel_free(dev_priv->channel);
 717                 dev_priv->channel = NULL;
 718         }
 719
 720         if (!nouveau_noaccel) {
 721                 engine->fifo.takedown(dev);
 722                 engine->graph.takedown(dev);
 723         }
 724         engine->fb.takedown(dev);
 725         engine->timer.takedown(dev);
 726         engine->gpio.takedown(dev);
 727         engine->mc.takedown(dev);
 728         engine->display.late_takedown(dev);
 729
 730         mutex_lock(&dev->struct_mutex);
 731         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
 732         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
 733         mutex_unlock(&dev->struct_mutex);
 734         nouveau_mem_gart_fini(dev);
 735
 736         engine->instmem.takedown(dev);
 737         nouveau_gpuobj_takedown(dev);
 738         nouveau_mem_vram_fini(dev);
 739
 740         drm_irq_uninstall(dev);
 741
 742         nouveau_pm_fini(dev);
 743         nouveau_bios_takedown(dev);
 744
 745         vga_client_register(dev->pdev, NULL, NULL, NULL);
 746 }
 747
 748 /* here a client dies, release the stuff that was allocated for its
 749  * file_priv */
 750 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
 751 {
 752         nouveau_channel_cleanup(dev, file_priv);
 753 }
 754
 755 /* first module load, setup the mmio/fb mapping */
 756 /* KMS: we need mmio at load time, not when the first drm client opens. */
 757 int nouveau_firstopen(struct drm_device *dev)
 758 {
 759         return 0;
 760 }
 761
 762 /* if we have an OF card, copy vbios to RAMIN */
 763 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
 764 {
 765 #if defined(__powerpc__)
 766         int size, i;
 767         const uint32_t *bios;
 768         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
 769         if (!dn) {
 770                 NV_INFO(dev, "Unable to get the OF node\n");
 771                 return;
 772         }
 773
 774         bios = of_get_property(dn, "NVDA,BMP", &size);
 775         if (bios) {
 776                 for (i = 0; i < size; i += 4)
 777                         nv_wi32(dev, i, bios[i/4]);
 778                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
 779         } else {
 780                 NV_INFO(dev, "Unable to get the OF bios\n");
 781         }
 782 #endif
 783 }
 784
 785 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
 786 {
 787         struct pci_dev *pdev = dev->pdev;
 788         struct apertures_struct *aper = alloc_apertures(3);
 789         if (!aper)
 790                 return NULL;
 791
 792         aper->ranges[0].base = pci_resource_start(pdev, 1);
 793         aper->ranges[0].size = pci_resource_len(pdev, 1);
 794         aper->count = 1;
 795
 796         if (pci_resource_len(pdev, 2)) {
 797                 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
 798                 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
 799                 aper->count++;
 800         }
 801
 802         if (pci_resource_len(pdev, 3)) {
 803                 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
 804                 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
 805                 aper->count++;
 806         }
 807
 808         return aper;
 809 }
 810
 811 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
 812 {
 813         struct drm_nouveau_private *dev_priv = dev->dev_private;
 814         bool primary = false;
 815         dev_priv->apertures = nouveau_get_apertures(dev);
 816         if (!dev_priv->apertures)
 817                 return -ENOMEM;
 818
 819 #ifdef CONFIG_X86
 820         primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 821 #endif
 822
 823         remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
 824         return 0;
 825 }
 826
 827 int nouveau_load(struct drm_device *dev, unsigned long flags)
 828 {
 829         struct drm_nouveau_private *dev_priv;
 830         uint32_t reg0;
 831         resource_size_t mmio_start_offs;
 832         int ret;
 833
 834         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 835         if (!dev_priv) {
 836                 ret = -ENOMEM;
 837                 goto err_out;
 838         }
 839         dev->dev_private = dev_priv;
 840         dev_priv->dev = dev;
 841
 842         dev_priv->flags = flags & NOUVEAU_FLAGS;
 843
 844         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
 845                  dev->pci_vendor, dev->pci_device, dev->pdev->class);
 846
 847         dev_priv->wq = create_workqueue("nouveau");
 848         if (!dev_priv->wq) {
 849                 ret = -EINVAL;
 850                 goto err_priv;
 851         }
 852
 853         /* resource 0 is mmio regs */
 854         /* resource 1 is linear FB */
 855         /* resource 2 is RAMIN (mmio regs + 0x1000000) */
 856         /* resource 6 is bios */
 857
 858         /* map the mmio regs */
 859         mmio_start_offs = pci_resource_start(dev->pdev, 0);
 860         dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
 861         if (!dev_priv->mmio) {
 862                 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
 863                          "Please report your setup to " DRIVER_EMAIL "\n");
 864                 ret = -EINVAL;
 865                 goto err_wq;
 866         }
 867         NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
 868                                         (unsigned long long)mmio_start_offs);
 869
 870 #ifdef __BIG_ENDIAN
 871         /* Put the card in BE mode if it's not */
 872         if (nv_rd32(dev, NV03_PMC_BOOT_1))
 873                 nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
 874
 875         DRM_MEMORYBARRIER();
 876 #endif
 877
 878         /* Time to determine the card architecture */
 879         reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
 880
 881         /* We're dealing with >=NV10 */
 882         if ((reg0 & 0x0f000000) > 0) {
 883                 /* Bit 27-20 contain the architecture in hex */
 884                 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
 885         /* NV04 or NV05 */
 886         } else if ((reg0 & 0xff00fff0) == 0x20004000) {
 887                 if (reg0 & 0x00f00000)
 888                         dev_priv->chipset = 0x05;
 889                 else
 890                         dev_priv->chipset = 0x04;
 891         } else
 892                 dev_priv->chipset = 0xff;
 893
 894         switch (dev_priv->chipset & 0xf0) {
 895         case 0x00:
 896         case 0x10:
 897         case 0x20:
 898         case 0x30:
 899                 dev_priv->card_type = dev_priv->chipset & 0xf0;
 900                 break;
 901         case 0x40:
 902         case 0x60:
 903                 dev_priv->card_type = NV_40;
 904                 break;
 905         case 0x50:
 906         case 0x80:
 907         case 0x90:
 908         case 0xa0:
 909                 dev_priv->card_type = NV_50;
 910                 break;
 911         case 0xc0:
 912                 dev_priv->card_type = NV_C0;
 913                 break;
 914         default:
 915                 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
 916                 ret = -EINVAL;
 917                 goto err_mmio;
 918         }
 919
 920         NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
 921                 dev_priv->card_type, reg0);
 922
 923         ret = nouveau_remove_conflicting_drivers(dev);
 924         if (ret)
 925                 goto err_mmio;
 926
 927         /* Map PRAMIN BAR, or on older cards, the aperture withing BAR0 */
 928         if (dev_priv->card_type >= NV_40) {
 929                 int ramin_bar = 2;
 930                 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
 931                         ramin_bar = 3;
 932
 933                 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
 934                 dev_priv->ramin =
 935                         ioremap(pci_resource_start(dev->pdev, ramin_bar),
 936                                 dev_priv->ramin_size);
 937                 if (!dev_priv->ramin) {
 938                         NV_ERROR(dev, "Failed to PRAMIN BAR");
 939                         ret = -ENOMEM;
 940                         goto err_mmio;
 941                 }
 942         } else {
 943                 dev_priv->ramin_size = 1 * 1024 * 1024;
 944                 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
 945                                           dev_priv->ramin_size);
 946                 if (!dev_priv->ramin) {
 947                         NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
 948                         ret = -ENOMEM;
 949                         goto err_mmio;
 950                 }
 951         }
 952
 953         nouveau_OF_copy_vbios_to_ramin(dev);
 954
 955         /* Special flags */
 956         if (dev->pci_device == 0x01a0)
 957                 dev_priv->flags |= NV_NFORCE;
 958         else if (dev->pci_device == 0x01f0)
 959                 dev_priv->flags |= NV_NFORCE2;
 960
 961         /* For kernel modesetting, init card now and bring up fbcon */
 962         ret = nouveau_card_init(dev);
 963         if (ret)
 964                 goto err_ramin;
 965
 966         return 0;
 967
 968 err_ramin:
 969         iounmap(dev_priv->ramin);
 970 err_mmio:
 971         iounmap(dev_priv->mmio);
 972 err_wq:
 973         destroy_workqueue(dev_priv->wq);
 974 err_priv:
 975         kfree(dev_priv);
 976         dev->dev_private = NULL;
 977 err_out:
 978         return ret;
 979 }
 980
 981 void nouveau_lastclose(struct drm_device *dev)
 982 {
 983 }
 984
 985 int nouveau_unload(struct drm_device *dev)
 986 {
 987         struct drm_nouveau_private *dev_priv = dev->dev_private;
 988         struct nouveau_engine *engine = &dev_priv->engine;
 989
 990         drm_kms_helper_poll_fini(dev);
 991         nouveau_fbcon_fini(dev);
 992         engine->display.destroy(dev);
 993         nouveau_card_takedown(dev);
 994
 995         iounmap(dev_priv->mmio);
 996         iounmap(dev_priv->ramin);
 997
 998         kfree(dev_priv);
 999         dev->dev_private = NULL;
1000         return 0;
1001 }
1002
1003 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
1004                                                 struct drm_file *file_priv)
1005 {
1006         struct drm_nouveau_private *dev_priv = dev->dev_private;
1007         struct drm_nouveau_getparam *getparam = data;
1008
1009         switch (getparam->param) {
1010         case NOUVEAU_GETPARAM_CHIPSET_ID:
1011                 getparam->value = dev_priv->chipset;
1012                 break;
1013         case NOUVEAU_GETPARAM_PCI_VENDOR:
1014                 getparam->value = dev->pci_vendor;
1015                 break;
1016         case NOUVEAU_GETPARAM_PCI_DEVICE:
1017                 getparam->value = dev->pci_device;
1018                 break;
1019         case NOUVEAU_GETPARAM_BUS_TYPE:
1020                 if (drm_device_is_agp(dev))
1021                         getparam->value = NV_AGP;
1022                 else if (drm_device_is_pcie(dev))
1023                         getparam->value = NV_PCIE;
1024                 else
1025                         getparam->value = NV_PCI;
1026                 break;
1027         case NOUVEAU_GETPARAM_FB_PHYSICAL:
1028                 getparam->value = dev_priv->fb_phys;
1029                 break;
1030         case NOUVEAU_GETPARAM_AGP_PHYSICAL:
1031                 getparam->value = dev_priv->gart_info.aper_base;
1032                 break;
1033         case NOUVEAU_GETPARAM_PCI_PHYSICAL:
1034                 if (dev->sg) {
1035                         getparam->value = (unsigned long)dev->sg->virtual;
1036                 } else {
1037                         NV_ERROR(dev, "Requested PCIGART address, "
1038                                         "while no PCIGART was created\n");
1039                         return -EINVAL;
1040                 }
1041                 break;
1042         case NOUVEAU_GETPARAM_FB_SIZE:
1043                 getparam->value = dev_priv->fb_available_size;
1044                 break;
1045         case NOUVEAU_GETPARAM_AGP_SIZE:
1046                 getparam->value = dev_priv->gart_info.aper_size;
1047                 break;
1048         case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1049                 getparam->value = dev_priv->vm_vram_base;
1050                 break;
1051         case NOUVEAU_GETPARAM_PTIMER_TIME:
1052                 getparam->value = dev_priv->engine.timer.read(dev);
1053                 break;
1054         case NOUVEAU_GETPARAM_HAS_BO_USAGE:
1055                 getparam->value = 1;
1056                 break;
1057         case NOUVEAU_GETPARAM_GRAPH_UNITS:
1058                 /* NV40 and NV50 versions are quite different, but register
1059                  * address is the same. User is supposed to know the card
1060                  * family anyway... */
1061                 if (dev_priv->chipset >= 0x40) {
1062                         getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1063                         break;
1064                 }
1065                 /* FALLTHRU */
1066         default:
1067                 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
1068                 return -EINVAL;
1069         }
1070
1071         return 0;
1072 }
1073
1074 int
1075 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1076                        struct drm_file *file_priv)
1077 {
1078         struct drm_nouveau_setparam *setparam = data;
1079
1080         switch (setparam->param) {
1081         default:
1082                 NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
1083                 return -EINVAL;
1084         }
1085
1086         return 0;
1087 }
1088
1089 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1090 bool nouveau_wait_until(struct drm_device *dev, uint64_t timeout,
1091                         uint32_t reg, uint32_t mask, uint32_t val)
1092 {
1093         struct drm_nouveau_private *dev_priv = dev->dev_private;
1094         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1095         uint64_t start = ptimer->read(dev);
1096
1097         do {
1098                 if ((nv_rd32(dev, reg) & mask) == val)
1099                         return true;
1100         } while (ptimer->read(dev) - start < timeout);
1101
1102         return false;
1103 }
1104
1105 /* Waits for PGRAPH to go completely idle */
1106 bool nouveau_wait_for_idle(struct drm_device *dev)
1107 {
1108         if (!nv_wait(dev, NV04_PGRAPH_STATUS, 0xffffffff, 0x00000000)) {
1109                 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1110                          nv_rd32(dev, NV04_PGRAPH_STATUS));
1111                 return false;
1112         }
1113
1114         return true;
1115 }
1116