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[karo-tx-linux.git] / drivers / gpu / drm / nouveau / nouveau_state.c
1 /*
2  * Copyright 2005 Stephane Marchesin
3  * Copyright 2008 Stuart Bennett
4  * All Rights Reserved.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the next
14  * paragraph) shall be included in all copies or substantial portions of the
15  * Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23  * DEALINGS IN THE SOFTWARE.
24  */
25
26 #include <linux/swab.h>
27 #include <linux/slab.h>
28 #include "drmP.h"
29 #include "drm.h"
30 #include "drm_sarea.h"
31 #include "drm_crtc_helper.h"
32 #include <linux/vgaarb.h>
33 #include <linux/vga_switcheroo.h>
34
35 #include "nouveau_drv.h"
36 #include "nouveau_drm.h"
37 #include "nouveau_fbcon.h"
38 #include "nouveau_ramht.h"
39 #include "nouveau_gpio.h"
40 #include "nouveau_pm.h"
41 #include "nv50_display.h"
42
43 static void nouveau_stub_takedown(struct drm_device *dev) {}
44 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
45
46 static int nouveau_init_engine_ptrs(struct drm_device *dev)
47 {
48         struct drm_nouveau_private *dev_priv = dev->dev_private;
49         struct nouveau_engine *engine = &dev_priv->engine;
50
51         switch (dev_priv->chipset & 0xf0) {
52         case 0x00:
53                 engine->instmem.init            = nv04_instmem_init;
54                 engine->instmem.takedown        = nv04_instmem_takedown;
55                 engine->instmem.suspend         = nv04_instmem_suspend;
56                 engine->instmem.resume          = nv04_instmem_resume;
57                 engine->instmem.get             = nv04_instmem_get;
58                 engine->instmem.put             = nv04_instmem_put;
59                 engine->instmem.map             = nv04_instmem_map;
60                 engine->instmem.unmap           = nv04_instmem_unmap;
61                 engine->instmem.flush           = nv04_instmem_flush;
62                 engine->mc.init                 = nv04_mc_init;
63                 engine->mc.takedown             = nv04_mc_takedown;
64                 engine->timer.init              = nv04_timer_init;
65                 engine->timer.read              = nv04_timer_read;
66                 engine->timer.takedown          = nv04_timer_takedown;
67                 engine->fb.init                 = nv04_fb_init;
68                 engine->fb.takedown             = nv04_fb_takedown;
69                 engine->fifo.channels           = 16;
70                 engine->fifo.init               = nv04_fifo_init;
71                 engine->fifo.takedown           = nv04_fifo_fini;
72                 engine->fifo.disable            = nv04_fifo_disable;
73                 engine->fifo.enable             = nv04_fifo_enable;
74                 engine->fifo.reassign           = nv04_fifo_reassign;
75                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
76                 engine->fifo.channel_id         = nv04_fifo_channel_id;
77                 engine->fifo.create_context     = nv04_fifo_create_context;
78                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
79                 engine->fifo.load_context       = nv04_fifo_load_context;
80                 engine->fifo.unload_context     = nv04_fifo_unload_context;
81                 engine->display.early_init      = nv04_display_early_init;
82                 engine->display.late_takedown   = nv04_display_late_takedown;
83                 engine->display.create          = nv04_display_create;
84                 engine->display.destroy         = nv04_display_destroy;
85                 engine->display.init            = nv04_display_init;
86                 engine->display.fini            = nv04_display_fini;
87                 engine->pm.clocks_get           = nv04_pm_clocks_get;
88                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
89                 engine->pm.clocks_set           = nv04_pm_clocks_set;
90                 engine->vram.init               = nv04_fb_vram_init;
91                 engine->vram.takedown           = nouveau_stub_takedown;
92                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
93                 break;
94         case 0x10:
95                 engine->instmem.init            = nv04_instmem_init;
96                 engine->instmem.takedown        = nv04_instmem_takedown;
97                 engine->instmem.suspend         = nv04_instmem_suspend;
98                 engine->instmem.resume          = nv04_instmem_resume;
99                 engine->instmem.get             = nv04_instmem_get;
100                 engine->instmem.put             = nv04_instmem_put;
101                 engine->instmem.map             = nv04_instmem_map;
102                 engine->instmem.unmap           = nv04_instmem_unmap;
103                 engine->instmem.flush           = nv04_instmem_flush;
104                 engine->mc.init                 = nv04_mc_init;
105                 engine->mc.takedown             = nv04_mc_takedown;
106                 engine->timer.init              = nv04_timer_init;
107                 engine->timer.read              = nv04_timer_read;
108                 engine->timer.takedown          = nv04_timer_takedown;
109                 engine->fb.init                 = nv10_fb_init;
110                 engine->fb.takedown             = nv10_fb_takedown;
111                 engine->fb.init_tile_region     = nv10_fb_init_tile_region;
112                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
113                 engine->fb.free_tile_region     = nv10_fb_free_tile_region;
114                 engine->fifo.channels           = 32;
115                 engine->fifo.init               = nv10_fifo_init;
116                 engine->fifo.takedown           = nv04_fifo_fini;
117                 engine->fifo.disable            = nv04_fifo_disable;
118                 engine->fifo.enable             = nv04_fifo_enable;
119                 engine->fifo.reassign           = nv04_fifo_reassign;
120                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
121                 engine->fifo.channel_id         = nv10_fifo_channel_id;
122                 engine->fifo.create_context     = nv10_fifo_create_context;
123                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
124                 engine->fifo.load_context       = nv10_fifo_load_context;
125                 engine->fifo.unload_context     = nv10_fifo_unload_context;
126                 engine->display.early_init      = nv04_display_early_init;
127                 engine->display.late_takedown   = nv04_display_late_takedown;
128                 engine->display.create          = nv04_display_create;
129                 engine->display.destroy         = nv04_display_destroy;
130                 engine->display.init            = nv04_display_init;
131                 engine->display.fini            = nv04_display_fini;
132                 engine->gpio.drive              = nv10_gpio_drive;
133                 engine->gpio.sense              = nv10_gpio_sense;
134                 engine->pm.clocks_get           = nv04_pm_clocks_get;
135                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
136                 engine->pm.clocks_set           = nv04_pm_clocks_set;
137                 if (dev_priv->chipset == 0x1a ||
138                     dev_priv->chipset == 0x1f)
139                         engine->vram.init       = nv1a_fb_vram_init;
140                 else
141                         engine->vram.init       = nv10_fb_vram_init;
142                 engine->vram.takedown           = nouveau_stub_takedown;
143                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
144                 break;
145         case 0x20:
146                 engine->instmem.init            = nv04_instmem_init;
147                 engine->instmem.takedown        = nv04_instmem_takedown;
148                 engine->instmem.suspend         = nv04_instmem_suspend;
149                 engine->instmem.resume          = nv04_instmem_resume;
150                 engine->instmem.get             = nv04_instmem_get;
151                 engine->instmem.put             = nv04_instmem_put;
152                 engine->instmem.map             = nv04_instmem_map;
153                 engine->instmem.unmap           = nv04_instmem_unmap;
154                 engine->instmem.flush           = nv04_instmem_flush;
155                 engine->mc.init                 = nv04_mc_init;
156                 engine->mc.takedown             = nv04_mc_takedown;
157                 engine->timer.init              = nv04_timer_init;
158                 engine->timer.read              = nv04_timer_read;
159                 engine->timer.takedown          = nv04_timer_takedown;
160                 engine->fb.init                 = nv20_fb_init;
161                 engine->fb.takedown             = nv20_fb_takedown;
162                 engine->fb.init_tile_region     = nv20_fb_init_tile_region;
163                 engine->fb.set_tile_region      = nv20_fb_set_tile_region;
164                 engine->fb.free_tile_region     = nv20_fb_free_tile_region;
165                 engine->fifo.channels           = 32;
166                 engine->fifo.init               = nv10_fifo_init;
167                 engine->fifo.takedown           = nv04_fifo_fini;
168                 engine->fifo.disable            = nv04_fifo_disable;
169                 engine->fifo.enable             = nv04_fifo_enable;
170                 engine->fifo.reassign           = nv04_fifo_reassign;
171                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
172                 engine->fifo.channel_id         = nv10_fifo_channel_id;
173                 engine->fifo.create_context     = nv10_fifo_create_context;
174                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
175                 engine->fifo.load_context       = nv10_fifo_load_context;
176                 engine->fifo.unload_context     = nv10_fifo_unload_context;
177                 engine->display.early_init      = nv04_display_early_init;
178                 engine->display.late_takedown   = nv04_display_late_takedown;
179                 engine->display.create          = nv04_display_create;
180                 engine->display.destroy         = nv04_display_destroy;
181                 engine->display.init            = nv04_display_init;
182                 engine->display.fini            = nv04_display_fini;
183                 engine->gpio.drive              = nv10_gpio_drive;
184                 engine->gpio.sense              = nv10_gpio_sense;
185                 engine->pm.clocks_get           = nv04_pm_clocks_get;
186                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
187                 engine->pm.clocks_set           = nv04_pm_clocks_set;
188                 engine->vram.init               = nv20_fb_vram_init;
189                 engine->vram.takedown           = nouveau_stub_takedown;
190                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
191                 break;
192         case 0x30:
193                 engine->instmem.init            = nv04_instmem_init;
194                 engine->instmem.takedown        = nv04_instmem_takedown;
195                 engine->instmem.suspend         = nv04_instmem_suspend;
196                 engine->instmem.resume          = nv04_instmem_resume;
197                 engine->instmem.get             = nv04_instmem_get;
198                 engine->instmem.put             = nv04_instmem_put;
199                 engine->instmem.map             = nv04_instmem_map;
200                 engine->instmem.unmap           = nv04_instmem_unmap;
201                 engine->instmem.flush           = nv04_instmem_flush;
202                 engine->mc.init                 = nv04_mc_init;
203                 engine->mc.takedown             = nv04_mc_takedown;
204                 engine->timer.init              = nv04_timer_init;
205                 engine->timer.read              = nv04_timer_read;
206                 engine->timer.takedown          = nv04_timer_takedown;
207                 engine->fb.init                 = nv30_fb_init;
208                 engine->fb.takedown             = nv30_fb_takedown;
209                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
210                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
211                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
212                 engine->fifo.channels           = 32;
213                 engine->fifo.init               = nv10_fifo_init;
214                 engine->fifo.takedown           = nv04_fifo_fini;
215                 engine->fifo.disable            = nv04_fifo_disable;
216                 engine->fifo.enable             = nv04_fifo_enable;
217                 engine->fifo.reassign           = nv04_fifo_reassign;
218                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
219                 engine->fifo.channel_id         = nv10_fifo_channel_id;
220                 engine->fifo.create_context     = nv10_fifo_create_context;
221                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
222                 engine->fifo.load_context       = nv10_fifo_load_context;
223                 engine->fifo.unload_context     = nv10_fifo_unload_context;
224                 engine->display.early_init      = nv04_display_early_init;
225                 engine->display.late_takedown   = nv04_display_late_takedown;
226                 engine->display.create          = nv04_display_create;
227                 engine->display.destroy         = nv04_display_destroy;
228                 engine->display.init            = nv04_display_init;
229                 engine->display.fini            = nv04_display_fini;
230                 engine->gpio.drive              = nv10_gpio_drive;
231                 engine->gpio.sense              = nv10_gpio_sense;
232                 engine->pm.clocks_get           = nv04_pm_clocks_get;
233                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
234                 engine->pm.clocks_set           = nv04_pm_clocks_set;
235                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
236                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
237                 engine->vram.init               = nv20_fb_vram_init;
238                 engine->vram.takedown           = nouveau_stub_takedown;
239                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
240                 break;
241         case 0x40:
242         case 0x60:
243                 engine->instmem.init            = nv04_instmem_init;
244                 engine->instmem.takedown        = nv04_instmem_takedown;
245                 engine->instmem.suspend         = nv04_instmem_suspend;
246                 engine->instmem.resume          = nv04_instmem_resume;
247                 engine->instmem.get             = nv04_instmem_get;
248                 engine->instmem.put             = nv04_instmem_put;
249                 engine->instmem.map             = nv04_instmem_map;
250                 engine->instmem.unmap           = nv04_instmem_unmap;
251                 engine->instmem.flush           = nv04_instmem_flush;
252                 engine->mc.init                 = nv40_mc_init;
253                 engine->mc.takedown             = nv40_mc_takedown;
254                 engine->timer.init              = nv04_timer_init;
255                 engine->timer.read              = nv04_timer_read;
256                 engine->timer.takedown          = nv04_timer_takedown;
257                 engine->fb.init                 = nv40_fb_init;
258                 engine->fb.takedown             = nv40_fb_takedown;
259                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
260                 engine->fb.set_tile_region      = nv40_fb_set_tile_region;
261                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
262                 engine->fifo.channels           = 32;
263                 engine->fifo.init               = nv40_fifo_init;
264                 engine->fifo.takedown           = nv04_fifo_fini;
265                 engine->fifo.disable            = nv04_fifo_disable;
266                 engine->fifo.enable             = nv04_fifo_enable;
267                 engine->fifo.reassign           = nv04_fifo_reassign;
268                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
269                 engine->fifo.channel_id         = nv10_fifo_channel_id;
270                 engine->fifo.create_context     = nv40_fifo_create_context;
271                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
272                 engine->fifo.load_context       = nv40_fifo_load_context;
273                 engine->fifo.unload_context     = nv40_fifo_unload_context;
274                 engine->display.early_init      = nv04_display_early_init;
275                 engine->display.late_takedown   = nv04_display_late_takedown;
276                 engine->display.create          = nv04_display_create;
277                 engine->display.destroy         = nv04_display_destroy;
278                 engine->display.init            = nv04_display_init;
279                 engine->display.fini            = nv04_display_fini;
280                 engine->gpio.init               = nv10_gpio_init;
281                 engine->gpio.fini               = nv10_gpio_fini;
282                 engine->gpio.drive              = nv10_gpio_drive;
283                 engine->gpio.sense              = nv10_gpio_sense;
284                 engine->gpio.irq_enable         = nv10_gpio_irq_enable;
285                 engine->pm.clocks_get           = nv40_pm_clocks_get;
286                 engine->pm.clocks_pre           = nv40_pm_clocks_pre;
287                 engine->pm.clocks_set           = nv40_pm_clocks_set;
288                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
289                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
290                 engine->pm.temp_get             = nv40_temp_get;
291                 engine->pm.pwm_get              = nv40_pm_pwm_get;
292                 engine->pm.pwm_set              = nv40_pm_pwm_set;
293                 engine->vram.init               = nv40_fb_vram_init;
294                 engine->vram.takedown           = nouveau_stub_takedown;
295                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
296                 break;
297         case 0x50:
298         case 0x80: /* gotta love NVIDIA's consistency.. */
299         case 0x90:
300         case 0xa0:
301                 engine->instmem.init            = nv50_instmem_init;
302                 engine->instmem.takedown        = nv50_instmem_takedown;
303                 engine->instmem.suspend         = nv50_instmem_suspend;
304                 engine->instmem.resume          = nv50_instmem_resume;
305                 engine->instmem.get             = nv50_instmem_get;
306                 engine->instmem.put             = nv50_instmem_put;
307                 engine->instmem.map             = nv50_instmem_map;
308                 engine->instmem.unmap           = nv50_instmem_unmap;
309                 if (dev_priv->chipset == 0x50)
310                         engine->instmem.flush   = nv50_instmem_flush;
311                 else
312                         engine->instmem.flush   = nv84_instmem_flush;
313                 engine->mc.init                 = nv50_mc_init;
314                 engine->mc.takedown             = nv50_mc_takedown;
315                 engine->timer.init              = nv04_timer_init;
316                 engine->timer.read              = nv04_timer_read;
317                 engine->timer.takedown          = nv04_timer_takedown;
318                 engine->fb.init                 = nv50_fb_init;
319                 engine->fb.takedown             = nv50_fb_takedown;
320                 engine->fifo.channels           = 128;
321                 engine->fifo.init               = nv50_fifo_init;
322                 engine->fifo.takedown           = nv50_fifo_takedown;
323                 engine->fifo.disable            = nv04_fifo_disable;
324                 engine->fifo.enable             = nv04_fifo_enable;
325                 engine->fifo.reassign           = nv04_fifo_reassign;
326                 engine->fifo.channel_id         = nv50_fifo_channel_id;
327                 engine->fifo.create_context     = nv50_fifo_create_context;
328                 engine->fifo.destroy_context    = nv50_fifo_destroy_context;
329                 engine->fifo.load_context       = nv50_fifo_load_context;
330                 engine->fifo.unload_context     = nv50_fifo_unload_context;
331                 engine->fifo.tlb_flush          = nv50_fifo_tlb_flush;
332                 engine->display.early_init      = nv50_display_early_init;
333                 engine->display.late_takedown   = nv50_display_late_takedown;
334                 engine->display.create          = nv50_display_create;
335                 engine->display.destroy         = nv50_display_destroy;
336                 engine->display.init            = nv50_display_init;
337                 engine->display.fini            = nv50_display_fini;
338                 engine->gpio.init               = nv50_gpio_init;
339                 engine->gpio.fini               = nv50_gpio_fini;
340                 engine->gpio.drive              = nv50_gpio_drive;
341                 engine->gpio.sense              = nv50_gpio_sense;
342                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
343                 switch (dev_priv->chipset) {
344                 case 0x84:
345                 case 0x86:
346                 case 0x92:
347                 case 0x94:
348                 case 0x96:
349                 case 0x98:
350                 case 0xa0:
351                 case 0xaa:
352                 case 0xac:
353                 case 0x50:
354                         engine->pm.clocks_get   = nv50_pm_clocks_get;
355                         engine->pm.clocks_pre   = nv50_pm_clocks_pre;
356                         engine->pm.clocks_set   = nv50_pm_clocks_set;
357                         break;
358                 default:
359                         engine->pm.clocks_get   = nva3_pm_clocks_get;
360                         engine->pm.clocks_pre   = nva3_pm_clocks_pre;
361                         engine->pm.clocks_set   = nva3_pm_clocks_set;
362                         break;
363                 }
364                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
365                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
366                 if (dev_priv->chipset >= 0x84)
367                         engine->pm.temp_get     = nv84_temp_get;
368                 else
369                         engine->pm.temp_get     = nv40_temp_get;
370                 engine->pm.pwm_get              = nv50_pm_pwm_get;
371                 engine->pm.pwm_set              = nv50_pm_pwm_set;
372                 engine->vram.init               = nv50_vram_init;
373                 engine->vram.takedown           = nv50_vram_fini;
374                 engine->vram.get                = nv50_vram_new;
375                 engine->vram.put                = nv50_vram_del;
376                 engine->vram.flags_valid        = nv50_vram_flags_valid;
377                 break;
378         case 0xc0:
379                 engine->instmem.init            = nvc0_instmem_init;
380                 engine->instmem.takedown        = nvc0_instmem_takedown;
381                 engine->instmem.suspend         = nvc0_instmem_suspend;
382                 engine->instmem.resume          = nvc0_instmem_resume;
383                 engine->instmem.get             = nv50_instmem_get;
384                 engine->instmem.put             = nv50_instmem_put;
385                 engine->instmem.map             = nv50_instmem_map;
386                 engine->instmem.unmap           = nv50_instmem_unmap;
387                 engine->instmem.flush           = nv84_instmem_flush;
388                 engine->mc.init                 = nv50_mc_init;
389                 engine->mc.takedown             = nv50_mc_takedown;
390                 engine->timer.init              = nv04_timer_init;
391                 engine->timer.read              = nv04_timer_read;
392                 engine->timer.takedown          = nv04_timer_takedown;
393                 engine->fb.init                 = nvc0_fb_init;
394                 engine->fb.takedown             = nvc0_fb_takedown;
395                 engine->fifo.channels           = 128;
396                 engine->fifo.init               = nvc0_fifo_init;
397                 engine->fifo.takedown           = nvc0_fifo_takedown;
398                 engine->fifo.disable            = nvc0_fifo_disable;
399                 engine->fifo.enable             = nvc0_fifo_enable;
400                 engine->fifo.reassign           = nvc0_fifo_reassign;
401                 engine->fifo.channel_id         = nvc0_fifo_channel_id;
402                 engine->fifo.create_context     = nvc0_fifo_create_context;
403                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
404                 engine->fifo.load_context       = nvc0_fifo_load_context;
405                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
406                 engine->display.early_init      = nv50_display_early_init;
407                 engine->display.late_takedown   = nv50_display_late_takedown;
408                 engine->display.create          = nv50_display_create;
409                 engine->display.destroy         = nv50_display_destroy;
410                 engine->display.init            = nv50_display_init;
411                 engine->display.fini            = nv50_display_fini;
412                 engine->gpio.init               = nv50_gpio_init;
413                 engine->gpio.fini               = nv50_gpio_fini;
414                 engine->gpio.drive              = nv50_gpio_drive;
415                 engine->gpio.sense              = nv50_gpio_sense;
416                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
417                 engine->vram.init               = nvc0_vram_init;
418                 engine->vram.takedown           = nv50_vram_fini;
419                 engine->vram.get                = nvc0_vram_new;
420                 engine->vram.put                = nv50_vram_del;
421                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
422                 engine->pm.temp_get             = nv84_temp_get;
423                 engine->pm.clocks_get           = nvc0_pm_clocks_get;
424                 engine->pm.clocks_pre           = nvc0_pm_clocks_pre;
425                 engine->pm.clocks_set           = nvc0_pm_clocks_set;
426                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
427                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
428                 engine->pm.pwm_get              = nv50_pm_pwm_get;
429                 engine->pm.pwm_set              = nv50_pm_pwm_set;
430                 break;
431         case 0xd0:
432                 engine->instmem.init            = nvc0_instmem_init;
433                 engine->instmem.takedown        = nvc0_instmem_takedown;
434                 engine->instmem.suspend         = nvc0_instmem_suspend;
435                 engine->instmem.resume          = nvc0_instmem_resume;
436                 engine->instmem.get             = nv50_instmem_get;
437                 engine->instmem.put             = nv50_instmem_put;
438                 engine->instmem.map             = nv50_instmem_map;
439                 engine->instmem.unmap           = nv50_instmem_unmap;
440                 engine->instmem.flush           = nv84_instmem_flush;
441                 engine->mc.init                 = nv50_mc_init;
442                 engine->mc.takedown             = nv50_mc_takedown;
443                 engine->timer.init              = nv04_timer_init;
444                 engine->timer.read              = nv04_timer_read;
445                 engine->timer.takedown          = nv04_timer_takedown;
446                 engine->fb.init                 = nvc0_fb_init;
447                 engine->fb.takedown             = nvc0_fb_takedown;
448                 engine->fifo.channels           = 128;
449                 engine->fifo.init               = nvc0_fifo_init;
450                 engine->fifo.takedown           = nvc0_fifo_takedown;
451                 engine->fifo.disable            = nvc0_fifo_disable;
452                 engine->fifo.enable             = nvc0_fifo_enable;
453                 engine->fifo.reassign           = nvc0_fifo_reassign;
454                 engine->fifo.channel_id         = nvc0_fifo_channel_id;
455                 engine->fifo.create_context     = nvc0_fifo_create_context;
456                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
457                 engine->fifo.load_context       = nvc0_fifo_load_context;
458                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
459                 engine->display.early_init      = nouveau_stub_init;
460                 engine->display.late_takedown   = nouveau_stub_takedown;
461                 engine->display.create          = nvd0_display_create;
462                 engine->display.destroy         = nvd0_display_destroy;
463                 engine->display.init            = nvd0_display_init;
464                 engine->display.fini            = nvd0_display_fini;
465                 engine->gpio.init               = nv50_gpio_init;
466                 engine->gpio.fini               = nv50_gpio_fini;
467                 engine->gpio.drive              = nvd0_gpio_drive;
468                 engine->gpio.sense              = nvd0_gpio_sense;
469                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
470                 engine->vram.init               = nvc0_vram_init;
471                 engine->vram.takedown           = nv50_vram_fini;
472                 engine->vram.get                = nvc0_vram_new;
473                 engine->vram.put                = nv50_vram_del;
474                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
475                 engine->pm.temp_get             = nv84_temp_get;
476                 engine->pm.clocks_get           = nvc0_pm_clocks_get;
477                 engine->pm.clocks_pre           = nvc0_pm_clocks_pre;
478                 engine->pm.clocks_set           = nvc0_pm_clocks_set;
479                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
480                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
481                 break;
482         case 0xe0:
483                 engine->instmem.init            = nvc0_instmem_init;
484                 engine->instmem.takedown        = nvc0_instmem_takedown;
485                 engine->instmem.suspend         = nvc0_instmem_suspend;
486                 engine->instmem.resume          = nvc0_instmem_resume;
487                 engine->instmem.get             = nv50_instmem_get;
488                 engine->instmem.put             = nv50_instmem_put;
489                 engine->instmem.map             = nv50_instmem_map;
490                 engine->instmem.unmap           = nv50_instmem_unmap;
491                 engine->instmem.flush           = nv84_instmem_flush;
492                 engine->mc.init                 = nv50_mc_init;
493                 engine->mc.takedown             = nv50_mc_takedown;
494                 engine->timer.init              = nv04_timer_init;
495                 engine->timer.read              = nv04_timer_read;
496                 engine->timer.takedown          = nv04_timer_takedown;
497                 engine->fb.init                 = nvc0_fb_init;
498                 engine->fb.takedown             = nvc0_fb_takedown;
499                 engine->fifo.channels           = 4096;
500                 engine->fifo.init               = nve0_fifo_init;
501                 engine->fifo.takedown           = nve0_fifo_takedown;
502                 engine->fifo.disable            = nvc0_fifo_disable;
503                 engine->fifo.enable             = nvc0_fifo_enable;
504                 engine->fifo.reassign           = nvc0_fifo_reassign;
505                 engine->fifo.channel_id         = nve0_fifo_channel_id;
506                 engine->fifo.create_context     = nve0_fifo_create_context;
507                 engine->fifo.destroy_context    = nve0_fifo_destroy_context;
508                 engine->fifo.load_context       = nvc0_fifo_load_context;
509                 engine->fifo.unload_context     = nve0_fifo_unload_context;
510                 engine->display.early_init      = nouveau_stub_init;
511                 engine->display.late_takedown   = nouveau_stub_takedown;
512                 engine->display.create          = nvd0_display_create;
513                 engine->display.destroy         = nvd0_display_destroy;
514                 engine->display.init            = nvd0_display_init;
515                 engine->display.fini            = nvd0_display_fini;
516                 engine->gpio.init               = nv50_gpio_init;
517                 engine->gpio.fini               = nv50_gpio_fini;
518                 engine->gpio.drive              = nvd0_gpio_drive;
519                 engine->gpio.sense              = nvd0_gpio_sense;
520                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
521                 engine->vram.init               = nvc0_vram_init;
522                 engine->vram.takedown           = nv50_vram_fini;
523                 engine->vram.get                = nvc0_vram_new;
524                 engine->vram.put                = nv50_vram_del;
525                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
526                 break;
527         default:
528                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
529                 return 1;
530         }
531
532         /* headless mode */
533         if (nouveau_modeset == 2) {
534                 engine->display.early_init = nouveau_stub_init;
535                 engine->display.late_takedown = nouveau_stub_takedown;
536                 engine->display.create = nouveau_stub_init;
537                 engine->display.init = nouveau_stub_init;
538                 engine->display.destroy = nouveau_stub_takedown;
539         }
540
541         return 0;
542 }
543
544 static unsigned int
545 nouveau_vga_set_decode(void *priv, bool state)
546 {
547         struct drm_device *dev = priv;
548         struct drm_nouveau_private *dev_priv = dev->dev_private;
549
550         if (dev_priv->chipset >= 0x40)
551                 nv_wr32(dev, 0x88054, state);
552         else
553                 nv_wr32(dev, 0x1854, state);
554
555         if (state)
556                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
557                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
558         else
559                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
560 }
561
562 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
563                                          enum vga_switcheroo_state state)
564 {
565         struct drm_device *dev = pci_get_drvdata(pdev);
566         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
567         if (state == VGA_SWITCHEROO_ON) {
568                 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
569                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
570                 nouveau_pci_resume(pdev);
571                 drm_kms_helper_poll_enable(dev);
572                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
573         } else {
574                 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
575                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
576                 drm_kms_helper_poll_disable(dev);
577                 nouveau_switcheroo_optimus_dsm();
578                 nouveau_pci_suspend(pdev, pmm);
579                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
580         }
581 }
582
583 static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
584 {
585         struct drm_device *dev = pci_get_drvdata(pdev);
586         nouveau_fbcon_output_poll_changed(dev);
587 }
588
589 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
590 {
591         struct drm_device *dev = pci_get_drvdata(pdev);
592         bool can_switch;
593
594         spin_lock(&dev->count_lock);
595         can_switch = (dev->open_count == 0);
596         spin_unlock(&dev->count_lock);
597         return can_switch;
598 }
599
600 static void
601 nouveau_card_channel_fini(struct drm_device *dev)
602 {
603         struct drm_nouveau_private *dev_priv = dev->dev_private;
604
605         if (dev_priv->channel)
606                 nouveau_channel_put_unlocked(&dev_priv->channel);
607 }
608
609 static int
610 nouveau_card_channel_init(struct drm_device *dev)
611 {
612         struct drm_nouveau_private *dev_priv = dev->dev_private;
613         struct nouveau_channel *chan;
614         int ret, oclass;
615
616         ret = nouveau_channel_alloc(dev, &chan, NULL, NvDmaFB, NvDmaTT);
617         dev_priv->channel = chan;
618         if (ret)
619                 return ret;
620
621         mutex_unlock(&dev_priv->channel->mutex);
622
623         if (dev_priv->card_type <= NV_50) {
624                 if (dev_priv->card_type < NV_50)
625                         oclass = 0x0039;
626                 else
627                         oclass = 0x5039;
628
629                 ret = nouveau_gpuobj_gr_new(chan, NvM2MF, oclass);
630                 if (ret)
631                         goto error;
632
633                 ret = nouveau_notifier_alloc(chan, NvNotify0, 32, 0xfe0, 0x1000,
634                                              &chan->m2mf_ntfy);
635                 if (ret)
636                         goto error;
637
638                 ret = RING_SPACE(chan, 6);
639                 if (ret)
640                         goto error;
641
642                 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NAME, 1);
643                 OUT_RING  (chan, NvM2MF);
644                 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 3);
645                 OUT_RING  (chan, NvNotify0);
646                 OUT_RING  (chan, chan->vram_handle);
647                 OUT_RING  (chan, chan->gart_handle);
648         } else
649         if (dev_priv->card_type <= NV_D0) {
650                 ret = nouveau_gpuobj_gr_new(chan, 0x9039, 0x9039);
651                 if (ret)
652                         goto error;
653
654                 ret = RING_SPACE(chan, 2);
655                 if (ret)
656                         goto error;
657
658                 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0000, 1);
659                 OUT_RING  (chan, 0x00009039);
660         }
661
662         FIRE_RING (chan);
663 error:
664         if (ret)
665                 nouveau_card_channel_fini(dev);
666         return ret;
667 }
668
669 static const struct vga_switcheroo_client_ops nouveau_switcheroo_ops = {
670         .set_gpu_state = nouveau_switcheroo_set_state,
671         .reprobe = nouveau_switcheroo_reprobe,
672         .can_switch = nouveau_switcheroo_can_switch,
673 };
674
675 int
676 nouveau_card_init(struct drm_device *dev)
677 {
678         struct drm_nouveau_private *dev_priv = dev->dev_private;
679         struct nouveau_engine *engine;
680         int ret, e = 0;
681
682         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
683         vga_switcheroo_register_client(dev->pdev, &nouveau_switcheroo_ops);
684
685         /* Initialise internal driver API hooks */
686         ret = nouveau_init_engine_ptrs(dev);
687         if (ret)
688                 goto out;
689         engine = &dev_priv->engine;
690         spin_lock_init(&dev_priv->channels.lock);
691         spin_lock_init(&dev_priv->tile.lock);
692         spin_lock_init(&dev_priv->context_switch_lock);
693         spin_lock_init(&dev_priv->vm_lock);
694
695         /* Make the CRTCs and I2C buses accessible */
696         ret = engine->display.early_init(dev);
697         if (ret)
698                 goto out;
699
700         /* Parse BIOS tables / Run init tables if card not POSTed */
701         ret = nouveau_bios_init(dev);
702         if (ret)
703                 goto out_display_early;
704
705         /* workaround an odd issue on nvc1 by disabling the device's
706          * nosnoop capability.  hopefully won't cause issues until a
707          * better fix is found - assuming there is one...
708          */
709         if (dev_priv->chipset == 0xc1) {
710                 nv_mask(dev, 0x00088080, 0x00000800, 0x00000000);
711         }
712
713         /* PMC */
714         ret = engine->mc.init(dev);
715         if (ret)
716                 goto out_bios;
717
718         /* PTIMER */
719         ret = engine->timer.init(dev);
720         if (ret)
721                 goto out_mc;
722
723         /* PFB */
724         ret = engine->fb.init(dev);
725         if (ret)
726                 goto out_timer;
727
728         ret = engine->vram.init(dev);
729         if (ret)
730                 goto out_fb;
731
732         /* PGPIO */
733         ret = nouveau_gpio_create(dev);
734         if (ret)
735                 goto out_vram;
736
737         ret = nouveau_gpuobj_init(dev);
738         if (ret)
739                 goto out_gpio;
740
741         ret = engine->instmem.init(dev);
742         if (ret)
743                 goto out_gpuobj;
744
745         ret = nouveau_mem_vram_init(dev);
746         if (ret)
747                 goto out_instmem;
748
749         ret = nouveau_mem_gart_init(dev);
750         if (ret)
751                 goto out_ttmvram;
752
753         if (!dev_priv->noaccel) {
754                 switch (dev_priv->card_type) {
755                 case NV_04:
756                         nv04_graph_create(dev);
757                         break;
758                 case NV_10:
759                         nv10_graph_create(dev);
760                         break;
761                 case NV_20:
762                 case NV_30:
763                         nv20_graph_create(dev);
764                         break;
765                 case NV_40:
766                         nv40_graph_create(dev);
767                         break;
768                 case NV_50:
769                         nv50_graph_create(dev);
770                         break;
771                 case NV_C0:
772                 case NV_D0:
773                         nvc0_graph_create(dev);
774                         break;
775                 default:
776                         break;
777                 }
778
779                 switch (dev_priv->chipset) {
780                 case 0x84:
781                 case 0x86:
782                 case 0x92:
783                 case 0x94:
784                 case 0x96:
785                 case 0xa0:
786                         nv84_crypt_create(dev);
787                         break;
788                 case 0x98:
789                 case 0xaa:
790                 case 0xac:
791                         nv98_crypt_create(dev);
792                         break;
793                 }
794
795                 switch (dev_priv->card_type) {
796                 case NV_50:
797                         switch (dev_priv->chipset) {
798                         case 0xa3:
799                         case 0xa5:
800                         case 0xa8:
801                         case 0xaf:
802                                 nva3_copy_create(dev);
803                                 break;
804                         }
805                         break;
806                 case NV_C0:
807                         nvc0_copy_create(dev, 0);
808                         nvc0_copy_create(dev, 1);
809                         break;
810                 default:
811                         break;
812                 }
813
814                 if (dev_priv->chipset >= 0xa3 || dev_priv->chipset == 0x98) {
815                         nv84_bsp_create(dev);
816                         nv84_vp_create(dev);
817                         nv98_ppp_create(dev);
818                 } else
819                 if (dev_priv->chipset >= 0x84) {
820                         nv50_mpeg_create(dev);
821                         nv84_bsp_create(dev);
822                         nv84_vp_create(dev);
823                 } else
824                 if (dev_priv->chipset >= 0x50) {
825                         nv50_mpeg_create(dev);
826                 } else
827                 if (dev_priv->card_type == NV_40 ||
828                     dev_priv->chipset == 0x31 ||
829                     dev_priv->chipset == 0x34 ||
830                     dev_priv->chipset == 0x36) {
831                         nv31_mpeg_create(dev);
832                 }
833
834                 for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
835                         if (dev_priv->eng[e]) {
836                                 ret = dev_priv->eng[e]->init(dev, e);
837                                 if (ret)
838                                         goto out_engine;
839                         }
840                 }
841
842                 /* PFIFO */
843                 ret = engine->fifo.init(dev);
844                 if (ret)
845                         goto out_engine;
846         }
847
848         ret = nouveau_irq_init(dev);
849         if (ret)
850                 goto out_fifo;
851
852         ret = nouveau_display_create(dev);
853         if (ret)
854                 goto out_irq;
855
856         nouveau_backlight_init(dev);
857         nouveau_pm_init(dev);
858
859         ret = nouveau_fence_init(dev);
860         if (ret)
861                 goto out_pm;
862
863         if (dev_priv->eng[NVOBJ_ENGINE_GR]) {
864                 ret = nouveau_card_channel_init(dev);
865                 if (ret)
866                         goto out_fence;
867         }
868
869         if (dev->mode_config.num_crtc) {
870                 ret = nouveau_display_init(dev);
871                 if (ret)
872                         goto out_chan;
873
874                 nouveau_fbcon_init(dev);
875         }
876
877         return 0;
878
879 out_chan:
880         nouveau_card_channel_fini(dev);
881 out_fence:
882         nouveau_fence_fini(dev);
883 out_pm:
884         nouveau_pm_fini(dev);
885         nouveau_backlight_exit(dev);
886         nouveau_display_destroy(dev);
887 out_irq:
888         nouveau_irq_fini(dev);
889 out_fifo:
890         if (!dev_priv->noaccel)
891                 engine->fifo.takedown(dev);
892 out_engine:
893         if (!dev_priv->noaccel) {
894                 for (e = e - 1; e >= 0; e--) {
895                         if (!dev_priv->eng[e])
896                                 continue;
897                         dev_priv->eng[e]->fini(dev, e, false);
898                         dev_priv->eng[e]->destroy(dev,e );
899                 }
900         }
901         nouveau_mem_gart_fini(dev);
902 out_ttmvram:
903         nouveau_mem_vram_fini(dev);
904 out_instmem:
905         engine->instmem.takedown(dev);
906 out_gpuobj:
907         nouveau_gpuobj_takedown(dev);
908 out_gpio:
909         nouveau_gpio_destroy(dev);
910 out_vram:
911         engine->vram.takedown(dev);
912 out_fb:
913         engine->fb.takedown(dev);
914 out_timer:
915         engine->timer.takedown(dev);
916 out_mc:
917         engine->mc.takedown(dev);
918 out_bios:
919         nouveau_bios_takedown(dev);
920 out_display_early:
921         engine->display.late_takedown(dev);
922 out:
923         vga_client_register(dev->pdev, NULL, NULL, NULL);
924         return ret;
925 }
926
927 static void nouveau_card_takedown(struct drm_device *dev)
928 {
929         struct drm_nouveau_private *dev_priv = dev->dev_private;
930         struct nouveau_engine *engine = &dev_priv->engine;
931         int e;
932
933         if (dev->mode_config.num_crtc) {
934                 nouveau_fbcon_fini(dev);
935                 nouveau_display_fini(dev);
936         }
937
938         nouveau_card_channel_fini(dev);
939         nouveau_fence_fini(dev);
940         nouveau_pm_fini(dev);
941         nouveau_backlight_exit(dev);
942         nouveau_display_destroy(dev);
943
944         if (!dev_priv->noaccel) {
945                 engine->fifo.takedown(dev);
946                 for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
947                         if (dev_priv->eng[e]) {
948                                 dev_priv->eng[e]->fini(dev, e, false);
949                                 dev_priv->eng[e]->destroy(dev,e );
950                         }
951                 }
952         }
953
954         if (dev_priv->vga_ram) {
955                 nouveau_bo_unpin(dev_priv->vga_ram);
956                 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
957         }
958
959         mutex_lock(&dev->struct_mutex);
960         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
961         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
962         mutex_unlock(&dev->struct_mutex);
963         nouveau_mem_gart_fini(dev);
964         nouveau_mem_vram_fini(dev);
965
966         engine->instmem.takedown(dev);
967         nouveau_gpuobj_takedown(dev);
968
969         nouveau_gpio_destroy(dev);
970         engine->vram.takedown(dev);
971         engine->fb.takedown(dev);
972         engine->timer.takedown(dev);
973         engine->mc.takedown(dev);
974
975         nouveau_bios_takedown(dev);
976         engine->display.late_takedown(dev);
977
978         nouveau_irq_fini(dev);
979
980         vga_client_register(dev->pdev, NULL, NULL, NULL);
981 }
982
983 int
984 nouveau_open(struct drm_device *dev, struct drm_file *file_priv)
985 {
986         struct drm_nouveau_private *dev_priv = dev->dev_private;
987         struct nouveau_fpriv *fpriv;
988         int ret;
989
990         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
991         if (unlikely(!fpriv))
992                 return -ENOMEM;
993
994         spin_lock_init(&fpriv->lock);
995         INIT_LIST_HEAD(&fpriv->channels);
996
997         if (dev_priv->card_type == NV_50) {
998                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL,
999                                      &fpriv->vm);
1000                 if (ret) {
1001                         kfree(fpriv);
1002                         return ret;
1003                 }
1004         } else
1005         if (dev_priv->card_type >= NV_C0) {
1006                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL,
1007                                      &fpriv->vm);
1008                 if (ret) {
1009                         kfree(fpriv);
1010                         return ret;
1011                 }
1012         }
1013
1014         file_priv->driver_priv = fpriv;
1015         return 0;
1016 }
1017
1018 /* here a client dies, release the stuff that was allocated for its
1019  * file_priv */
1020 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
1021 {
1022         nouveau_channel_cleanup(dev, file_priv);
1023 }
1024
1025 void
1026 nouveau_postclose(struct drm_device *dev, struct drm_file *file_priv)
1027 {
1028         struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
1029         nouveau_vm_ref(NULL, &fpriv->vm, NULL);
1030         kfree(fpriv);
1031 }
1032
1033 /* first module load, setup the mmio/fb mapping */
1034 /* KMS: we need mmio at load time, not when the first drm client opens. */
1035 int nouveau_firstopen(struct drm_device *dev)
1036 {
1037         return 0;
1038 }
1039
1040 /* if we have an OF card, copy vbios to RAMIN */
1041 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
1042 {
1043 #if defined(__powerpc__)
1044         int size, i;
1045         const uint32_t *bios;
1046         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
1047         if (!dn) {
1048                 NV_INFO(dev, "Unable to get the OF node\n");
1049                 return;
1050         }
1051
1052         bios = of_get_property(dn, "NVDA,BMP", &size);
1053         if (bios) {
1054                 for (i = 0; i < size; i += 4)
1055                         nv_wi32(dev, i, bios[i/4]);
1056                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
1057         } else {
1058                 NV_INFO(dev, "Unable to get the OF bios\n");
1059         }
1060 #endif
1061 }
1062
1063 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
1064 {
1065         struct pci_dev *pdev = dev->pdev;
1066         struct apertures_struct *aper = alloc_apertures(3);
1067         if (!aper)
1068                 return NULL;
1069
1070         aper->ranges[0].base = pci_resource_start(pdev, 1);
1071         aper->ranges[0].size = pci_resource_len(pdev, 1);
1072         aper->count = 1;
1073
1074         if (pci_resource_len(pdev, 2)) {
1075                 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
1076                 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
1077                 aper->count++;
1078         }
1079
1080         if (pci_resource_len(pdev, 3)) {
1081                 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
1082                 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
1083                 aper->count++;
1084         }
1085
1086         return aper;
1087 }
1088
1089 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
1090 {
1091         struct drm_nouveau_private *dev_priv = dev->dev_private;
1092         bool primary = false;
1093         dev_priv->apertures = nouveau_get_apertures(dev);
1094         if (!dev_priv->apertures)
1095                 return -ENOMEM;
1096
1097 #ifdef CONFIG_X86
1098         primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1099 #endif
1100
1101         remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
1102         return 0;
1103 }
1104
1105 int nouveau_load(struct drm_device *dev, unsigned long flags)
1106 {
1107         struct drm_nouveau_private *dev_priv;
1108         unsigned long long offset, length;
1109         uint32_t reg0 = ~0, strap;
1110         int ret;
1111
1112         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1113         if (!dev_priv) {
1114                 ret = -ENOMEM;
1115                 goto err_out;
1116         }
1117         dev->dev_private = dev_priv;
1118         dev_priv->dev = dev;
1119
1120         pci_set_master(dev->pdev);
1121
1122         dev_priv->flags = flags & NOUVEAU_FLAGS;
1123
1124         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
1125                  dev->pci_vendor, dev->pci_device, dev->pdev->class);
1126
1127         /* first up, map the start of mmio and determine the chipset */
1128         dev_priv->mmio = ioremap(pci_resource_start(dev->pdev, 0), PAGE_SIZE);
1129         if (dev_priv->mmio) {
1130 #ifdef __BIG_ENDIAN
1131                 /* put the card into big-endian mode if it's not */
1132                 if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
1133                         nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
1134                 DRM_MEMORYBARRIER();
1135 #endif
1136
1137                 /* determine chipset and derive architecture from it */
1138                 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
1139                 if ((reg0 & 0x0f000000) > 0) {
1140                         dev_priv->chipset = (reg0 & 0xff00000) >> 20;
1141                         switch (dev_priv->chipset & 0xf0) {
1142                         case 0x10:
1143                         case 0x20:
1144                         case 0x30:
1145                                 dev_priv->card_type = dev_priv->chipset & 0xf0;
1146                                 break;
1147                         case 0x40:
1148                         case 0x60:
1149                                 dev_priv->card_type = NV_40;
1150                                 break;
1151                         case 0x50:
1152                         case 0x80:
1153                         case 0x90:
1154                         case 0xa0:
1155                                 dev_priv->card_type = NV_50;
1156                                 break;
1157                         case 0xc0:
1158                                 dev_priv->card_type = NV_C0;
1159                                 break;
1160                         case 0xd0:
1161                                 dev_priv->card_type = NV_D0;
1162                                 break;
1163                         case 0xe0:
1164                                 dev_priv->card_type = NV_E0;
1165                                 break;
1166                         default:
1167                                 break;
1168                         }
1169                 } else
1170                 if ((reg0 & 0xff00fff0) == 0x20004000) {
1171                         if (reg0 & 0x00f00000)
1172                                 dev_priv->chipset = 0x05;
1173                         else
1174                                 dev_priv->chipset = 0x04;
1175                         dev_priv->card_type = NV_04;
1176                 }
1177
1178                 iounmap(dev_priv->mmio);
1179         }
1180
1181         if (!dev_priv->card_type) {
1182                 NV_ERROR(dev, "unsupported chipset 0x%08x\n", reg0);
1183                 ret = -EINVAL;
1184                 goto err_priv;
1185         }
1186
1187         NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
1188                      dev_priv->card_type, reg0);
1189
1190         /* map the mmio regs, limiting the amount to preserve vmap space */
1191         offset = pci_resource_start(dev->pdev, 0);
1192         length = pci_resource_len(dev->pdev, 0);
1193         if (dev_priv->card_type < NV_E0)
1194                 length = min(length, (unsigned long long)0x00800000);
1195
1196         dev_priv->mmio = ioremap(offset, length);
1197         if (!dev_priv->mmio) {
1198                 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
1199                          "Please report your setup to " DRIVER_EMAIL "\n");
1200                 ret = -EINVAL;
1201                 goto err_priv;
1202         }
1203         NV_DEBUG(dev, "regs mapped ok at 0x%llx\n", offset);
1204
1205         /* determine frequency of timing crystal */
1206         strap = nv_rd32(dev, 0x101000);
1207         if ( dev_priv->chipset < 0x17 ||
1208             (dev_priv->chipset >= 0x20 && dev_priv->chipset <= 0x25))
1209                 strap &= 0x00000040;
1210         else
1211                 strap &= 0x00400040;
1212
1213         switch (strap) {
1214         case 0x00000000: dev_priv->crystal = 13500; break;
1215         case 0x00000040: dev_priv->crystal = 14318; break;
1216         case 0x00400000: dev_priv->crystal = 27000; break;
1217         case 0x00400040: dev_priv->crystal = 25000; break;
1218         }
1219
1220         NV_DEBUG(dev, "crystal freq: %dKHz\n", dev_priv->crystal);
1221
1222         /* Determine whether we'll attempt acceleration or not, some
1223          * cards are disabled by default here due to them being known
1224          * non-functional, or never been tested due to lack of hw.
1225          */
1226         dev_priv->noaccel = !!nouveau_noaccel;
1227         if (nouveau_noaccel == -1) {
1228                 switch (dev_priv->chipset) {
1229                 case 0xd9: /* known broken */
1230                         NV_INFO(dev, "acceleration disabled by default, pass "
1231                                      "noaccel=0 to force enable\n");
1232                         dev_priv->noaccel = true;
1233                         break;
1234                 default:
1235                         dev_priv->noaccel = false;
1236                         break;
1237                 }
1238         }
1239
1240         ret = nouveau_remove_conflicting_drivers(dev);
1241         if (ret)
1242                 goto err_mmio;
1243
1244         /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
1245         if (dev_priv->card_type >= NV_40) {
1246                 int ramin_bar = 2;
1247                 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
1248                         ramin_bar = 3;
1249
1250                 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
1251                 dev_priv->ramin =
1252                         ioremap(pci_resource_start(dev->pdev, ramin_bar),
1253                                 dev_priv->ramin_size);
1254                 if (!dev_priv->ramin) {
1255                         NV_ERROR(dev, "Failed to map PRAMIN BAR\n");
1256                         ret = -ENOMEM;
1257                         goto err_mmio;
1258                 }
1259         } else {
1260                 dev_priv->ramin_size = 1 * 1024 * 1024;
1261                 dev_priv->ramin = ioremap(offset + NV_RAMIN,
1262                                           dev_priv->ramin_size);
1263                 if (!dev_priv->ramin) {
1264                         NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
1265                         ret = -ENOMEM;
1266                         goto err_mmio;
1267                 }
1268         }
1269
1270         nouveau_OF_copy_vbios_to_ramin(dev);
1271
1272         /* Special flags */
1273         if (dev->pci_device == 0x01a0)
1274                 dev_priv->flags |= NV_NFORCE;
1275         else if (dev->pci_device == 0x01f0)
1276                 dev_priv->flags |= NV_NFORCE2;
1277
1278         /* For kernel modesetting, init card now and bring up fbcon */
1279         ret = nouveau_card_init(dev);
1280         if (ret)
1281                 goto err_ramin;
1282
1283         return 0;
1284
1285 err_ramin:
1286         iounmap(dev_priv->ramin);
1287 err_mmio:
1288         iounmap(dev_priv->mmio);
1289 err_priv:
1290         kfree(dev_priv);
1291         dev->dev_private = NULL;
1292 err_out:
1293         return ret;
1294 }
1295
1296 void nouveau_lastclose(struct drm_device *dev)
1297 {
1298         vga_switcheroo_process_delayed_switch();
1299 }
1300
1301 int nouveau_unload(struct drm_device *dev)
1302 {
1303         struct drm_nouveau_private *dev_priv = dev->dev_private;
1304
1305         nouveau_card_takedown(dev);
1306
1307         iounmap(dev_priv->mmio);
1308         iounmap(dev_priv->ramin);
1309
1310         kfree(dev_priv);
1311         dev->dev_private = NULL;
1312         return 0;
1313 }
1314
1315 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
1316                                                 struct drm_file *file_priv)
1317 {
1318         struct drm_nouveau_private *dev_priv = dev->dev_private;
1319         struct drm_nouveau_getparam *getparam = data;
1320
1321         switch (getparam->param) {
1322         case NOUVEAU_GETPARAM_CHIPSET_ID:
1323                 getparam->value = dev_priv->chipset;
1324                 break;
1325         case NOUVEAU_GETPARAM_PCI_VENDOR:
1326                 getparam->value = dev->pci_vendor;
1327                 break;
1328         case NOUVEAU_GETPARAM_PCI_DEVICE:
1329                 getparam->value = dev->pci_device;
1330                 break;
1331         case NOUVEAU_GETPARAM_BUS_TYPE:
1332                 if (drm_pci_device_is_agp(dev))
1333                         getparam->value = NV_AGP;
1334                 else if (pci_is_pcie(dev->pdev))
1335                         getparam->value = NV_PCIE;
1336                 else
1337                         getparam->value = NV_PCI;
1338                 break;
1339         case NOUVEAU_GETPARAM_FB_SIZE:
1340                 getparam->value = dev_priv->fb_available_size;
1341                 break;
1342         case NOUVEAU_GETPARAM_AGP_SIZE:
1343                 getparam->value = dev_priv->gart_info.aper_size;
1344                 break;
1345         case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1346                 getparam->value = 0; /* deprecated */
1347                 break;
1348         case NOUVEAU_GETPARAM_PTIMER_TIME:
1349                 getparam->value = dev_priv->engine.timer.read(dev);
1350                 break;
1351         case NOUVEAU_GETPARAM_HAS_BO_USAGE:
1352                 getparam->value = 1;
1353                 break;
1354         case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
1355                 getparam->value = 1;
1356                 break;
1357         case NOUVEAU_GETPARAM_GRAPH_UNITS:
1358                 /* NV40 and NV50 versions are quite different, but register
1359                  * address is the same. User is supposed to know the card
1360                  * family anyway... */
1361                 if (dev_priv->chipset >= 0x40) {
1362                         getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1363                         break;
1364                 }
1365                 /* FALLTHRU */
1366         default:
1367                 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
1368                 return -EINVAL;
1369         }
1370
1371         return 0;
1372 }
1373
1374 int
1375 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1376                        struct drm_file *file_priv)
1377 {
1378         struct drm_nouveau_setparam *setparam = data;
1379
1380         switch (setparam->param) {
1381         default:
1382                 NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
1383                 return -EINVAL;
1384         }
1385
1386         return 0;
1387 }
1388
1389 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1390 bool
1391 nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
1392                 uint32_t reg, uint32_t mask, uint32_t val)
1393 {
1394         struct drm_nouveau_private *dev_priv = dev->dev_private;
1395         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1396         uint64_t start = ptimer->read(dev);
1397
1398         do {
1399                 if ((nv_rd32(dev, reg) & mask) == val)
1400                         return true;
1401         } while (ptimer->read(dev) - start < timeout);
1402
1403         return false;
1404 }
1405
1406 /* Wait until (value(reg) & mask) != val, up until timeout has hit */
1407 bool
1408 nouveau_wait_ne(struct drm_device *dev, uint64_t timeout,
1409                 uint32_t reg, uint32_t mask, uint32_t val)
1410 {
1411         struct drm_nouveau_private *dev_priv = dev->dev_private;
1412         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1413         uint64_t start = ptimer->read(dev);
1414
1415         do {
1416                 if ((nv_rd32(dev, reg) & mask) != val)
1417                         return true;
1418         } while (ptimer->read(dev) - start < timeout);
1419
1420         return false;
1421 }
1422
1423 /* Wait until cond(data) == true, up until timeout has hit */
1424 bool
1425 nouveau_wait_cb(struct drm_device *dev, u64 timeout,
1426                 bool (*cond)(void *), void *data)
1427 {
1428         struct drm_nouveau_private *dev_priv = dev->dev_private;
1429         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1430         u64 start = ptimer->read(dev);
1431
1432         do {
1433                 if (cond(data) == true)
1434                         return true;
1435         } while (ptimer->read(dev) - start < timeout);
1436
1437         return false;
1438 }
1439
1440 /* Waits for PGRAPH to go completely idle */
1441 bool nouveau_wait_for_idle(struct drm_device *dev)
1442 {
1443         struct drm_nouveau_private *dev_priv = dev->dev_private;
1444         uint32_t mask = ~0;
1445
1446         if (dev_priv->card_type == NV_40)
1447                 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1448
1449         if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
1450                 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1451                          nv_rd32(dev, NV04_PGRAPH_STATUS));
1452                 return false;
1453         }
1454
1455         return true;
1456 }
1457