drivers/gpu/drm/nouveau/nouveau_state.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin
   3  * Copyright 2008 Stuart Bennett
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include <linux/swab.h>
  27 #include <linux/slab.h>
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "drm_sarea.h"
  31 #include "drm_crtc_helper.h"
  32 #include <linux/vgaarb.h>
  33 #include <linux/vga_switcheroo.h>
  34
  35 #include "nouveau_drv.h"
  36 #include "nouveau_drm.h"
  37 #include "nouveau_fbcon.h"
  38 #include "nouveau_ramht.h"
  39 #include "nouveau_pm.h"
  40 #include "nv50_display.h"
  41
  42 static void nouveau_stub_takedown(struct drm_device *dev) {}
  43 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
  44
  45 static int nouveau_init_engine_ptrs(struct drm_device *dev)
  46 {
  47         struct drm_nouveau_private *dev_priv = dev->dev_private;
  48         struct nouveau_engine *engine = &dev_priv->engine;
  49
  50         switch (dev_priv->chipset & 0xf0) {
  51         case 0x00:
  52                 engine->instmem.init            = nv04_instmem_init;
  53                 engine->instmem.takedown        = nv04_instmem_takedown;
  54                 engine->instmem.suspend         = nv04_instmem_suspend;
  55                 engine->instmem.resume          = nv04_instmem_resume;
  56                 engine->instmem.get             = nv04_instmem_get;
  57                 engine->instmem.put             = nv04_instmem_put;
  58                 engine->instmem.map             = nv04_instmem_map;
  59                 engine->instmem.unmap           = nv04_instmem_unmap;
  60                 engine->instmem.flush           = nv04_instmem_flush;
  61                 engine->mc.init                 = nv04_mc_init;
  62                 engine->mc.takedown             = nv04_mc_takedown;
  63                 engine->timer.init              = nv04_timer_init;
  64                 engine->timer.read              = nv04_timer_read;
  65                 engine->timer.takedown          = nv04_timer_takedown;
  66                 engine->fb.init                 = nv04_fb_init;
  67                 engine->fb.takedown             = nv04_fb_takedown;
  68                 engine->graph.init              = nv04_graph_init;
  69                 engine->graph.takedown          = nv04_graph_takedown;
  70                 engine->graph.fifo_access       = nv04_graph_fifo_access;
  71                 engine->graph.channel           = nv04_graph_channel;
  72                 engine->graph.create_context    = nv04_graph_create_context;
  73                 engine->graph.destroy_context   = nv04_graph_destroy_context;
  74                 engine->graph.load_context      = nv04_graph_load_context;
  75                 engine->graph.unload_context    = nv04_graph_unload_context;
  76                 engine->fifo.channels           = 16;
  77                 engine->fifo.init               = nv04_fifo_init;
  78                 engine->fifo.takedown           = nv04_fifo_fini;
  79                 engine->fifo.disable            = nv04_fifo_disable;
  80                 engine->fifo.enable             = nv04_fifo_enable;
  81                 engine->fifo.reassign           = nv04_fifo_reassign;
  82                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
  83                 engine->fifo.channel_id         = nv04_fifo_channel_id;
  84                 engine->fifo.create_context     = nv04_fifo_create_context;
  85                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
  86                 engine->fifo.load_context       = nv04_fifo_load_context;
  87                 engine->fifo.unload_context     = nv04_fifo_unload_context;
  88                 engine->display.early_init      = nv04_display_early_init;
  89                 engine->display.late_takedown   = nv04_display_late_takedown;
  90                 engine->display.create          = nv04_display_create;
  91                 engine->display.init            = nv04_display_init;
  92                 engine->display.destroy         = nv04_display_destroy;
  93                 engine->gpio.init               = nouveau_stub_init;
  94                 engine->gpio.takedown           = nouveau_stub_takedown;
  95                 engine->gpio.get                = NULL;
  96                 engine->gpio.set                = NULL;
  97                 engine->gpio.irq_enable         = NULL;
  98                 engine->pm.clock_get            = nv04_pm_clock_get;
  99                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 100                 engine->pm.clock_set            = nv04_pm_clock_set;
 101                 engine->crypt.init              = nouveau_stub_init;
 102                 engine->crypt.takedown          = nouveau_stub_takedown;
 103                 break;
 104         case 0x10:
 105                 engine->instmem.init            = nv04_instmem_init;
 106                 engine->instmem.takedown        = nv04_instmem_takedown;
 107                 engine->instmem.suspend         = nv04_instmem_suspend;
 108                 engine->instmem.resume          = nv04_instmem_resume;
 109                 engine->instmem.get             = nv04_instmem_get;
 110                 engine->instmem.put             = nv04_instmem_put;
 111                 engine->instmem.map             = nv04_instmem_map;
 112                 engine->instmem.unmap           = nv04_instmem_unmap;
 113                 engine->instmem.flush           = nv04_instmem_flush;
 114                 engine->mc.init                 = nv04_mc_init;
 115                 engine->mc.takedown             = nv04_mc_takedown;
 116                 engine->timer.init              = nv04_timer_init;
 117                 engine->timer.read              = nv04_timer_read;
 118                 engine->timer.takedown          = nv04_timer_takedown;
 119                 engine->fb.init                 = nv10_fb_init;
 120                 engine->fb.takedown             = nv10_fb_takedown;
 121                 engine->fb.init_tile_region     = nv10_fb_init_tile_region;
 122                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 123                 engine->fb.free_tile_region     = nv10_fb_free_tile_region;
 124                 engine->graph.init              = nv10_graph_init;
 125                 engine->graph.takedown          = nv10_graph_takedown;
 126                 engine->graph.channel           = nv10_graph_channel;
 127                 engine->graph.create_context    = nv10_graph_create_context;
 128                 engine->graph.destroy_context   = nv10_graph_destroy_context;
 129                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 130                 engine->graph.load_context      = nv10_graph_load_context;
 131                 engine->graph.unload_context    = nv10_graph_unload_context;
 132                 engine->graph.set_tile_region   = nv10_graph_set_tile_region;
 133                 engine->fifo.channels           = 32;
 134                 engine->fifo.init               = nv10_fifo_init;
 135                 engine->fifo.takedown           = nv04_fifo_fini;
 136                 engine->fifo.disable            = nv04_fifo_disable;
 137                 engine->fifo.enable             = nv04_fifo_enable;
 138                 engine->fifo.reassign           = nv04_fifo_reassign;
 139                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 140                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 141                 engine->fifo.create_context     = nv10_fifo_create_context;
 142                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 143                 engine->fifo.load_context       = nv10_fifo_load_context;
 144                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 145                 engine->display.early_init      = nv04_display_early_init;
 146                 engine->display.late_takedown   = nv04_display_late_takedown;
 147                 engine->display.create          = nv04_display_create;
 148                 engine->display.init            = nv04_display_init;
 149                 engine->display.destroy         = nv04_display_destroy;
 150                 engine->gpio.init               = nouveau_stub_init;
 151                 engine->gpio.takedown           = nouveau_stub_takedown;
 152                 engine->gpio.get                = nv10_gpio_get;
 153                 engine->gpio.set                = nv10_gpio_set;
 154                 engine->gpio.irq_enable         = NULL;
 155                 engine->pm.clock_get            = nv04_pm_clock_get;
 156                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 157                 engine->pm.clock_set            = nv04_pm_clock_set;
 158                 engine->crypt.init              = nouveau_stub_init;
 159                 engine->crypt.takedown          = nouveau_stub_takedown;
 160                 break;
 161         case 0x20:
 162                 engine->instmem.init            = nv04_instmem_init;
 163                 engine->instmem.takedown        = nv04_instmem_takedown;
 164                 engine->instmem.suspend         = nv04_instmem_suspend;
 165                 engine->instmem.resume          = nv04_instmem_resume;
 166                 engine->instmem.get             = nv04_instmem_get;
 167                 engine->instmem.put             = nv04_instmem_put;
 168                 engine->instmem.map             = nv04_instmem_map;
 169                 engine->instmem.unmap           = nv04_instmem_unmap;
 170                 engine->instmem.flush           = nv04_instmem_flush;
 171                 engine->mc.init                 = nv04_mc_init;
 172                 engine->mc.takedown             = nv04_mc_takedown;
 173                 engine->timer.init              = nv04_timer_init;
 174                 engine->timer.read              = nv04_timer_read;
 175                 engine->timer.takedown          = nv04_timer_takedown;
 176                 engine->fb.init                 = nv10_fb_init;
 177                 engine->fb.takedown             = nv10_fb_takedown;
 178                 engine->fb.init_tile_region     = nv10_fb_init_tile_region;
 179                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 180                 engine->fb.free_tile_region     = nv10_fb_free_tile_region;
 181                 engine->graph.init              = nv20_graph_init;
 182                 engine->graph.takedown          = nv20_graph_takedown;
 183                 engine->graph.channel           = nv10_graph_channel;
 184                 engine->graph.create_context    = nv20_graph_create_context;
 185                 engine->graph.destroy_context   = nv20_graph_destroy_context;
 186                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 187                 engine->graph.load_context      = nv20_graph_load_context;
 188                 engine->graph.unload_context    = nv20_graph_unload_context;
 189                 engine->graph.set_tile_region   = nv20_graph_set_tile_region;
 190                 engine->fifo.channels           = 32;
 191                 engine->fifo.init               = nv10_fifo_init;
 192                 engine->fifo.takedown           = nv04_fifo_fini;
 193                 engine->fifo.disable            = nv04_fifo_disable;
 194                 engine->fifo.enable             = nv04_fifo_enable;
 195                 engine->fifo.reassign           = nv04_fifo_reassign;
 196                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 197                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 198                 engine->fifo.create_context     = nv10_fifo_create_context;
 199                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 200                 engine->fifo.load_context       = nv10_fifo_load_context;
 201                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 202                 engine->display.early_init      = nv04_display_early_init;
 203                 engine->display.late_takedown   = nv04_display_late_takedown;
 204                 engine->display.create          = nv04_display_create;
 205                 engine->display.init            = nv04_display_init;
 206                 engine->display.destroy         = nv04_display_destroy;
 207                 engine->gpio.init               = nouveau_stub_init;
 208                 engine->gpio.takedown           = nouveau_stub_takedown;
 209                 engine->gpio.get                = nv10_gpio_get;
 210                 engine->gpio.set                = nv10_gpio_set;
 211                 engine->gpio.irq_enable         = NULL;
 212                 engine->pm.clock_get            = nv04_pm_clock_get;
 213                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 214                 engine->pm.clock_set            = nv04_pm_clock_set;
 215                 engine->crypt.init              = nouveau_stub_init;
 216                 engine->crypt.takedown          = nouveau_stub_takedown;
 217                 break;
 218         case 0x30:
 219                 engine->instmem.init            = nv04_instmem_init;
 220                 engine->instmem.takedown        = nv04_instmem_takedown;
 221                 engine->instmem.suspend         = nv04_instmem_suspend;
 222                 engine->instmem.resume          = nv04_instmem_resume;
 223                 engine->instmem.get             = nv04_instmem_get;
 224                 engine->instmem.put             = nv04_instmem_put;
 225                 engine->instmem.map             = nv04_instmem_map;
 226                 engine->instmem.unmap           = nv04_instmem_unmap;
 227                 engine->instmem.flush           = nv04_instmem_flush;
 228                 engine->mc.init                 = nv04_mc_init;
 229                 engine->mc.takedown             = nv04_mc_takedown;
 230                 engine->timer.init              = nv04_timer_init;
 231                 engine->timer.read              = nv04_timer_read;
 232                 engine->timer.takedown          = nv04_timer_takedown;
 233                 engine->fb.init                 = nv30_fb_init;
 234                 engine->fb.takedown             = nv30_fb_takedown;
 235                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 236                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 237                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 238                 engine->graph.init              = nv30_graph_init;
 239                 engine->graph.takedown          = nv20_graph_takedown;
 240                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 241                 engine->graph.channel           = nv10_graph_channel;
 242                 engine->graph.create_context    = nv20_graph_create_context;
 243                 engine->graph.destroy_context   = nv20_graph_destroy_context;
 244                 engine->graph.load_context      = nv20_graph_load_context;
 245                 engine->graph.unload_context    = nv20_graph_unload_context;
 246                 engine->graph.set_tile_region   = nv20_graph_set_tile_region;
 247                 engine->fifo.channels           = 32;
 248                 engine->fifo.init               = nv10_fifo_init;
 249                 engine->fifo.takedown           = nv04_fifo_fini;
 250                 engine->fifo.disable            = nv04_fifo_disable;
 251                 engine->fifo.enable             = nv04_fifo_enable;
 252                 engine->fifo.reassign           = nv04_fifo_reassign;
 253                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 254                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 255                 engine->fifo.create_context     = nv10_fifo_create_context;
 256                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 257                 engine->fifo.load_context       = nv10_fifo_load_context;
 258                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 259                 engine->display.early_init      = nv04_display_early_init;
 260                 engine->display.late_takedown   = nv04_display_late_takedown;
 261                 engine->display.create          = nv04_display_create;
 262                 engine->display.init            = nv04_display_init;
 263                 engine->display.destroy         = nv04_display_destroy;
 264                 engine->gpio.init               = nouveau_stub_init;
 265                 engine->gpio.takedown           = nouveau_stub_takedown;
 266                 engine->gpio.get                = nv10_gpio_get;
 267                 engine->gpio.set                = nv10_gpio_set;
 268                 engine->gpio.irq_enable         = NULL;
 269                 engine->pm.clock_get            = nv04_pm_clock_get;
 270                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 271                 engine->pm.clock_set            = nv04_pm_clock_set;
 272                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 273                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 274                 engine->crypt.init              = nouveau_stub_init;
 275                 engine->crypt.takedown          = nouveau_stub_takedown;
 276                 break;
 277         case 0x40:
 278         case 0x60:
 279                 engine->instmem.init            = nv04_instmem_init;
 280                 engine->instmem.takedown        = nv04_instmem_takedown;
 281                 engine->instmem.suspend         = nv04_instmem_suspend;
 282                 engine->instmem.resume          = nv04_instmem_resume;
 283                 engine->instmem.get             = nv04_instmem_get;
 284                 engine->instmem.put             = nv04_instmem_put;
 285                 engine->instmem.map             = nv04_instmem_map;
 286                 engine->instmem.unmap           = nv04_instmem_unmap;
 287                 engine->instmem.flush           = nv04_instmem_flush;
 288                 engine->mc.init                 = nv40_mc_init;
 289                 engine->mc.takedown             = nv40_mc_takedown;
 290                 engine->timer.init              = nv04_timer_init;
 291                 engine->timer.read              = nv04_timer_read;
 292                 engine->timer.takedown          = nv04_timer_takedown;
 293                 engine->fb.init                 = nv40_fb_init;
 294                 engine->fb.takedown             = nv40_fb_takedown;
 295                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 296                 engine->fb.set_tile_region      = nv40_fb_set_tile_region;
 297                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 298                 engine->graph.init              = nv40_graph_init;
 299                 engine->graph.takedown          = nv40_graph_takedown;
 300                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 301                 engine->graph.channel           = nv40_graph_channel;
 302                 engine->graph.create_context    = nv40_graph_create_context;
 303                 engine->graph.destroy_context   = nv40_graph_destroy_context;
 304                 engine->graph.load_context      = nv40_graph_load_context;
 305                 engine->graph.unload_context    = nv40_graph_unload_context;
 306                 engine->graph.set_tile_region   = nv40_graph_set_tile_region;
 307                 engine->fifo.channels           = 32;
 308                 engine->fifo.init               = nv40_fifo_init;
 309                 engine->fifo.takedown           = nv04_fifo_fini;
 310                 engine->fifo.disable            = nv04_fifo_disable;
 311                 engine->fifo.enable             = nv04_fifo_enable;
 312                 engine->fifo.reassign           = nv04_fifo_reassign;
 313                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 314                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 315                 engine->fifo.create_context     = nv40_fifo_create_context;
 316                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 317                 engine->fifo.load_context       = nv40_fifo_load_context;
 318                 engine->fifo.unload_context     = nv40_fifo_unload_context;
 319                 engine->display.early_init      = nv04_display_early_init;
 320                 engine->display.late_takedown   = nv04_display_late_takedown;
 321                 engine->display.create          = nv04_display_create;
 322                 engine->display.init            = nv04_display_init;
 323                 engine->display.destroy         = nv04_display_destroy;
 324                 engine->gpio.init               = nouveau_stub_init;
 325                 engine->gpio.takedown           = nouveau_stub_takedown;
 326                 engine->gpio.get                = nv10_gpio_get;
 327                 engine->gpio.set                = nv10_gpio_set;
 328                 engine->gpio.irq_enable         = NULL;
 329                 engine->pm.clock_get            = nv04_pm_clock_get;
 330                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 331                 engine->pm.clock_set            = nv04_pm_clock_set;
 332                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 333                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 334                 engine->pm.temp_get             = nv40_temp_get;
 335                 engine->crypt.init              = nouveau_stub_init;
 336                 engine->crypt.takedown          = nouveau_stub_takedown;
 337                 break;
 338         case 0x50:
 339         case 0x80: /* gotta love NVIDIA's consistency.. */
 340         case 0x90:
 341         case 0xA0:
 342                 engine->instmem.init            = nv50_instmem_init;
 343                 engine->instmem.takedown        = nv50_instmem_takedown;
 344                 engine->instmem.suspend         = nv50_instmem_suspend;
 345                 engine->instmem.resume          = nv50_instmem_resume;
 346                 engine->instmem.get             = nv50_instmem_get;
 347                 engine->instmem.put             = nv50_instmem_put;
 348                 engine->instmem.map             = nv50_instmem_map;
 349                 engine->instmem.unmap           = nv50_instmem_unmap;
 350                 if (dev_priv->chipset == 0x50)
 351                         engine->instmem.flush   = nv50_instmem_flush;
 352                 else
 353                         engine->instmem.flush   = nv84_instmem_flush;
 354                 engine->mc.init                 = nv50_mc_init;
 355                 engine->mc.takedown             = nv50_mc_takedown;
 356                 engine->timer.init              = nv04_timer_init;
 357                 engine->timer.read              = nv04_timer_read;
 358                 engine->timer.takedown          = nv04_timer_takedown;
 359                 engine->fb.init                 = nv50_fb_init;
 360                 engine->fb.takedown             = nv50_fb_takedown;
 361                 engine->graph.init              = nv50_graph_init;
 362                 engine->graph.takedown          = nv50_graph_takedown;
 363                 engine->graph.fifo_access       = nv50_graph_fifo_access;
 364                 engine->graph.channel           = nv50_graph_channel;
 365                 engine->graph.create_context    = nv50_graph_create_context;
 366                 engine->graph.destroy_context   = nv50_graph_destroy_context;
 367                 engine->graph.load_context      = nv50_graph_load_context;
 368                 engine->graph.unload_context    = nv50_graph_unload_context;
 369                 if (dev_priv->chipset != 0x86)
 370                         engine->graph.tlb_flush = nv50_graph_tlb_flush;
 371                 else {
 372                         /* from what i can see nvidia do this on every
 373                          * pre-NVA3 board except NVAC, but, we've only
 374                          * ever seen problems on NV86
 375                          */
 376                         engine->graph.tlb_flush = nv86_graph_tlb_flush;
 377                 }
 378                 engine->fifo.channels           = 128;
 379                 engine->fifo.init               = nv50_fifo_init;
 380                 engine->fifo.takedown           = nv50_fifo_takedown;
 381                 engine->fifo.disable            = nv04_fifo_disable;
 382                 engine->fifo.enable             = nv04_fifo_enable;
 383                 engine->fifo.reassign           = nv04_fifo_reassign;
 384                 engine->fifo.channel_id         = nv50_fifo_channel_id;
 385                 engine->fifo.create_context     = nv50_fifo_create_context;
 386                 engine->fifo.destroy_context    = nv50_fifo_destroy_context;
 387                 engine->fifo.load_context       = nv50_fifo_load_context;
 388                 engine->fifo.unload_context     = nv50_fifo_unload_context;
 389                 engine->fifo.tlb_flush          = nv50_fifo_tlb_flush;
 390                 engine->display.early_init      = nv50_display_early_init;
 391                 engine->display.late_takedown   = nv50_display_late_takedown;
 392                 engine->display.create          = nv50_display_create;
 393                 engine->display.init            = nv50_display_init;
 394                 engine->display.destroy         = nv50_display_destroy;
 395                 engine->gpio.init               = nv50_gpio_init;
 396                 engine->gpio.takedown           = nv50_gpio_fini;
 397                 engine->gpio.get                = nv50_gpio_get;
 398                 engine->gpio.set                = nv50_gpio_set;
 399                 engine->gpio.irq_register       = nv50_gpio_irq_register;
 400                 engine->gpio.irq_unregister     = nv50_gpio_irq_unregister;
 401                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 402                 switch (dev_priv->chipset) {
 403                 case 0x84:
 404                 case 0x86:
 405                 case 0x92:
 406                 case 0x94:
 407                 case 0x96:
 408                 case 0x98:
 409                 case 0xa0:
 410                 case 0xaa:
 411                 case 0xac:
 412                 case 0x50:
 413                         engine->pm.clock_get    = nv50_pm_clock_get;
 414                         engine->pm.clock_pre    = nv50_pm_clock_pre;
 415                         engine->pm.clock_set    = nv50_pm_clock_set;
 416                         break;
 417                 default:
 418                         engine->pm.clock_get    = nva3_pm_clock_get;
 419                         engine->pm.clock_pre    = nva3_pm_clock_pre;
 420                         engine->pm.clock_set    = nva3_pm_clock_set;
 421                         break;
 422                 }
 423                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 424                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 425                 if (dev_priv->chipset >= 0x84)
 426                         engine->pm.temp_get     = nv84_temp_get;
 427                 else
 428                         engine->pm.temp_get     = nv40_temp_get;
 429                 switch (dev_priv->chipset) {
 430                 case 0x84:
 431                 case 0x86:
 432                 case 0x92:
 433                 case 0x94:
 434                 case 0x96:
 435                 case 0xa0:
 436                         engine->crypt.init      = nv84_crypt_init;
 437                         engine->crypt.takedown  = nv84_crypt_fini;
 438                         engine->crypt.create_context = nv84_crypt_create_context;
 439                         engine->crypt.destroy_context = nv84_crypt_destroy_context;
 440                         engine->crypt.tlb_flush = nv84_crypt_tlb_flush;
 441                         break;
 442                 default:
 443                         engine->crypt.init      = nouveau_stub_init;
 444                         engine->crypt.takedown  = nouveau_stub_takedown;
 445                         break;
 446                 }
 447                 break;
 448         case 0xC0:
 449                 engine->instmem.init            = nvc0_instmem_init;
 450                 engine->instmem.takedown        = nvc0_instmem_takedown;
 451                 engine->instmem.suspend         = nvc0_instmem_suspend;
 452                 engine->instmem.resume          = nvc0_instmem_resume;
 453                 engine->instmem.get             = nvc0_instmem_get;
 454                 engine->instmem.put             = nvc0_instmem_put;
 455                 engine->instmem.map             = nvc0_instmem_map;
 456                 engine->instmem.unmap           = nvc0_instmem_unmap;
 457                 engine->instmem.flush           = nvc0_instmem_flush;
 458                 engine->mc.init                 = nv50_mc_init;
 459                 engine->mc.takedown             = nv50_mc_takedown;
 460                 engine->timer.init              = nv04_timer_init;
 461                 engine->timer.read              = nv04_timer_read;
 462                 engine->timer.takedown          = nv04_timer_takedown;
 463                 engine->fb.init                 = nvc0_fb_init;
 464                 engine->fb.takedown             = nvc0_fb_takedown;
 465                 engine->graph.init              = nvc0_graph_init;
 466                 engine->graph.takedown          = nvc0_graph_takedown;
 467                 engine->graph.fifo_access       = nvc0_graph_fifo_access;
 468                 engine->graph.channel           = nvc0_graph_channel;
 469                 engine->graph.create_context    = nvc0_graph_create_context;
 470                 engine->graph.destroy_context   = nvc0_graph_destroy_context;
 471                 engine->graph.load_context      = nvc0_graph_load_context;
 472                 engine->graph.unload_context    = nvc0_graph_unload_context;
 473                 engine->fifo.channels           = 128;
 474                 engine->fifo.init               = nvc0_fifo_init;
 475                 engine->fifo.takedown           = nvc0_fifo_takedown;
 476                 engine->fifo.disable            = nvc0_fifo_disable;
 477                 engine->fifo.enable             = nvc0_fifo_enable;
 478                 engine->fifo.reassign           = nvc0_fifo_reassign;
 479                 engine->fifo.channel_id         = nvc0_fifo_channel_id;
 480                 engine->fifo.create_context     = nvc0_fifo_create_context;
 481                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
 482                 engine->fifo.load_context       = nvc0_fifo_load_context;
 483                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
 484                 engine->display.early_init      = nv50_display_early_init;
 485                 engine->display.late_takedown   = nv50_display_late_takedown;
 486                 engine->display.create          = nv50_display_create;
 487                 engine->display.init            = nv50_display_init;
 488                 engine->display.destroy         = nv50_display_destroy;
 489                 engine->gpio.init               = nv50_gpio_init;
 490                 engine->gpio.takedown           = nouveau_stub_takedown;
 491                 engine->gpio.get                = nv50_gpio_get;
 492                 engine->gpio.set                = nv50_gpio_set;
 493                 engine->gpio.irq_register       = nv50_gpio_irq_register;
 494                 engine->gpio.irq_unregister     = nv50_gpio_irq_unregister;
 495                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 496                 engine->crypt.init              = nouveau_stub_init;
 497                 engine->crypt.takedown          = nouveau_stub_takedown;
 498                 break;
 499         default:
 500                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
 501                 return 1;
 502         }
 503
 504         return 0;
 505 }
 506
 507 static unsigned int
 508 nouveau_vga_set_decode(void *priv, bool state)
 509 {
 510         struct drm_device *dev = priv;
 511         struct drm_nouveau_private *dev_priv = dev->dev_private;
 512
 513         if (dev_priv->chipset >= 0x40)
 514                 nv_wr32(dev, 0x88054, state);
 515         else
 516                 nv_wr32(dev, 0x1854, state);
 517
 518         if (state)
 519                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 520                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 521         else
 522                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 523 }
 524
 525 static int
 526 nouveau_card_init_channel(struct drm_device *dev)
 527 {
 528         struct drm_nouveau_private *dev_priv = dev->dev_private;
 529         struct nouveau_gpuobj *gpuobj = NULL;
 530         int ret;
 531
 532         ret = nouveau_channel_alloc(dev, &dev_priv->channel,
 533                                     (struct drm_file *)-2, NvDmaFB, NvDmaTT);
 534         if (ret)
 535                 return ret;
 536
 537         ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
 538                                      0, dev_priv->vram_size,
 539                                      NV_MEM_ACCESS_RW, NV_MEM_TARGET_VRAM,
 540                                      &gpuobj);
 541         if (ret)
 542                 goto out_err;
 543
 544         ret = nouveau_ramht_insert(dev_priv->channel, NvDmaVRAM, gpuobj);
 545         nouveau_gpuobj_ref(NULL, &gpuobj);
 546         if (ret)
 547                 goto out_err;
 548
 549         ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
 550                                      0, dev_priv->gart_info.aper_size,
 551                                      NV_MEM_ACCESS_RW, NV_MEM_TARGET_GART,
 552                                      &gpuobj);
 553         if (ret)
 554                 goto out_err;
 555
 556         ret = nouveau_ramht_insert(dev_priv->channel, NvDmaGART, gpuobj);
 557         nouveau_gpuobj_ref(NULL, &gpuobj);
 558         if (ret)
 559                 goto out_err;
 560
 561         mutex_unlock(&dev_priv->channel->mutex);
 562         return 0;
 563
 564 out_err:
 565         nouveau_channel_put(&dev_priv->channel);
 566         return ret;
 567 }
 568
 569 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
 570                                          enum vga_switcheroo_state state)
 571 {
 572         struct drm_device *dev = pci_get_drvdata(pdev);
 573         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 574         if (state == VGA_SWITCHEROO_ON) {
 575                 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
 576                 nouveau_pci_resume(pdev);
 577                 drm_kms_helper_poll_enable(dev);
 578         } else {
 579                 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
 580                 drm_kms_helper_poll_disable(dev);
 581                 nouveau_pci_suspend(pdev, pmm);
 582         }
 583 }
 584
 585 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
 586 {
 587         struct drm_device *dev = pci_get_drvdata(pdev);
 588         bool can_switch;
 589
 590         spin_lock(&dev->count_lock);
 591         can_switch = (dev->open_count == 0);
 592         spin_unlock(&dev->count_lock);
 593         return can_switch;
 594 }
 595
 596 int
 597 nouveau_card_init(struct drm_device *dev)
 598 {
 599         struct drm_nouveau_private *dev_priv = dev->dev_private;
 600         struct nouveau_engine *engine;
 601         int ret;
 602
 603         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
 604         vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
 605                                        nouveau_switcheroo_can_switch);
 606
 607         /* Initialise internal driver API hooks */
 608         ret = nouveau_init_engine_ptrs(dev);
 609         if (ret)
 610                 goto out;
 611         engine = &dev_priv->engine;
 612         spin_lock_init(&dev_priv->channels.lock);
 613         spin_lock_init(&dev_priv->tile.lock);
 614         spin_lock_init(&dev_priv->context_switch_lock);
 615
 616         /* Make the CRTCs and I2C buses accessible */
 617         ret = engine->display.early_init(dev);
 618         if (ret)
 619                 goto out;
 620
 621         /* Parse BIOS tables / Run init tables if card not POSTed */
 622         ret = nouveau_bios_init(dev);
 623         if (ret)
 624                 goto out_display_early;
 625
 626         nouveau_pm_init(dev);
 627
 628         ret = nouveau_mem_vram_init(dev);
 629         if (ret)
 630                 goto out_bios;
 631
 632         ret = nouveau_gpuobj_init(dev);
 633         if (ret)
 634                 goto out_vram;
 635
 636         ret = engine->instmem.init(dev);
 637         if (ret)
 638                 goto out_gpuobj;
 639
 640         ret = nouveau_mem_gart_init(dev);
 641         if (ret)
 642                 goto out_instmem;
 643
 644         /* PMC */
 645         ret = engine->mc.init(dev);
 646         if (ret)
 647                 goto out_gart;
 648
 649         /* PGPIO */
 650         ret = engine->gpio.init(dev);
 651         if (ret)
 652                 goto out_mc;
 653
 654         /* PTIMER */
 655         ret = engine->timer.init(dev);
 656         if (ret)
 657                 goto out_gpio;
 658
 659         /* PFB */
 660         ret = engine->fb.init(dev);
 661         if (ret)
 662                 goto out_timer;
 663
 664         if (nouveau_noaccel)
 665                 engine->graph.accel_blocked = true;
 666         else {
 667                 /* PGRAPH */
 668                 ret = engine->graph.init(dev);
 669                 if (ret)
 670                         goto out_fb;
 671
 672                 /* PCRYPT */
 673                 ret = engine->crypt.init(dev);
 674                 if (ret)
 675                         goto out_graph;
 676
 677                 /* PFIFO */
 678                 ret = engine->fifo.init(dev);
 679                 if (ret)
 680                         goto out_crypt;
 681         }
 682
 683         ret = engine->display.create(dev);
 684         if (ret)
 685                 goto out_fifo;
 686
 687         ret = drm_vblank_init(dev, nv_two_heads(dev) ? 2 : 1);
 688         if (ret)
 689                 goto out_vblank;
 690
 691         ret = nouveau_irq_init(dev);
 692         if (ret)
 693                 goto out_vblank;
 694
 695         /* what about PVIDEO/PCRTC/PRAMDAC etc? */
 696
 697         if (!engine->graph.accel_blocked) {
 698                 ret = nouveau_fence_init(dev);
 699                 if (ret)
 700                         goto out_irq;
 701
 702                 ret = nouveau_card_init_channel(dev);
 703                 if (ret)
 704                         goto out_fence;
 705         }
 706
 707         ret = nouveau_backlight_init(dev);
 708         if (ret)
 709                 NV_ERROR(dev, "Error %d registering backlight\n", ret);
 710
 711         nouveau_fbcon_init(dev);
 712         drm_kms_helper_poll_init(dev);
 713         return 0;
 714
 715 out_fence:
 716         nouveau_fence_fini(dev);
 717 out_irq:
 718         nouveau_irq_fini(dev);
 719 out_vblank:
 720         drm_vblank_cleanup(dev);
 721         engine->display.destroy(dev);
 722 out_fifo:
 723         if (!nouveau_noaccel)
 724                 engine->fifo.takedown(dev);
 725 out_crypt:
 726         if (!nouveau_noaccel)
 727                 engine->crypt.takedown(dev);
 728 out_graph:
 729         if (!nouveau_noaccel)
 730                 engine->graph.takedown(dev);
 731 out_fb:
 732         engine->fb.takedown(dev);
 733 out_timer:
 734         engine->timer.takedown(dev);
 735 out_gpio:
 736         engine->gpio.takedown(dev);
 737 out_mc:
 738         engine->mc.takedown(dev);
 739 out_gart:
 740         nouveau_mem_gart_fini(dev);
 741 out_instmem:
 742         engine->instmem.takedown(dev);
 743 out_gpuobj:
 744         nouveau_gpuobj_takedown(dev);
 745 out_vram:
 746         nouveau_mem_vram_fini(dev);
 747 out_bios:
 748         nouveau_pm_fini(dev);
 749         nouveau_bios_takedown(dev);
 750 out_display_early:
 751         engine->display.late_takedown(dev);
 752 out:
 753         vga_client_register(dev->pdev, NULL, NULL, NULL);
 754         return ret;
 755 }
 756
 757 static void nouveau_card_takedown(struct drm_device *dev)
 758 {
 759         struct drm_nouveau_private *dev_priv = dev->dev_private;
 760         struct nouveau_engine *engine = &dev_priv->engine;
 761
 762         nouveau_backlight_exit(dev);
 763
 764         if (!engine->graph.accel_blocked) {
 765                 nouveau_fence_fini(dev);
 766                 nouveau_channel_put_unlocked(&dev_priv->channel);
 767         }
 768
 769         if (!nouveau_noaccel) {
 770                 engine->fifo.takedown(dev);
 771                 engine->crypt.takedown(dev);
 772                 engine->graph.takedown(dev);
 773         }
 774         engine->fb.takedown(dev);
 775         engine->timer.takedown(dev);
 776         engine->gpio.takedown(dev);
 777         engine->mc.takedown(dev);
 778         engine->display.late_takedown(dev);
 779
 780         mutex_lock(&dev->struct_mutex);
 781         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
 782         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
 783         mutex_unlock(&dev->struct_mutex);
 784         nouveau_mem_gart_fini(dev);
 785
 786         engine->instmem.takedown(dev);
 787         nouveau_gpuobj_takedown(dev);
 788         nouveau_mem_vram_fini(dev);
 789
 790         nouveau_irq_fini(dev);
 791         drm_vblank_cleanup(dev);
 792
 793         nouveau_pm_fini(dev);
 794         nouveau_bios_takedown(dev);
 795
 796         vga_client_register(dev->pdev, NULL, NULL, NULL);
 797 }
 798
 799 /* here a client dies, release the stuff that was allocated for its
 800  * file_priv */
 801 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
 802 {
 803         nouveau_channel_cleanup(dev, file_priv);
 804 }
 805
 806 /* first module load, setup the mmio/fb mapping */
 807 /* KMS: we need mmio at load time, not when the first drm client opens. */
 808 int nouveau_firstopen(struct drm_device *dev)
 809 {
 810         return 0;
 811 }
 812
 813 /* if we have an OF card, copy vbios to RAMIN */
 814 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
 815 {
 816 #if defined(__powerpc__)
 817         int size, i;
 818         const uint32_t *bios;
 819         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
 820         if (!dn) {
 821                 NV_INFO(dev, "Unable to get the OF node\n");
 822                 return;
 823         }
 824
 825         bios = of_get_property(dn, "NVDA,BMP", &size);
 826         if (bios) {
 827                 for (i = 0; i < size; i += 4)
 828                         nv_wi32(dev, i, bios[i/4]);
 829                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
 830         } else {
 831                 NV_INFO(dev, "Unable to get the OF bios\n");
 832         }
 833 #endif
 834 }
 835
 836 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
 837 {
 838         struct pci_dev *pdev = dev->pdev;
 839         struct apertures_struct *aper = alloc_apertures(3);
 840         if (!aper)
 841                 return NULL;
 842
 843         aper->ranges[0].base = pci_resource_start(pdev, 1);
 844         aper->ranges[0].size = pci_resource_len(pdev, 1);
 845         aper->count = 1;
 846
 847         if (pci_resource_len(pdev, 2)) {
 848                 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
 849                 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
 850                 aper->count++;
 851         }
 852
 853         if (pci_resource_len(pdev, 3)) {
 854                 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
 855                 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
 856                 aper->count++;
 857         }
 858
 859         return aper;
 860 }
 861
 862 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
 863 {
 864         struct drm_nouveau_private *dev_priv = dev->dev_private;
 865         bool primary = false;
 866         dev_priv->apertures = nouveau_get_apertures(dev);
 867         if (!dev_priv->apertures)
 868                 return -ENOMEM;
 869
 870 #ifdef CONFIG_X86
 871         primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 872 #endif
 873
 874         remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
 875         return 0;
 876 }
 877
 878 int nouveau_load(struct drm_device *dev, unsigned long flags)
 879 {
 880         struct drm_nouveau_private *dev_priv;
 881         uint32_t reg0;
 882         resource_size_t mmio_start_offs;
 883         int ret;
 884
 885         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 886         if (!dev_priv) {
 887                 ret = -ENOMEM;
 888                 goto err_out;
 889         }
 890         dev->dev_private = dev_priv;
 891         dev_priv->dev = dev;
 892
 893         dev_priv->flags = flags & NOUVEAU_FLAGS;
 894
 895         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
 896                  dev->pci_vendor, dev->pci_device, dev->pdev->class);
 897
 898         dev_priv->wq = create_workqueue("nouveau");
 899         if (!dev_priv->wq) {
 900                 ret = -EINVAL;
 901                 goto err_priv;
 902         }
 903
 904         /* resource 0 is mmio regs */
 905         /* resource 1 is linear FB */
 906         /* resource 2 is RAMIN (mmio regs + 0x1000000) */
 907         /* resource 6 is bios */
 908
 909         /* map the mmio regs */
 910         mmio_start_offs = pci_resource_start(dev->pdev, 0);
 911         dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
 912         if (!dev_priv->mmio) {
 913                 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
 914                          "Please report your setup to " DRIVER_EMAIL "\n");
 915                 ret = -EINVAL;
 916                 goto err_wq;
 917         }
 918         NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
 919                                         (unsigned long long)mmio_start_offs);
 920
 921 #ifdef __BIG_ENDIAN
 922         /* Put the card in BE mode if it's not */
 923         if (nv_rd32(dev, NV03_PMC_BOOT_1))
 924                 nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
 925
 926         DRM_MEMORYBARRIER();
 927 #endif
 928
 929         /* Time to determine the card architecture */
 930         reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
 931
 932         /* We're dealing with >=NV10 */
 933         if ((reg0 & 0x0f000000) > 0) {
 934                 /* Bit 27-20 contain the architecture in hex */
 935                 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
 936         /* NV04 or NV05 */
 937         } else if ((reg0 & 0xff00fff0) == 0x20004000) {
 938                 if (reg0 & 0x00f00000)
 939                         dev_priv->chipset = 0x05;
 940                 else
 941                         dev_priv->chipset = 0x04;
 942         } else
 943                 dev_priv->chipset = 0xff;
 944
 945         switch (dev_priv->chipset & 0xf0) {
 946         case 0x00:
 947         case 0x10:
 948         case 0x20:
 949         case 0x30:
 950                 dev_priv->card_type = dev_priv->chipset & 0xf0;
 951                 break;
 952         case 0x40:
 953         case 0x60:
 954                 dev_priv->card_type = NV_40;
 955                 break;
 956         case 0x50:
 957         case 0x80:
 958         case 0x90:
 959         case 0xa0:
 960                 dev_priv->card_type = NV_50;
 961                 break;
 962         case 0xc0:
 963                 dev_priv->card_type = NV_C0;
 964                 break;
 965         default:
 966                 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
 967                 ret = -EINVAL;
 968                 goto err_mmio;
 969         }
 970
 971         NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
 972                 dev_priv->card_type, reg0);
 973
 974         ret = nouveau_remove_conflicting_drivers(dev);
 975         if (ret)
 976                 goto err_mmio;
 977
 978         /* Map PRAMIN BAR, or on older cards, the aperture withing BAR0 */
 979         if (dev_priv->card_type >= NV_40) {
 980                 int ramin_bar = 2;
 981                 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
 982                         ramin_bar = 3;
 983
 984                 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
 985                 dev_priv->ramin =
 986                         ioremap(pci_resource_start(dev->pdev, ramin_bar),
 987                                 dev_priv->ramin_size);
 988                 if (!dev_priv->ramin) {
 989                         NV_ERROR(dev, "Failed to PRAMIN BAR");
 990                         ret = -ENOMEM;
 991                         goto err_mmio;
 992                 }
 993         } else {
 994                 dev_priv->ramin_size = 1 * 1024 * 1024;
 995                 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
 996                                           dev_priv->ramin_size);
 997                 if (!dev_priv->ramin) {
 998                         NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
 999                         ret = -ENOMEM;
1000                         goto err_mmio;
1001                 }
1002         }
1003
1004         nouveau_OF_copy_vbios_to_ramin(dev);
1005
1006         /* Special flags */
1007         if (dev->pci_device == 0x01a0)
1008                 dev_priv->flags |= NV_NFORCE;
1009         else if (dev->pci_device == 0x01f0)
1010                 dev_priv->flags |= NV_NFORCE2;
1011
1012         /* For kernel modesetting, init card now and bring up fbcon */
1013         ret = nouveau_card_init(dev);
1014         if (ret)
1015                 goto err_ramin;
1016
1017         return 0;
1018
1019 err_ramin:
1020         iounmap(dev_priv->ramin);
1021 err_mmio:
1022         iounmap(dev_priv->mmio);
1023 err_wq:
1024         destroy_workqueue(dev_priv->wq);
1025 err_priv:
1026         kfree(dev_priv);
1027         dev->dev_private = NULL;
1028 err_out:
1029         return ret;
1030 }
1031
1032 void nouveau_lastclose(struct drm_device *dev)
1033 {
1034 }
1035
1036 int nouveau_unload(struct drm_device *dev)
1037 {
1038         struct drm_nouveau_private *dev_priv = dev->dev_private;
1039         struct nouveau_engine *engine = &dev_priv->engine;
1040
1041         drm_kms_helper_poll_fini(dev);
1042         nouveau_fbcon_fini(dev);
1043         engine->display.destroy(dev);
1044         nouveau_card_takedown(dev);
1045
1046         iounmap(dev_priv->mmio);
1047         iounmap(dev_priv->ramin);
1048
1049         kfree(dev_priv);
1050         dev->dev_private = NULL;
1051         return 0;
1052 }
1053
1054 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
1055                                                 struct drm_file *file_priv)
1056 {
1057         struct drm_nouveau_private *dev_priv = dev->dev_private;
1058         struct drm_nouveau_getparam *getparam = data;
1059
1060         switch (getparam->param) {
1061         case NOUVEAU_GETPARAM_CHIPSET_ID:
1062                 getparam->value = dev_priv->chipset;
1063                 break;
1064         case NOUVEAU_GETPARAM_PCI_VENDOR:
1065                 getparam->value = dev->pci_vendor;
1066                 break;
1067         case NOUVEAU_GETPARAM_PCI_DEVICE:
1068                 getparam->value = dev->pci_device;
1069                 break;
1070         case NOUVEAU_GETPARAM_BUS_TYPE:
1071                 if (drm_device_is_agp(dev))
1072                         getparam->value = NV_AGP;
1073                 else if (drm_device_is_pcie(dev))
1074                         getparam->value = NV_PCIE;
1075                 else
1076                         getparam->value = NV_PCI;
1077                 break;
1078         case NOUVEAU_GETPARAM_FB_SIZE:
1079                 getparam->value = dev_priv->fb_available_size;
1080                 break;
1081         case NOUVEAU_GETPARAM_AGP_SIZE:
1082                 getparam->value = dev_priv->gart_info.aper_size;
1083                 break;
1084         case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1085                 getparam->value = 0; /* deprecated */
1086                 break;
1087         case NOUVEAU_GETPARAM_PTIMER_TIME:
1088                 getparam->value = dev_priv->engine.timer.read(dev);
1089                 break;
1090         case NOUVEAU_GETPARAM_HAS_BO_USAGE:
1091                 getparam->value = 1;
1092                 break;
1093         case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
1094                 getparam->value = (dev_priv->card_type < NV_50);
1095                 break;
1096         case NOUVEAU_GETPARAM_GRAPH_UNITS:
1097                 /* NV40 and NV50 versions are quite different, but register
1098                  * address is the same. User is supposed to know the card
1099                  * family anyway... */
1100                 if (dev_priv->chipset >= 0x40) {
1101                         getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1102                         break;
1103                 }
1104                 /* FALLTHRU */
1105         default:
1106                 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
1107                 return -EINVAL;
1108         }
1109
1110         return 0;
1111 }
1112
1113 int
1114 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1115                        struct drm_file *file_priv)
1116 {
1117         struct drm_nouveau_setparam *setparam = data;
1118
1119         switch (setparam->param) {
1120         default:
1121                 NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
1122                 return -EINVAL;
1123         }
1124
1125         return 0;
1126 }
1127
1128 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1129 bool
1130 nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
1131                 uint32_t reg, uint32_t mask, uint32_t val)
1132 {
1133         struct drm_nouveau_private *dev_priv = dev->dev_private;
1134         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1135         uint64_t start = ptimer->read(dev);
1136
1137         do {
1138                 if ((nv_rd32(dev, reg) & mask) == val)
1139                         return true;
1140         } while (ptimer->read(dev) - start < timeout);
1141
1142         return false;
1143 }
1144
1145 /* Wait until (value(reg) & mask) != val, up until timeout has hit */
1146 bool
1147 nouveau_wait_ne(struct drm_device *dev, uint64_t timeout,
1148                 uint32_t reg, uint32_t mask, uint32_t val)
1149 {
1150         struct drm_nouveau_private *dev_priv = dev->dev_private;
1151         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1152         uint64_t start = ptimer->read(dev);
1153
1154         do {
1155                 if ((nv_rd32(dev, reg) & mask) != val)
1156                         return true;
1157         } while (ptimer->read(dev) - start < timeout);
1158
1159         return false;
1160 }
1161
1162 /* Waits for PGRAPH to go completely idle */
1163 bool nouveau_wait_for_idle(struct drm_device *dev)
1164 {
1165         struct drm_nouveau_private *dev_priv = dev->dev_private;
1166         uint32_t mask = ~0;
1167
1168         if (dev_priv->card_type == NV_40)
1169                 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1170
1171         if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
1172                 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1173                          nv_rd32(dev, NV04_PGRAPH_STATUS));
1174                 return false;
1175         }
1176
1177         return true;
1178 }
1179