drivers/gpu/drm/nouveau/nouveau_state.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin
   3  * Copyright 2008 Stuart Bennett
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include <linux/swab.h>
  27 #include <linux/slab.h>
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "drm_sarea.h"
  31 #include "drm_crtc_helper.h"
  32 #include <linux/vgaarb.h>
  33 #include <linux/vga_switcheroo.h>
  34
  35 #include "nouveau_drv.h"
  36 #include "nouveau_drm.h"
  37 #include "nouveau_fbcon.h"
  38 #include "nouveau_ramht.h"
  39 #include "nouveau_pm.h"
  40 #include "nv50_display.h"
  41
  42 static void nouveau_stub_takedown(struct drm_device *dev) {}
  43 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
  44
  45 static int nouveau_init_engine_ptrs(struct drm_device *dev)
  46 {
  47         struct drm_nouveau_private *dev_priv = dev->dev_private;
  48         struct nouveau_engine *engine = &dev_priv->engine;
  49
  50         switch (dev_priv->chipset & 0xf0) {
  51         case 0x00:
  52                 engine->instmem.init            = nv04_instmem_init;
  53                 engine->instmem.takedown        = nv04_instmem_takedown;
  54                 engine->instmem.suspend         = nv04_instmem_suspend;
  55                 engine->instmem.resume          = nv04_instmem_resume;
  56                 engine->instmem.populate        = nv04_instmem_populate;
  57                 engine->instmem.clear           = nv04_instmem_clear;
  58                 engine->instmem.bind            = nv04_instmem_bind;
  59                 engine->instmem.unbind          = nv04_instmem_unbind;
  60                 engine->instmem.flush           = nv04_instmem_flush;
  61                 engine->mc.init                 = nv04_mc_init;
  62                 engine->mc.takedown             = nv04_mc_takedown;
  63                 engine->timer.init              = nv04_timer_init;
  64                 engine->timer.read              = nv04_timer_read;
  65                 engine->timer.takedown          = nv04_timer_takedown;
  66                 engine->fb.init                 = nv04_fb_init;
  67                 engine->fb.takedown             = nv04_fb_takedown;
  68                 engine->graph.grclass           = nv04_graph_grclass;
  69                 engine->graph.init              = nv04_graph_init;
  70                 engine->graph.takedown          = nv04_graph_takedown;
  71                 engine->graph.fifo_access       = nv04_graph_fifo_access;
  72                 engine->graph.channel           = nv04_graph_channel;
  73                 engine->graph.create_context    = nv04_graph_create_context;
  74                 engine->graph.destroy_context   = nv04_graph_destroy_context;
  75                 engine->graph.load_context      = nv04_graph_load_context;
  76                 engine->graph.unload_context    = nv04_graph_unload_context;
  77                 engine->fifo.channels           = 16;
  78                 engine->fifo.init               = nv04_fifo_init;
  79                 engine->fifo.takedown           = nouveau_stub_takedown;
  80                 engine->fifo.disable            = nv04_fifo_disable;
  81                 engine->fifo.enable             = nv04_fifo_enable;
  82                 engine->fifo.reassign           = nv04_fifo_reassign;
  83                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
  84                 engine->fifo.channel_id         = nv04_fifo_channel_id;
  85                 engine->fifo.create_context     = nv04_fifo_create_context;
  86                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
  87                 engine->fifo.load_context       = nv04_fifo_load_context;
  88                 engine->fifo.unload_context     = nv04_fifo_unload_context;
  89                 engine->display.early_init      = nv04_display_early_init;
  90                 engine->display.late_takedown   = nv04_display_late_takedown;
  91                 engine->display.create          = nv04_display_create;
  92                 engine->display.init            = nv04_display_init;
  93                 engine->display.destroy         = nv04_display_destroy;
  94                 engine->gpio.init               = nouveau_stub_init;
  95                 engine->gpio.takedown           = nouveau_stub_takedown;
  96                 engine->gpio.get                = NULL;
  97                 engine->gpio.set                = NULL;
  98                 engine->gpio.irq_enable         = NULL;
  99                 engine->pm.clock_get            = nv04_pm_clock_get;
 100                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 101                 engine->pm.clock_set            = nv04_pm_clock_set;
 102                 break;
 103         case 0x10:
 104                 engine->instmem.init            = nv04_instmem_init;
 105                 engine->instmem.takedown        = nv04_instmem_takedown;
 106                 engine->instmem.suspend         = nv04_instmem_suspend;
 107                 engine->instmem.resume          = nv04_instmem_resume;
 108                 engine->instmem.populate        = nv04_instmem_populate;
 109                 engine->instmem.clear           = nv04_instmem_clear;
 110                 engine->instmem.bind            = nv04_instmem_bind;
 111                 engine->instmem.unbind          = nv04_instmem_unbind;
 112                 engine->instmem.flush           = nv04_instmem_flush;
 113                 engine->mc.init                 = nv04_mc_init;
 114                 engine->mc.takedown             = nv04_mc_takedown;
 115                 engine->timer.init              = nv04_timer_init;
 116                 engine->timer.read              = nv04_timer_read;
 117                 engine->timer.takedown          = nv04_timer_takedown;
 118                 engine->fb.init                 = nv10_fb_init;
 119                 engine->fb.takedown             = nv10_fb_takedown;
 120                 engine->fb.set_region_tiling    = nv10_fb_set_region_tiling;
 121                 engine->graph.grclass           = nv10_graph_grclass;
 122                 engine->graph.init              = nv10_graph_init;
 123                 engine->graph.takedown          = nv10_graph_takedown;
 124                 engine->graph.channel           = nv10_graph_channel;
 125                 engine->graph.create_context    = nv10_graph_create_context;
 126                 engine->graph.destroy_context   = nv10_graph_destroy_context;
 127                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 128                 engine->graph.load_context      = nv10_graph_load_context;
 129                 engine->graph.unload_context    = nv10_graph_unload_context;
 130                 engine->graph.set_region_tiling = nv10_graph_set_region_tiling;
 131                 engine->fifo.channels           = 32;
 132                 engine->fifo.init               = nv10_fifo_init;
 133                 engine->fifo.takedown           = nouveau_stub_takedown;
 134                 engine->fifo.disable            = nv04_fifo_disable;
 135                 engine->fifo.enable             = nv04_fifo_enable;
 136                 engine->fifo.reassign           = nv04_fifo_reassign;
 137                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 138                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 139                 engine->fifo.create_context     = nv10_fifo_create_context;
 140                 engine->fifo.destroy_context    = nv10_fifo_destroy_context;
 141                 engine->fifo.load_context       = nv10_fifo_load_context;
 142                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 143                 engine->display.early_init      = nv04_display_early_init;
 144                 engine->display.late_takedown   = nv04_display_late_takedown;
 145                 engine->display.create          = nv04_display_create;
 146                 engine->display.init            = nv04_display_init;
 147                 engine->display.destroy         = nv04_display_destroy;
 148                 engine->gpio.init               = nouveau_stub_init;
 149                 engine->gpio.takedown           = nouveau_stub_takedown;
 150                 engine->gpio.get                = nv10_gpio_get;
 151                 engine->gpio.set                = nv10_gpio_set;
 152                 engine->gpio.irq_enable         = NULL;
 153                 engine->pm.clock_get            = nv04_pm_clock_get;
 154                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 155                 engine->pm.clock_set            = nv04_pm_clock_set;
 156                 break;
 157         case 0x20:
 158                 engine->instmem.init            = nv04_instmem_init;
 159                 engine->instmem.takedown        = nv04_instmem_takedown;
 160                 engine->instmem.suspend         = nv04_instmem_suspend;
 161                 engine->instmem.resume          = nv04_instmem_resume;
 162                 engine->instmem.populate        = nv04_instmem_populate;
 163                 engine->instmem.clear           = nv04_instmem_clear;
 164                 engine->instmem.bind            = nv04_instmem_bind;
 165                 engine->instmem.unbind          = nv04_instmem_unbind;
 166                 engine->instmem.flush           = nv04_instmem_flush;
 167                 engine->mc.init                 = nv04_mc_init;
 168                 engine->mc.takedown             = nv04_mc_takedown;
 169                 engine->timer.init              = nv04_timer_init;
 170                 engine->timer.read              = nv04_timer_read;
 171                 engine->timer.takedown          = nv04_timer_takedown;
 172                 engine->fb.init                 = nv10_fb_init;
 173                 engine->fb.takedown             = nv10_fb_takedown;
 174                 engine->fb.set_region_tiling    = nv10_fb_set_region_tiling;
 175                 engine->graph.grclass           = nv20_graph_grclass;
 176                 engine->graph.init              = nv20_graph_init;
 177                 engine->graph.takedown          = nv20_graph_takedown;
 178                 engine->graph.channel           = nv10_graph_channel;
 179                 engine->graph.create_context    = nv20_graph_create_context;
 180                 engine->graph.destroy_context   = nv20_graph_destroy_context;
 181                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 182                 engine->graph.load_context      = nv20_graph_load_context;
 183                 engine->graph.unload_context    = nv20_graph_unload_context;
 184                 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
 185                 engine->fifo.channels           = 32;
 186                 engine->fifo.init               = nv10_fifo_init;
 187                 engine->fifo.takedown           = nouveau_stub_takedown;
 188                 engine->fifo.disable            = nv04_fifo_disable;
 189                 engine->fifo.enable             = nv04_fifo_enable;
 190                 engine->fifo.reassign           = nv04_fifo_reassign;
 191                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 192                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 193                 engine->fifo.create_context     = nv10_fifo_create_context;
 194                 engine->fifo.destroy_context    = nv10_fifo_destroy_context;
 195                 engine->fifo.load_context       = nv10_fifo_load_context;
 196                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 197                 engine->display.early_init      = nv04_display_early_init;
 198                 engine->display.late_takedown   = nv04_display_late_takedown;
 199                 engine->display.create          = nv04_display_create;
 200                 engine->display.init            = nv04_display_init;
 201                 engine->display.destroy         = nv04_display_destroy;
 202                 engine->gpio.init               = nouveau_stub_init;
 203                 engine->gpio.takedown           = nouveau_stub_takedown;
 204                 engine->gpio.get                = nv10_gpio_get;
 205                 engine->gpio.set                = nv10_gpio_set;
 206                 engine->gpio.irq_enable         = NULL;
 207                 engine->pm.clock_get            = nv04_pm_clock_get;
 208                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 209                 engine->pm.clock_set            = nv04_pm_clock_set;
 210                 break;
 211         case 0x30:
 212                 engine->instmem.init            = nv04_instmem_init;
 213                 engine->instmem.takedown        = nv04_instmem_takedown;
 214                 engine->instmem.suspend         = nv04_instmem_suspend;
 215                 engine->instmem.resume          = nv04_instmem_resume;
 216                 engine->instmem.populate        = nv04_instmem_populate;
 217                 engine->instmem.clear           = nv04_instmem_clear;
 218                 engine->instmem.bind            = nv04_instmem_bind;
 219                 engine->instmem.unbind          = nv04_instmem_unbind;
 220                 engine->instmem.flush           = nv04_instmem_flush;
 221                 engine->mc.init                 = nv04_mc_init;
 222                 engine->mc.takedown             = nv04_mc_takedown;
 223                 engine->timer.init              = nv04_timer_init;
 224                 engine->timer.read              = nv04_timer_read;
 225                 engine->timer.takedown          = nv04_timer_takedown;
 226                 engine->fb.init                 = nv30_fb_init;
 227                 engine->fb.takedown             = nv30_fb_takedown;
 228                 engine->fb.set_region_tiling    = nv10_fb_set_region_tiling;
 229                 engine->graph.grclass           = nv30_graph_grclass;
 230                 engine->graph.init              = nv30_graph_init;
 231                 engine->graph.takedown          = nv20_graph_takedown;
 232                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 233                 engine->graph.channel           = nv10_graph_channel;
 234                 engine->graph.create_context    = nv20_graph_create_context;
 235                 engine->graph.destroy_context   = nv20_graph_destroy_context;
 236                 engine->graph.load_context      = nv20_graph_load_context;
 237                 engine->graph.unload_context    = nv20_graph_unload_context;
 238                 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
 239                 engine->fifo.channels           = 32;
 240                 engine->fifo.init               = nv10_fifo_init;
 241                 engine->fifo.takedown           = nouveau_stub_takedown;
 242                 engine->fifo.disable            = nv04_fifo_disable;
 243                 engine->fifo.enable             = nv04_fifo_enable;
 244                 engine->fifo.reassign           = nv04_fifo_reassign;
 245                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 246                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 247                 engine->fifo.create_context     = nv10_fifo_create_context;
 248                 engine->fifo.destroy_context    = nv10_fifo_destroy_context;
 249                 engine->fifo.load_context       = nv10_fifo_load_context;
 250                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 251                 engine->display.early_init      = nv04_display_early_init;
 252                 engine->display.late_takedown   = nv04_display_late_takedown;
 253                 engine->display.create          = nv04_display_create;
 254                 engine->display.init            = nv04_display_init;
 255                 engine->display.destroy         = nv04_display_destroy;
 256                 engine->gpio.init               = nouveau_stub_init;
 257                 engine->gpio.takedown           = nouveau_stub_takedown;
 258                 engine->gpio.get                = nv10_gpio_get;
 259                 engine->gpio.set                = nv10_gpio_set;
 260                 engine->gpio.irq_enable         = NULL;
 261                 engine->pm.clock_get            = nv04_pm_clock_get;
 262                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 263                 engine->pm.clock_set            = nv04_pm_clock_set;
 264                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 265                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 266                 break;
 267         case 0x40:
 268         case 0x60:
 269                 engine->instmem.init            = nv04_instmem_init;
 270                 engine->instmem.takedown        = nv04_instmem_takedown;
 271                 engine->instmem.suspend         = nv04_instmem_suspend;
 272                 engine->instmem.resume          = nv04_instmem_resume;
 273                 engine->instmem.populate        = nv04_instmem_populate;
 274                 engine->instmem.clear           = nv04_instmem_clear;
 275                 engine->instmem.bind            = nv04_instmem_bind;
 276                 engine->instmem.unbind          = nv04_instmem_unbind;
 277                 engine->instmem.flush           = nv04_instmem_flush;
 278                 engine->mc.init                 = nv40_mc_init;
 279                 engine->mc.takedown             = nv40_mc_takedown;
 280                 engine->timer.init              = nv04_timer_init;
 281                 engine->timer.read              = nv04_timer_read;
 282                 engine->timer.takedown          = nv04_timer_takedown;
 283                 engine->fb.init                 = nv40_fb_init;
 284                 engine->fb.takedown             = nv40_fb_takedown;
 285                 engine->fb.set_region_tiling    = nv40_fb_set_region_tiling;
 286                 engine->graph.grclass           = nv40_graph_grclass;
 287                 engine->graph.init              = nv40_graph_init;
 288                 engine->graph.takedown          = nv40_graph_takedown;
 289                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 290                 engine->graph.channel           = nv40_graph_channel;
 291                 engine->graph.create_context    = nv40_graph_create_context;
 292                 engine->graph.destroy_context   = nv40_graph_destroy_context;
 293                 engine->graph.load_context      = nv40_graph_load_context;
 294                 engine->graph.unload_context    = nv40_graph_unload_context;
 295                 engine->graph.set_region_tiling = nv40_graph_set_region_tiling;
 296                 engine->fifo.channels           = 32;
 297                 engine->fifo.init               = nv40_fifo_init;
 298                 engine->fifo.takedown           = nouveau_stub_takedown;
 299                 engine->fifo.disable            = nv04_fifo_disable;
 300                 engine->fifo.enable             = nv04_fifo_enable;
 301                 engine->fifo.reassign           = nv04_fifo_reassign;
 302                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 303                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 304                 engine->fifo.create_context     = nv40_fifo_create_context;
 305                 engine->fifo.destroy_context    = nv40_fifo_destroy_context;
 306                 engine->fifo.load_context       = nv40_fifo_load_context;
 307                 engine->fifo.unload_context     = nv40_fifo_unload_context;
 308                 engine->display.early_init      = nv04_display_early_init;
 309                 engine->display.late_takedown   = nv04_display_late_takedown;
 310                 engine->display.create          = nv04_display_create;
 311                 engine->display.init            = nv04_display_init;
 312                 engine->display.destroy         = nv04_display_destroy;
 313                 engine->gpio.init               = nouveau_stub_init;
 314                 engine->gpio.takedown           = nouveau_stub_takedown;
 315                 engine->gpio.get                = nv10_gpio_get;
 316                 engine->gpio.set                = nv10_gpio_set;
 317                 engine->gpio.irq_enable         = NULL;
 318                 engine->pm.clock_get            = nv04_pm_clock_get;
 319                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 320                 engine->pm.clock_set            = nv04_pm_clock_set;
 321                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 322                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 323                 break;
 324         case 0x50:
 325         case 0x80: /* gotta love NVIDIA's consistency.. */
 326         case 0x90:
 327         case 0xA0:
 328                 engine->instmem.init            = nv50_instmem_init;
 329                 engine->instmem.takedown        = nv50_instmem_takedown;
 330                 engine->instmem.suspend         = nv50_instmem_suspend;
 331                 engine->instmem.resume          = nv50_instmem_resume;
 332                 engine->instmem.populate        = nv50_instmem_populate;
 333                 engine->instmem.clear           = nv50_instmem_clear;
 334                 engine->instmem.bind            = nv50_instmem_bind;
 335                 engine->instmem.unbind          = nv50_instmem_unbind;
 336                 if (dev_priv->chipset == 0x50)
 337                         engine->instmem.flush   = nv50_instmem_flush;
 338                 else
 339                         engine->instmem.flush   = nv84_instmem_flush;
 340                 engine->mc.init                 = nv50_mc_init;
 341                 engine->mc.takedown             = nv50_mc_takedown;
 342                 engine->timer.init              = nv04_timer_init;
 343                 engine->timer.read              = nv04_timer_read;
 344                 engine->timer.takedown          = nv04_timer_takedown;
 345                 engine->fb.init                 = nv50_fb_init;
 346                 engine->fb.takedown             = nv50_fb_takedown;
 347                 engine->graph.grclass           = nv50_graph_grclass;
 348                 engine->graph.init              = nv50_graph_init;
 349                 engine->graph.takedown          = nv50_graph_takedown;
 350                 engine->graph.fifo_access       = nv50_graph_fifo_access;
 351                 engine->graph.channel           = nv50_graph_channel;
 352                 engine->graph.create_context    = nv50_graph_create_context;
 353                 engine->graph.destroy_context   = nv50_graph_destroy_context;
 354                 engine->graph.load_context      = nv50_graph_load_context;
 355                 engine->graph.unload_context    = nv50_graph_unload_context;
 356                 engine->fifo.channels           = 128;
 357                 engine->fifo.init               = nv50_fifo_init;
 358                 engine->fifo.takedown           = nv50_fifo_takedown;
 359                 engine->fifo.disable            = nv04_fifo_disable;
 360                 engine->fifo.enable             = nv04_fifo_enable;
 361                 engine->fifo.reassign           = nv04_fifo_reassign;
 362                 engine->fifo.channel_id         = nv50_fifo_channel_id;
 363                 engine->fifo.create_context     = nv50_fifo_create_context;
 364                 engine->fifo.destroy_context    = nv50_fifo_destroy_context;
 365                 engine->fifo.load_context       = nv50_fifo_load_context;
 366                 engine->fifo.unload_context     = nv50_fifo_unload_context;
 367                 engine->display.early_init      = nv50_display_early_init;
 368                 engine->display.late_takedown   = nv50_display_late_takedown;
 369                 engine->display.create          = nv50_display_create;
 370                 engine->display.init            = nv50_display_init;
 371                 engine->display.destroy         = nv50_display_destroy;
 372                 engine->gpio.init               = nv50_gpio_init;
 373                 engine->gpio.takedown           = nouveau_stub_takedown;
 374                 engine->gpio.get                = nv50_gpio_get;
 375                 engine->gpio.set                = nv50_gpio_set;
 376                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 377                 engine->pm.clock_get            = nv50_pm_clock_get;
 378                 engine->pm.clock_pre            = nv50_pm_clock_pre;
 379                 engine->pm.clock_set            = nv50_pm_clock_set;
 380                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 381                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 382                 break;
 383         case 0xC0:
 384                 engine->instmem.init            = nvc0_instmem_init;
 385                 engine->instmem.takedown        = nvc0_instmem_takedown;
 386                 engine->instmem.suspend         = nvc0_instmem_suspend;
 387                 engine->instmem.resume          = nvc0_instmem_resume;
 388                 engine->instmem.populate        = nvc0_instmem_populate;
 389                 engine->instmem.clear           = nvc0_instmem_clear;
 390                 engine->instmem.bind            = nvc0_instmem_bind;
 391                 engine->instmem.unbind          = nvc0_instmem_unbind;
 392                 engine->instmem.flush           = nvc0_instmem_flush;
 393                 engine->mc.init                 = nv50_mc_init;
 394                 engine->mc.takedown             = nv50_mc_takedown;
 395                 engine->timer.init              = nv04_timer_init;
 396                 engine->timer.read              = nv04_timer_read;
 397                 engine->timer.takedown          = nv04_timer_takedown;
 398                 engine->fb.init                 = nvc0_fb_init;
 399                 engine->fb.takedown             = nvc0_fb_takedown;
 400                 engine->graph.grclass           = NULL;  //nvc0_graph_grclass;
 401                 engine->graph.init              = nvc0_graph_init;
 402                 engine->graph.takedown          = nvc0_graph_takedown;
 403                 engine->graph.fifo_access       = nvc0_graph_fifo_access;
 404                 engine->graph.channel           = nvc0_graph_channel;
 405                 engine->graph.create_context    = nvc0_graph_create_context;
 406                 engine->graph.destroy_context   = nvc0_graph_destroy_context;
 407                 engine->graph.load_context      = nvc0_graph_load_context;
 408                 engine->graph.unload_context    = nvc0_graph_unload_context;
 409                 engine->fifo.channels           = 128;
 410                 engine->fifo.init               = nvc0_fifo_init;
 411                 engine->fifo.takedown           = nvc0_fifo_takedown;
 412                 engine->fifo.disable            = nvc0_fifo_disable;
 413                 engine->fifo.enable             = nvc0_fifo_enable;
 414                 engine->fifo.reassign           = nvc0_fifo_reassign;
 415                 engine->fifo.channel_id         = nvc0_fifo_channel_id;
 416                 engine->fifo.create_context     = nvc0_fifo_create_context;
 417                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
 418                 engine->fifo.load_context       = nvc0_fifo_load_context;
 419                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
 420                 engine->display.early_init      = nv50_display_early_init;
 421                 engine->display.late_takedown   = nv50_display_late_takedown;
 422                 engine->display.create          = nv50_display_create;
 423                 engine->display.init            = nv50_display_init;
 424                 engine->display.destroy         = nv50_display_destroy;
 425                 engine->gpio.init               = nv50_gpio_init;
 426                 engine->gpio.takedown           = nouveau_stub_takedown;
 427                 engine->gpio.get                = nv50_gpio_get;
 428                 engine->gpio.set                = nv50_gpio_set;
 429                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 430                 break;
 431         default:
 432                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
 433                 return 1;
 434         }
 435
 436         return 0;
 437 }
 438
 439 static unsigned int
 440 nouveau_vga_set_decode(void *priv, bool state)
 441 {
 442         struct drm_device *dev = priv;
 443         struct drm_nouveau_private *dev_priv = dev->dev_private;
 444
 445         if (dev_priv->chipset >= 0x40)
 446                 nv_wr32(dev, 0x88054, state);
 447         else
 448                 nv_wr32(dev, 0x1854, state);
 449
 450         if (state)
 451                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 452                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 453         else
 454                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 455 }
 456
 457 static int
 458 nouveau_card_init_channel(struct drm_device *dev)
 459 {
 460         struct drm_nouveau_private *dev_priv = dev->dev_private;
 461         struct nouveau_gpuobj *gpuobj = NULL;
 462         int ret;
 463
 464         ret = nouveau_channel_alloc(dev, &dev_priv->channel,
 465                                     (struct drm_file *)-2, NvDmaFB, NvDmaTT);
 466         if (ret)
 467                 return ret;
 468
 469         ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
 470                                      0, dev_priv->vram_size,
 471                                      NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
 472                                      &gpuobj);
 473         if (ret)
 474                 goto out_err;
 475
 476         ret = nouveau_ramht_insert(dev_priv->channel, NvDmaVRAM, gpuobj);
 477         nouveau_gpuobj_ref(NULL, &gpuobj);
 478         if (ret)
 479                 goto out_err;
 480
 481         ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0,
 482                                           dev_priv->gart_info.aper_size,
 483                                           NV_DMA_ACCESS_RW, &gpuobj, NULL);
 484         if (ret)
 485                 goto out_err;
 486
 487         ret = nouveau_ramht_insert(dev_priv->channel, NvDmaGART, gpuobj);
 488         nouveau_gpuobj_ref(NULL, &gpuobj);
 489         if (ret)
 490                 goto out_err;
 491
 492         return 0;
 493
 494 out_err:
 495         nouveau_channel_free(dev_priv->channel);
 496         dev_priv->channel = NULL;
 497         return ret;
 498 }
 499
 500 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
 501                                          enum vga_switcheroo_state state)
 502 {
 503         struct drm_device *dev = pci_get_drvdata(pdev);
 504         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 505         if (state == VGA_SWITCHEROO_ON) {
 506                 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
 507                 nouveau_pci_resume(pdev);
 508                 drm_kms_helper_poll_enable(dev);
 509         } else {
 510                 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
 511                 drm_kms_helper_poll_disable(dev);
 512                 nouveau_pci_suspend(pdev, pmm);
 513         }
 514 }
 515
 516 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
 517 {
 518         struct drm_device *dev = pci_get_drvdata(pdev);
 519         bool can_switch;
 520
 521         spin_lock(&dev->count_lock);
 522         can_switch = (dev->open_count == 0);
 523         spin_unlock(&dev->count_lock);
 524         return can_switch;
 525 }
 526
 527 int
 528 nouveau_card_init(struct drm_device *dev)
 529 {
 530         struct drm_nouveau_private *dev_priv = dev->dev_private;
 531         struct nouveau_engine *engine;
 532         int ret;
 533
 534         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
 535         vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
 536                                        nouveau_switcheroo_can_switch);
 537
 538         /* Initialise internal driver API hooks */
 539         ret = nouveau_init_engine_ptrs(dev);
 540         if (ret)
 541                 goto out;
 542         engine = &dev_priv->engine;
 543         spin_lock_init(&dev_priv->context_switch_lock);
 544
 545         /* Make the CRTCs and I2C buses accessible */
 546         ret = engine->display.early_init(dev);
 547         if (ret)
 548                 goto out;
 549
 550         /* Parse BIOS tables / Run init tables if card not POSTed */
 551         ret = nouveau_bios_init(dev);
 552         if (ret)
 553                 goto out_display_early;
 554
 555         nouveau_pm_init(dev);
 556
 557         ret = nouveau_mem_vram_init(dev);
 558         if (ret)
 559                 goto out_bios;
 560
 561         ret = nouveau_gpuobj_init(dev);
 562         if (ret)
 563                 goto out_vram;
 564
 565         ret = engine->instmem.init(dev);
 566         if (ret)
 567                 goto out_gpuobj;
 568
 569         ret = nouveau_mem_gart_init(dev);
 570         if (ret)
 571                 goto out_instmem;
 572
 573         /* PMC */
 574         ret = engine->mc.init(dev);
 575         if (ret)
 576                 goto out_gart;
 577
 578         /* PGPIO */
 579         ret = engine->gpio.init(dev);
 580         if (ret)
 581                 goto out_mc;
 582
 583         /* PTIMER */
 584         ret = engine->timer.init(dev);
 585         if (ret)
 586                 goto out_gpio;
 587
 588         /* PFB */
 589         ret = engine->fb.init(dev);
 590         if (ret)
 591                 goto out_timer;
 592
 593         if (nouveau_noaccel)
 594                 engine->graph.accel_blocked = true;
 595         else {
 596                 /* PGRAPH */
 597                 ret = engine->graph.init(dev);
 598                 if (ret)
 599                         goto out_fb;
 600
 601                 /* PFIFO */
 602                 ret = engine->fifo.init(dev);
 603                 if (ret)
 604                         goto out_graph;
 605         }
 606
 607         ret = engine->display.create(dev);
 608         if (ret)
 609                 goto out_fifo;
 610
 611         /* this call irq_preinstall, register irq handler and
 612          * call irq_postinstall
 613          */
 614         ret = drm_irq_install(dev);
 615         if (ret)
 616                 goto out_display;
 617
 618         ret = drm_vblank_init(dev, 0);
 619         if (ret)
 620                 goto out_irq;
 621
 622         /* what about PVIDEO/PCRTC/PRAMDAC etc? */
 623
 624         if (!engine->graph.accel_blocked) {
 625                 ret = nouveau_card_init_channel(dev);
 626                 if (ret)
 627                         goto out_irq;
 628         }
 629
 630         ret = nouveau_backlight_init(dev);
 631         if (ret)
 632                 NV_ERROR(dev, "Error %d registering backlight\n", ret);
 633
 634         nouveau_fbcon_init(dev);
 635         drm_kms_helper_poll_init(dev);
 636         return 0;
 637
 638 out_irq:
 639         drm_irq_uninstall(dev);
 640 out_display:
 641         engine->display.destroy(dev);
 642 out_fifo:
 643         if (!nouveau_noaccel)
 644                 engine->fifo.takedown(dev);
 645 out_graph:
 646         if (!nouveau_noaccel)
 647                 engine->graph.takedown(dev);
 648 out_fb:
 649         engine->fb.takedown(dev);
 650 out_timer:
 651         engine->timer.takedown(dev);
 652 out_gpio:
 653         engine->gpio.takedown(dev);
 654 out_mc:
 655         engine->mc.takedown(dev);
 656 out_gart:
 657         nouveau_mem_gart_fini(dev);
 658 out_instmem:
 659         engine->instmem.takedown(dev);
 660 out_gpuobj:
 661         nouveau_gpuobj_takedown(dev);
 662 out_vram:
 663         nouveau_mem_vram_fini(dev);
 664 out_bios:
 665         nouveau_pm_fini(dev);
 666         nouveau_bios_takedown(dev);
 667 out_display_early:
 668         engine->display.late_takedown(dev);
 669 out:
 670         vga_client_register(dev->pdev, NULL, NULL, NULL);
 671         return ret;
 672 }
 673
 674 static void nouveau_card_takedown(struct drm_device *dev)
 675 {
 676         struct drm_nouveau_private *dev_priv = dev->dev_private;
 677         struct nouveau_engine *engine = &dev_priv->engine;
 678
 679         nouveau_backlight_exit(dev);
 680
 681         if (dev_priv->channel) {
 682                 nouveau_channel_free(dev_priv->channel);
 683                 dev_priv->channel = NULL;
 684         }
 685
 686         if (!nouveau_noaccel) {
 687                 engine->fifo.takedown(dev);
 688                 engine->graph.takedown(dev);
 689         }
 690         engine->fb.takedown(dev);
 691         engine->timer.takedown(dev);
 692         engine->gpio.takedown(dev);
 693         engine->mc.takedown(dev);
 694         engine->display.late_takedown(dev);
 695
 696         mutex_lock(&dev->struct_mutex);
 697         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
 698         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
 699         mutex_unlock(&dev->struct_mutex);
 700         nouveau_mem_gart_fini(dev);
 701
 702         engine->instmem.takedown(dev);
 703         nouveau_gpuobj_takedown(dev);
 704         nouveau_mem_vram_fini(dev);
 705
 706         drm_irq_uninstall(dev);
 707
 708         nouveau_pm_fini(dev);
 709         nouveau_bios_takedown(dev);
 710
 711         vga_client_register(dev->pdev, NULL, NULL, NULL);
 712 }
 713
 714 /* here a client dies, release the stuff that was allocated for its
 715  * file_priv */
 716 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
 717 {
 718         nouveau_channel_cleanup(dev, file_priv);
 719 }
 720
 721 /* first module load, setup the mmio/fb mapping */
 722 /* KMS: we need mmio at load time, not when the first drm client opens. */
 723 int nouveau_firstopen(struct drm_device *dev)
 724 {
 725         return 0;
 726 }
 727
 728 /* if we have an OF card, copy vbios to RAMIN */
 729 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
 730 {
 731 #if defined(__powerpc__)
 732         int size, i;
 733         const uint32_t *bios;
 734         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
 735         if (!dn) {
 736                 NV_INFO(dev, "Unable to get the OF node\n");
 737                 return;
 738         }
 739
 740         bios = of_get_property(dn, "NVDA,BMP", &size);
 741         if (bios) {
 742                 for (i = 0; i < size; i += 4)
 743                         nv_wi32(dev, i, bios[i/4]);
 744                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
 745         } else {
 746                 NV_INFO(dev, "Unable to get the OF bios\n");
 747         }
 748 #endif
 749 }
 750
 751 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
 752 {
 753         struct pci_dev *pdev = dev->pdev;
 754         struct apertures_struct *aper = alloc_apertures(3);
 755         if (!aper)
 756                 return NULL;
 757
 758         aper->ranges[0].base = pci_resource_start(pdev, 1);
 759         aper->ranges[0].size = pci_resource_len(pdev, 1);
 760         aper->count = 1;
 761
 762         if (pci_resource_len(pdev, 2)) {
 763                 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
 764                 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
 765                 aper->count++;
 766         }
 767
 768         if (pci_resource_len(pdev, 3)) {
 769                 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
 770                 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
 771                 aper->count++;
 772         }
 773
 774         return aper;
 775 }
 776
 777 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
 778 {
 779         struct drm_nouveau_private *dev_priv = dev->dev_private;
 780         bool primary = false;
 781         dev_priv->apertures = nouveau_get_apertures(dev);
 782         if (!dev_priv->apertures)
 783                 return -ENOMEM;
 784
 785 #ifdef CONFIG_X86
 786         primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 787 #endif
 788
 789         remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
 790         return 0;
 791 }
 792
 793 int nouveau_load(struct drm_device *dev, unsigned long flags)
 794 {
 795         struct drm_nouveau_private *dev_priv;
 796         uint32_t reg0;
 797         resource_size_t mmio_start_offs;
 798         int ret;
 799
 800         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 801         if (!dev_priv) {
 802                 ret = -ENOMEM;
 803                 goto err_out;
 804         }
 805         dev->dev_private = dev_priv;
 806         dev_priv->dev = dev;
 807
 808         dev_priv->flags = flags & NOUVEAU_FLAGS;
 809
 810         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
 811                  dev->pci_vendor, dev->pci_device, dev->pdev->class);
 812
 813         dev_priv->wq = create_workqueue("nouveau");
 814         if (!dev_priv->wq) {
 815                 ret = -EINVAL;
 816                 goto err_priv;
 817         }
 818
 819         /* resource 0 is mmio regs */
 820         /* resource 1 is linear FB */
 821         /* resource 2 is RAMIN (mmio regs + 0x1000000) */
 822         /* resource 6 is bios */
 823
 824         /* map the mmio regs */
 825         mmio_start_offs = pci_resource_start(dev->pdev, 0);
 826         dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
 827         if (!dev_priv->mmio) {
 828                 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
 829                          "Please report your setup to " DRIVER_EMAIL "\n");
 830                 ret = -EINVAL;
 831                 goto err_wq;
 832         }
 833         NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
 834                                         (unsigned long long)mmio_start_offs);
 835
 836 #ifdef __BIG_ENDIAN
 837         /* Put the card in BE mode if it's not */
 838         if (nv_rd32(dev, NV03_PMC_BOOT_1))
 839                 nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
 840
 841         DRM_MEMORYBARRIER();
 842 #endif
 843
 844         /* Time to determine the card architecture */
 845         reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
 846
 847         /* We're dealing with >=NV10 */
 848         if ((reg0 & 0x0f000000) > 0) {
 849                 /* Bit 27-20 contain the architecture in hex */
 850                 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
 851         /* NV04 or NV05 */
 852         } else if ((reg0 & 0xff00fff0) == 0x20004000) {
 853                 if (reg0 & 0x00f00000)
 854                         dev_priv->chipset = 0x05;
 855                 else
 856                         dev_priv->chipset = 0x04;
 857         } else
 858                 dev_priv->chipset = 0xff;
 859
 860         switch (dev_priv->chipset & 0xf0) {
 861         case 0x00:
 862         case 0x10:
 863         case 0x20:
 864         case 0x30:
 865                 dev_priv->card_type = dev_priv->chipset & 0xf0;
 866                 break;
 867         case 0x40:
 868         case 0x60:
 869                 dev_priv->card_type = NV_40;
 870                 break;
 871         case 0x50:
 872         case 0x80:
 873         case 0x90:
 874         case 0xa0:
 875                 dev_priv->card_type = NV_50;
 876                 break;
 877         case 0xc0:
 878                 dev_priv->card_type = NV_C0;
 879                 break;
 880         default:
 881                 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
 882                 ret = -EINVAL;
 883                 goto err_mmio;
 884         }
 885
 886         NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
 887                 dev_priv->card_type, reg0);
 888
 889         ret = nouveau_remove_conflicting_drivers(dev);
 890         if (ret)
 891                 goto err_mmio;
 892
 893         /* Map PRAMIN BAR, or on older cards, the aperture withing BAR0 */
 894         if (dev_priv->card_type >= NV_40) {
 895                 int ramin_bar = 2;
 896                 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
 897                         ramin_bar = 3;
 898
 899                 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
 900                 dev_priv->ramin =
 901                         ioremap(pci_resource_start(dev->pdev, ramin_bar),
 902                                 dev_priv->ramin_size);
 903                 if (!dev_priv->ramin) {
 904                         NV_ERROR(dev, "Failed to PRAMIN BAR");
 905                         ret = -ENOMEM;
 906                         goto err_mmio;
 907                 }
 908         } else {
 909                 dev_priv->ramin_size = 1 * 1024 * 1024;
 910                 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
 911                                           dev_priv->ramin_size);
 912                 if (!dev_priv->ramin) {
 913                         NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
 914                         ret = -ENOMEM;
 915                         goto err_mmio;
 916                 }
 917         }
 918
 919         nouveau_OF_copy_vbios_to_ramin(dev);
 920
 921         /* Special flags */
 922         if (dev->pci_device == 0x01a0)
 923                 dev_priv->flags |= NV_NFORCE;
 924         else if (dev->pci_device == 0x01f0)
 925                 dev_priv->flags |= NV_NFORCE2;
 926
 927         /* For kernel modesetting, init card now and bring up fbcon */
 928         ret = nouveau_card_init(dev);
 929         if (ret)
 930                 goto err_ramin;
 931
 932         return 0;
 933
 934 err_ramin:
 935         iounmap(dev_priv->ramin);
 936 err_mmio:
 937         iounmap(dev_priv->mmio);
 938 err_wq:
 939         destroy_workqueue(dev_priv->wq);
 940 err_priv:
 941         kfree(dev_priv);
 942         dev->dev_private = NULL;
 943 err_out:
 944         return ret;
 945 }
 946
 947 void nouveau_lastclose(struct drm_device *dev)
 948 {
 949 }
 950
 951 int nouveau_unload(struct drm_device *dev)
 952 {
 953         struct drm_nouveau_private *dev_priv = dev->dev_private;
 954         struct nouveau_engine *engine = &dev_priv->engine;
 955
 956         drm_kms_helper_poll_fini(dev);
 957         nouveau_fbcon_fini(dev);
 958         engine->display.destroy(dev);
 959         nouveau_card_takedown(dev);
 960
 961         iounmap(dev_priv->mmio);
 962         iounmap(dev_priv->ramin);
 963
 964         kfree(dev_priv);
 965         dev->dev_private = NULL;
 966         return 0;
 967 }
 968
 969 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
 970                                                 struct drm_file *file_priv)
 971 {
 972         struct drm_nouveau_private *dev_priv = dev->dev_private;
 973         struct drm_nouveau_getparam *getparam = data;
 974
 975         switch (getparam->param) {
 976         case NOUVEAU_GETPARAM_CHIPSET_ID:
 977                 getparam->value = dev_priv->chipset;
 978                 break;
 979         case NOUVEAU_GETPARAM_PCI_VENDOR:
 980                 getparam->value = dev->pci_vendor;
 981                 break;
 982         case NOUVEAU_GETPARAM_PCI_DEVICE:
 983                 getparam->value = dev->pci_device;
 984                 break;
 985         case NOUVEAU_GETPARAM_BUS_TYPE:
 986                 if (drm_device_is_agp(dev))
 987                         getparam->value = NV_AGP;
 988                 else if (drm_device_is_pcie(dev))
 989                         getparam->value = NV_PCIE;
 990                 else
 991                         getparam->value = NV_PCI;
 992                 break;
 993         case NOUVEAU_GETPARAM_FB_PHYSICAL:
 994                 getparam->value = dev_priv->fb_phys;
 995                 break;
 996         case NOUVEAU_GETPARAM_AGP_PHYSICAL:
 997                 getparam->value = dev_priv->gart_info.aper_base;
 998                 break;
 999         case NOUVEAU_GETPARAM_PCI_PHYSICAL:
1000                 if (dev->sg) {
1001                         getparam->value = (unsigned long)dev->sg->virtual;
1002                 } else {
1003                         NV_ERROR(dev, "Requested PCIGART address, "
1004                                         "while no PCIGART was created\n");
1005                         return -EINVAL;
1006                 }
1007                 break;
1008         case NOUVEAU_GETPARAM_FB_SIZE:
1009                 getparam->value = dev_priv->fb_available_size;
1010                 break;
1011         case NOUVEAU_GETPARAM_AGP_SIZE:
1012                 getparam->value = dev_priv->gart_info.aper_size;
1013                 break;
1014         case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1015                 getparam->value = dev_priv->vm_vram_base;
1016                 break;
1017         case NOUVEAU_GETPARAM_PTIMER_TIME:
1018                 getparam->value = dev_priv->engine.timer.read(dev);
1019                 break;
1020         case NOUVEAU_GETPARAM_GRAPH_UNITS:
1021                 /* NV40 and NV50 versions are quite different, but register
1022                  * address is the same. User is supposed to know the card
1023                  * family anyway... */
1024                 if (dev_priv->chipset >= 0x40) {
1025                         getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1026                         break;
1027                 }
1028                 /* FALLTHRU */
1029         default:
1030                 NV_ERROR(dev, "unknown parameter %lld\n", getparam->param);
1031                 return -EINVAL;
1032         }
1033
1034         return 0;
1035 }
1036
1037 int
1038 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1039                        struct drm_file *file_priv)
1040 {
1041         struct drm_nouveau_setparam *setparam = data;
1042
1043         switch (setparam->param) {
1044         default:
1045                 NV_ERROR(dev, "unknown parameter %lld\n", setparam->param);
1046                 return -EINVAL;
1047         }
1048
1049         return 0;
1050 }
1051
1052 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1053 bool nouveau_wait_until(struct drm_device *dev, uint64_t timeout,
1054                         uint32_t reg, uint32_t mask, uint32_t val)
1055 {
1056         struct drm_nouveau_private *dev_priv = dev->dev_private;
1057         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1058         uint64_t start = ptimer->read(dev);
1059
1060         do {
1061                 if ((nv_rd32(dev, reg) & mask) == val)
1062                         return true;
1063         } while (ptimer->read(dev) - start < timeout);
1064
1065         return false;
1066 }
1067
1068 /* Waits for PGRAPH to go completely idle */
1069 bool nouveau_wait_for_idle(struct drm_device *dev)
1070 {
1071         if (!nv_wait(dev, NV04_PGRAPH_STATUS, 0xffffffff, 0x00000000)) {
1072                 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1073                          nv_rd32(dev, NV04_PGRAPH_STATUS));
1074                 return false;
1075         }
1076
1077         return true;
1078 }
1079