drivers/gpu/drm/nouveau/nouveau_state.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin
   3  * Copyright 2008 Stuart Bennett
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include <linux/swab.h>
  27 #include <linux/slab.h>
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "drm_sarea.h"
  31 #include "drm_crtc_helper.h"
  32 #include <linux/vgaarb.h>
  33 #include <linux/vga_switcheroo.h>
  34
  35 #include "nouveau_drv.h"
  36 #include "nouveau_drm.h"
  37 #include "nouveau_fbcon.h"
  38 #include "nouveau_ramht.h"
  39 #include "nv50_display.h"
  40
  41 static void nouveau_stub_takedown(struct drm_device *dev) {}
  42 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
  43
  44 static int nouveau_init_engine_ptrs(struct drm_device *dev)
  45 {
  46         struct drm_nouveau_private *dev_priv = dev->dev_private;
  47         struct nouveau_engine *engine = &dev_priv->engine;
  48
  49         switch (dev_priv->chipset & 0xf0) {
  50         case 0x00:
  51                 engine->instmem.init            = nv04_instmem_init;
  52                 engine->instmem.takedown        = nv04_instmem_takedown;
  53                 engine->instmem.suspend         = nv04_instmem_suspend;
  54                 engine->instmem.resume          = nv04_instmem_resume;
  55                 engine->instmem.populate        = nv04_instmem_populate;
  56                 engine->instmem.clear           = nv04_instmem_clear;
  57                 engine->instmem.bind            = nv04_instmem_bind;
  58                 engine->instmem.unbind          = nv04_instmem_unbind;
  59                 engine->instmem.flush           = nv04_instmem_flush;
  60                 engine->mc.init                 = nv04_mc_init;
  61                 engine->mc.takedown             = nv04_mc_takedown;
  62                 engine->timer.init              = nv04_timer_init;
  63                 engine->timer.read              = nv04_timer_read;
  64                 engine->timer.takedown          = nv04_timer_takedown;
  65                 engine->fb.init                 = nv04_fb_init;
  66                 engine->fb.takedown             = nv04_fb_takedown;
  67                 engine->graph.grclass           = nv04_graph_grclass;
  68                 engine->graph.init              = nv04_graph_init;
  69                 engine->graph.takedown          = nv04_graph_takedown;
  70                 engine->graph.fifo_access       = nv04_graph_fifo_access;
  71                 engine->graph.channel           = nv04_graph_channel;
  72                 engine->graph.create_context    = nv04_graph_create_context;
  73                 engine->graph.destroy_context   = nv04_graph_destroy_context;
  74                 engine->graph.load_context      = nv04_graph_load_context;
  75                 engine->graph.unload_context    = nv04_graph_unload_context;
  76                 engine->fifo.channels           = 16;
  77                 engine->fifo.init               = nv04_fifo_init;
  78                 engine->fifo.takedown           = nouveau_stub_takedown;
  79                 engine->fifo.disable            = nv04_fifo_disable;
  80                 engine->fifo.enable             = nv04_fifo_enable;
  81                 engine->fifo.reassign           = nv04_fifo_reassign;
  82                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
  83                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
  84                 engine->fifo.channel_id         = nv04_fifo_channel_id;
  85                 engine->fifo.create_context     = nv04_fifo_create_context;
  86                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
  87                 engine->fifo.load_context       = nv04_fifo_load_context;
  88                 engine->fifo.unload_context     = nv04_fifo_unload_context;
  89                 engine->display.early_init      = nv04_display_early_init;
  90                 engine->display.late_takedown   = nv04_display_late_takedown;
  91                 engine->display.create          = nv04_display_create;
  92                 engine->display.init            = nv04_display_init;
  93                 engine->display.destroy         = nv04_display_destroy;
  94                 engine->gpio.init               = nouveau_stub_init;
  95                 engine->gpio.takedown           = nouveau_stub_takedown;
  96                 engine->gpio.get                = NULL;
  97                 engine->gpio.set                = NULL;
  98                 engine->gpio.irq_enable         = NULL;
  99                 break;
 100         case 0x10:
 101                 engine->instmem.init            = nv04_instmem_init;
 102                 engine->instmem.takedown        = nv04_instmem_takedown;
 103                 engine->instmem.suspend         = nv04_instmem_suspend;
 104                 engine->instmem.resume          = nv04_instmem_resume;
 105                 engine->instmem.populate        = nv04_instmem_populate;
 106                 engine->instmem.clear           = nv04_instmem_clear;
 107                 engine->instmem.bind            = nv04_instmem_bind;
 108                 engine->instmem.unbind          = nv04_instmem_unbind;
 109                 engine->instmem.flush           = nv04_instmem_flush;
 110                 engine->mc.init                 = nv04_mc_init;
 111                 engine->mc.takedown             = nv04_mc_takedown;
 112                 engine->timer.init              = nv04_timer_init;
 113                 engine->timer.read              = nv04_timer_read;
 114                 engine->timer.takedown          = nv04_timer_takedown;
 115                 engine->fb.init                 = nv10_fb_init;
 116                 engine->fb.takedown             = nv10_fb_takedown;
 117                 engine->fb.set_region_tiling    = nv10_fb_set_region_tiling;
 118                 engine->graph.grclass           = nv10_graph_grclass;
 119                 engine->graph.init              = nv10_graph_init;
 120                 engine->graph.takedown          = nv10_graph_takedown;
 121                 engine->graph.channel           = nv10_graph_channel;
 122                 engine->graph.create_context    = nv10_graph_create_context;
 123                 engine->graph.destroy_context   = nv10_graph_destroy_context;
 124                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 125                 engine->graph.load_context      = nv10_graph_load_context;
 126                 engine->graph.unload_context    = nv10_graph_unload_context;
 127                 engine->graph.set_region_tiling = nv10_graph_set_region_tiling;
 128                 engine->fifo.channels           = 32;
 129                 engine->fifo.init               = nv10_fifo_init;
 130                 engine->fifo.takedown           = nouveau_stub_takedown;
 131                 engine->fifo.disable            = nv04_fifo_disable;
 132                 engine->fifo.enable             = nv04_fifo_enable;
 133                 engine->fifo.reassign           = nv04_fifo_reassign;
 134                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
 135                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 136                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 137                 engine->fifo.create_context     = nv10_fifo_create_context;
 138                 engine->fifo.destroy_context    = nv10_fifo_destroy_context;
 139                 engine->fifo.load_context       = nv10_fifo_load_context;
 140                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 141                 engine->display.early_init      = nv04_display_early_init;
 142                 engine->display.late_takedown   = nv04_display_late_takedown;
 143                 engine->display.create          = nv04_display_create;
 144                 engine->display.init            = nv04_display_init;
 145                 engine->display.destroy         = nv04_display_destroy;
 146                 engine->gpio.init               = nouveau_stub_init;
 147                 engine->gpio.takedown           = nouveau_stub_takedown;
 148                 engine->gpio.get                = nv10_gpio_get;
 149                 engine->gpio.set                = nv10_gpio_set;
 150                 engine->gpio.irq_enable         = NULL;
 151                 break;
 152         case 0x20:
 153                 engine->instmem.init            = nv04_instmem_init;
 154                 engine->instmem.takedown        = nv04_instmem_takedown;
 155                 engine->instmem.suspend         = nv04_instmem_suspend;
 156                 engine->instmem.resume          = nv04_instmem_resume;
 157                 engine->instmem.populate        = nv04_instmem_populate;
 158                 engine->instmem.clear           = nv04_instmem_clear;
 159                 engine->instmem.bind            = nv04_instmem_bind;
 160                 engine->instmem.unbind          = nv04_instmem_unbind;
 161                 engine->instmem.flush           = nv04_instmem_flush;
 162                 engine->mc.init                 = nv04_mc_init;
 163                 engine->mc.takedown             = nv04_mc_takedown;
 164                 engine->timer.init              = nv04_timer_init;
 165                 engine->timer.read              = nv04_timer_read;
 166                 engine->timer.takedown          = nv04_timer_takedown;
 167                 engine->fb.init                 = nv10_fb_init;
 168                 engine->fb.takedown             = nv10_fb_takedown;
 169                 engine->fb.set_region_tiling    = nv10_fb_set_region_tiling;
 170                 engine->graph.grclass           = nv20_graph_grclass;
 171                 engine->graph.init              = nv20_graph_init;
 172                 engine->graph.takedown          = nv20_graph_takedown;
 173                 engine->graph.channel           = nv10_graph_channel;
 174                 engine->graph.create_context    = nv20_graph_create_context;
 175                 engine->graph.destroy_context   = nv20_graph_destroy_context;
 176                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 177                 engine->graph.load_context      = nv20_graph_load_context;
 178                 engine->graph.unload_context    = nv20_graph_unload_context;
 179                 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
 180                 engine->fifo.channels           = 32;
 181                 engine->fifo.init               = nv10_fifo_init;
 182                 engine->fifo.takedown           = nouveau_stub_takedown;
 183                 engine->fifo.disable            = nv04_fifo_disable;
 184                 engine->fifo.enable             = nv04_fifo_enable;
 185                 engine->fifo.reassign           = nv04_fifo_reassign;
 186                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
 187                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 188                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 189                 engine->fifo.create_context     = nv10_fifo_create_context;
 190                 engine->fifo.destroy_context    = nv10_fifo_destroy_context;
 191                 engine->fifo.load_context       = nv10_fifo_load_context;
 192                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 193                 engine->display.early_init      = nv04_display_early_init;
 194                 engine->display.late_takedown   = nv04_display_late_takedown;
 195                 engine->display.create          = nv04_display_create;
 196                 engine->display.init            = nv04_display_init;
 197                 engine->display.destroy         = nv04_display_destroy;
 198                 engine->gpio.init               = nouveau_stub_init;
 199                 engine->gpio.takedown           = nouveau_stub_takedown;
 200                 engine->gpio.get                = nv10_gpio_get;
 201                 engine->gpio.set                = nv10_gpio_set;
 202                 engine->gpio.irq_enable         = NULL;
 203                 break;
 204         case 0x30:
 205                 engine->instmem.init            = nv04_instmem_init;
 206                 engine->instmem.takedown        = nv04_instmem_takedown;
 207                 engine->instmem.suspend         = nv04_instmem_suspend;
 208                 engine->instmem.resume          = nv04_instmem_resume;
 209                 engine->instmem.populate        = nv04_instmem_populate;
 210                 engine->instmem.clear           = nv04_instmem_clear;
 211                 engine->instmem.bind            = nv04_instmem_bind;
 212                 engine->instmem.unbind          = nv04_instmem_unbind;
 213                 engine->instmem.flush           = nv04_instmem_flush;
 214                 engine->mc.init                 = nv04_mc_init;
 215                 engine->mc.takedown             = nv04_mc_takedown;
 216                 engine->timer.init              = nv04_timer_init;
 217                 engine->timer.read              = nv04_timer_read;
 218                 engine->timer.takedown          = nv04_timer_takedown;
 219                 engine->fb.init                 = nv30_fb_init;
 220                 engine->fb.takedown             = nv30_fb_takedown;
 221                 engine->fb.set_region_tiling    = nv10_fb_set_region_tiling;
 222                 engine->graph.grclass           = nv30_graph_grclass;
 223                 engine->graph.init              = nv30_graph_init;
 224                 engine->graph.takedown          = nv20_graph_takedown;
 225                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 226                 engine->graph.channel           = nv10_graph_channel;
 227                 engine->graph.create_context    = nv20_graph_create_context;
 228                 engine->graph.destroy_context   = nv20_graph_destroy_context;
 229                 engine->graph.load_context      = nv20_graph_load_context;
 230                 engine->graph.unload_context    = nv20_graph_unload_context;
 231                 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
 232                 engine->fifo.channels           = 32;
 233                 engine->fifo.init               = nv10_fifo_init;
 234                 engine->fifo.takedown           = nouveau_stub_takedown;
 235                 engine->fifo.disable            = nv04_fifo_disable;
 236                 engine->fifo.enable             = nv04_fifo_enable;
 237                 engine->fifo.reassign           = nv04_fifo_reassign;
 238                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
 239                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 240                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 241                 engine->fifo.create_context     = nv10_fifo_create_context;
 242                 engine->fifo.destroy_context    = nv10_fifo_destroy_context;
 243                 engine->fifo.load_context       = nv10_fifo_load_context;
 244                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 245                 engine->display.early_init      = nv04_display_early_init;
 246                 engine->display.late_takedown   = nv04_display_late_takedown;
 247                 engine->display.create          = nv04_display_create;
 248                 engine->display.init            = nv04_display_init;
 249                 engine->display.destroy         = nv04_display_destroy;
 250                 engine->gpio.init               = nouveau_stub_init;
 251                 engine->gpio.takedown           = nouveau_stub_takedown;
 252                 engine->gpio.get                = nv10_gpio_get;
 253                 engine->gpio.set                = nv10_gpio_set;
 254                 engine->gpio.irq_enable         = NULL;
 255                 break;
 256         case 0x40:
 257         case 0x60:
 258                 engine->instmem.init            = nv04_instmem_init;
 259                 engine->instmem.takedown        = nv04_instmem_takedown;
 260                 engine->instmem.suspend         = nv04_instmem_suspend;
 261                 engine->instmem.resume          = nv04_instmem_resume;
 262                 engine->instmem.populate        = nv04_instmem_populate;
 263                 engine->instmem.clear           = nv04_instmem_clear;
 264                 engine->instmem.bind            = nv04_instmem_bind;
 265                 engine->instmem.unbind          = nv04_instmem_unbind;
 266                 engine->instmem.flush           = nv04_instmem_flush;
 267                 engine->mc.init                 = nv40_mc_init;
 268                 engine->mc.takedown             = nv40_mc_takedown;
 269                 engine->timer.init              = nv04_timer_init;
 270                 engine->timer.read              = nv04_timer_read;
 271                 engine->timer.takedown          = nv04_timer_takedown;
 272                 engine->fb.init                 = nv40_fb_init;
 273                 engine->fb.takedown             = nv40_fb_takedown;
 274                 engine->fb.set_region_tiling    = nv40_fb_set_region_tiling;
 275                 engine->graph.grclass           = nv40_graph_grclass;
 276                 engine->graph.init              = nv40_graph_init;
 277                 engine->graph.takedown          = nv40_graph_takedown;
 278                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 279                 engine->graph.channel           = nv40_graph_channel;
 280                 engine->graph.create_context    = nv40_graph_create_context;
 281                 engine->graph.destroy_context   = nv40_graph_destroy_context;
 282                 engine->graph.load_context      = nv40_graph_load_context;
 283                 engine->graph.unload_context    = nv40_graph_unload_context;
 284                 engine->graph.set_region_tiling = nv40_graph_set_region_tiling;
 285                 engine->fifo.channels           = 32;
 286                 engine->fifo.init               = nv40_fifo_init;
 287                 engine->fifo.takedown           = nouveau_stub_takedown;
 288                 engine->fifo.disable            = nv04_fifo_disable;
 289                 engine->fifo.enable             = nv04_fifo_enable;
 290                 engine->fifo.reassign           = nv04_fifo_reassign;
 291                 engine->fifo.cache_flush        = nv04_fifo_cache_flush;
 292                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 293                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 294                 engine->fifo.create_context     = nv40_fifo_create_context;
 295                 engine->fifo.destroy_context    = nv40_fifo_destroy_context;
 296                 engine->fifo.load_context       = nv40_fifo_load_context;
 297                 engine->fifo.unload_context     = nv40_fifo_unload_context;
 298                 engine->display.early_init      = nv04_display_early_init;
 299                 engine->display.late_takedown   = nv04_display_late_takedown;
 300                 engine->display.create          = nv04_display_create;
 301                 engine->display.init            = nv04_display_init;
 302                 engine->display.destroy         = nv04_display_destroy;
 303                 engine->gpio.init               = nouveau_stub_init;
 304                 engine->gpio.takedown           = nouveau_stub_takedown;
 305                 engine->gpio.get                = nv10_gpio_get;
 306                 engine->gpio.set                = nv10_gpio_set;
 307                 engine->gpio.irq_enable         = NULL;
 308                 break;
 309         case 0x50:
 310         case 0x80: /* gotta love NVIDIA's consistency.. */
 311         case 0x90:
 312         case 0xA0:
 313                 engine->instmem.init            = nv50_instmem_init;
 314                 engine->instmem.takedown        = nv50_instmem_takedown;
 315                 engine->instmem.suspend         = nv50_instmem_suspend;
 316                 engine->instmem.resume          = nv50_instmem_resume;
 317                 engine->instmem.populate        = nv50_instmem_populate;
 318                 engine->instmem.clear           = nv50_instmem_clear;
 319                 engine->instmem.bind            = nv50_instmem_bind;
 320                 engine->instmem.unbind          = nv50_instmem_unbind;
 321                 if (dev_priv->chipset == 0x50)
 322                         engine->instmem.flush   = nv50_instmem_flush;
 323                 else
 324                         engine->instmem.flush   = nv84_instmem_flush;
 325                 engine->mc.init                 = nv50_mc_init;
 326                 engine->mc.takedown             = nv50_mc_takedown;
 327                 engine->timer.init              = nv04_timer_init;
 328                 engine->timer.read              = nv04_timer_read;
 329                 engine->timer.takedown          = nv04_timer_takedown;
 330                 engine->fb.init                 = nv50_fb_init;
 331                 engine->fb.takedown             = nv50_fb_takedown;
 332                 engine->graph.grclass           = nv50_graph_grclass;
 333                 engine->graph.init              = nv50_graph_init;
 334                 engine->graph.takedown          = nv50_graph_takedown;
 335                 engine->graph.fifo_access       = nv50_graph_fifo_access;
 336                 engine->graph.channel           = nv50_graph_channel;
 337                 engine->graph.create_context    = nv50_graph_create_context;
 338                 engine->graph.destroy_context   = nv50_graph_destroy_context;
 339                 engine->graph.load_context      = nv50_graph_load_context;
 340                 engine->graph.unload_context    = nv50_graph_unload_context;
 341                 engine->fifo.channels           = 128;
 342                 engine->fifo.init               = nv50_fifo_init;
 343                 engine->fifo.takedown           = nv50_fifo_takedown;
 344                 engine->fifo.disable            = nv04_fifo_disable;
 345                 engine->fifo.enable             = nv04_fifo_enable;
 346                 engine->fifo.reassign           = nv04_fifo_reassign;
 347                 engine->fifo.channel_id         = nv50_fifo_channel_id;
 348                 engine->fifo.create_context     = nv50_fifo_create_context;
 349                 engine->fifo.destroy_context    = nv50_fifo_destroy_context;
 350                 engine->fifo.load_context       = nv50_fifo_load_context;
 351                 engine->fifo.unload_context     = nv50_fifo_unload_context;
 352                 engine->display.early_init      = nv50_display_early_init;
 353                 engine->display.late_takedown   = nv50_display_late_takedown;
 354                 engine->display.create          = nv50_display_create;
 355                 engine->display.init            = nv50_display_init;
 356                 engine->display.destroy         = nv50_display_destroy;
 357                 engine->gpio.init               = nv50_gpio_init;
 358                 engine->gpio.takedown           = nouveau_stub_takedown;
 359                 engine->gpio.get                = nv50_gpio_get;
 360                 engine->gpio.set                = nv50_gpio_set;
 361                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 362                 break;
 363         case 0xC0:
 364                 engine->instmem.init            = nvc0_instmem_init;
 365                 engine->instmem.takedown        = nvc0_instmem_takedown;
 366                 engine->instmem.suspend         = nvc0_instmem_suspend;
 367                 engine->instmem.resume          = nvc0_instmem_resume;
 368                 engine->instmem.populate        = nvc0_instmem_populate;
 369                 engine->instmem.clear           = nvc0_instmem_clear;
 370                 engine->instmem.bind            = nvc0_instmem_bind;
 371                 engine->instmem.unbind          = nvc0_instmem_unbind;
 372                 engine->instmem.flush           = nvc0_instmem_flush;
 373                 engine->mc.init                 = nv50_mc_init;
 374                 engine->mc.takedown             = nv50_mc_takedown;
 375                 engine->timer.init              = nv04_timer_init;
 376                 engine->timer.read              = nv04_timer_read;
 377                 engine->timer.takedown          = nv04_timer_takedown;
 378                 engine->fb.init                 = nvc0_fb_init;
 379                 engine->fb.takedown             = nvc0_fb_takedown;
 380                 engine->graph.grclass           = NULL;  //nvc0_graph_grclass;
 381                 engine->graph.init              = nvc0_graph_init;
 382                 engine->graph.takedown          = nvc0_graph_takedown;
 383                 engine->graph.fifo_access       = nvc0_graph_fifo_access;
 384                 engine->graph.channel           = nvc0_graph_channel;
 385                 engine->graph.create_context    = nvc0_graph_create_context;
 386                 engine->graph.destroy_context   = nvc0_graph_destroy_context;
 387                 engine->graph.load_context      = nvc0_graph_load_context;
 388                 engine->graph.unload_context    = nvc0_graph_unload_context;
 389                 engine->fifo.channels           = 128;
 390                 engine->fifo.init               = nvc0_fifo_init;
 391                 engine->fifo.takedown           = nvc0_fifo_takedown;
 392                 engine->fifo.disable            = nvc0_fifo_disable;
 393                 engine->fifo.enable             = nvc0_fifo_enable;
 394                 engine->fifo.reassign           = nvc0_fifo_reassign;
 395                 engine->fifo.channel_id         = nvc0_fifo_channel_id;
 396                 engine->fifo.create_context     = nvc0_fifo_create_context;
 397                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
 398                 engine->fifo.load_context       = nvc0_fifo_load_context;
 399                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
 400                 engine->display.early_init      = nv50_display_early_init;
 401                 engine->display.late_takedown   = nv50_display_late_takedown;
 402                 engine->display.create          = nv50_display_create;
 403                 engine->display.init            = nv50_display_init;
 404                 engine->display.destroy         = nv50_display_destroy;
 405                 engine->gpio.init               = nv50_gpio_init;
 406                 engine->gpio.takedown           = nouveau_stub_takedown;
 407                 engine->gpio.get                = nv50_gpio_get;
 408                 engine->gpio.set                = nv50_gpio_set;
 409                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 410                 break;
 411         default:
 412                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
 413                 return 1;
 414         }
 415
 416         return 0;
 417 }
 418
 419 static unsigned int
 420 nouveau_vga_set_decode(void *priv, bool state)
 421 {
 422         struct drm_device *dev = priv;
 423         struct drm_nouveau_private *dev_priv = dev->dev_private;
 424
 425         if (dev_priv->chipset >= 0x40)
 426                 nv_wr32(dev, 0x88054, state);
 427         else
 428                 nv_wr32(dev, 0x1854, state);
 429
 430         if (state)
 431                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 432                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 433         else
 434                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 435 }
 436
 437 static int
 438 nouveau_card_init_channel(struct drm_device *dev)
 439 {
 440         struct drm_nouveau_private *dev_priv = dev->dev_private;
 441         struct nouveau_gpuobj *gpuobj = NULL;
 442         int ret;
 443
 444         ret = nouveau_channel_alloc(dev, &dev_priv->channel,
 445                                     (struct drm_file *)-2, NvDmaFB, NvDmaTT);
 446         if (ret)
 447                 return ret;
 448
 449         ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
 450                                      0, dev_priv->vram_size,
 451                                      NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
 452                                      &gpuobj);
 453         if (ret)
 454                 goto out_err;
 455
 456         ret = nouveau_ramht_insert(dev_priv->channel, NvDmaVRAM, gpuobj);
 457         nouveau_gpuobj_ref(NULL, &gpuobj);
 458         if (ret)
 459                 goto out_err;
 460
 461         ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0,
 462                                           dev_priv->gart_info.aper_size,
 463                                           NV_DMA_ACCESS_RW, &gpuobj, NULL);
 464         if (ret)
 465                 goto out_err;
 466
 467         ret = nouveau_ramht_insert(dev_priv->channel, NvDmaGART, gpuobj);
 468         nouveau_gpuobj_ref(NULL, &gpuobj);
 469         if (ret)
 470                 goto out_err;
 471
 472         return 0;
 473
 474 out_err:
 475         nouveau_channel_free(dev_priv->channel);
 476         dev_priv->channel = NULL;
 477         return ret;
 478 }
 479
 480 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
 481                                          enum vga_switcheroo_state state)
 482 {
 483         struct drm_device *dev = pci_get_drvdata(pdev);
 484         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 485         if (state == VGA_SWITCHEROO_ON) {
 486                 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
 487                 nouveau_pci_resume(pdev);
 488                 drm_kms_helper_poll_enable(dev);
 489         } else {
 490                 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
 491                 drm_kms_helper_poll_disable(dev);
 492                 nouveau_pci_suspend(pdev, pmm);
 493         }
 494 }
 495
 496 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
 497 {
 498         struct drm_device *dev = pci_get_drvdata(pdev);
 499         bool can_switch;
 500
 501         spin_lock(&dev->count_lock);
 502         can_switch = (dev->open_count == 0);
 503         spin_unlock(&dev->count_lock);
 504         return can_switch;
 505 }
 506
 507 int
 508 nouveau_card_init(struct drm_device *dev)
 509 {
 510         struct drm_nouveau_private *dev_priv = dev->dev_private;
 511         struct nouveau_engine *engine;
 512         int ret;
 513
 514         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
 515         vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
 516                                        nouveau_switcheroo_can_switch);
 517
 518         /* Initialise internal driver API hooks */
 519         ret = nouveau_init_engine_ptrs(dev);
 520         if (ret)
 521                 goto out;
 522         engine = &dev_priv->engine;
 523         spin_lock_init(&dev_priv->context_switch_lock);
 524
 525         /* Make the CRTCs and I2C buses accessible */
 526         ret = engine->display.early_init(dev);
 527         if (ret)
 528                 goto out;
 529
 530         /* Parse BIOS tables / Run init tables if card not POSTed */
 531         ret = nouveau_bios_init(dev);
 532         if (ret)
 533                 goto out_display_early;
 534
 535         ret = nouveau_mem_detect(dev);
 536         if (ret)
 537                 goto out_bios;
 538
 539         ret = nouveau_gpuobj_early_init(dev);
 540         if (ret)
 541                 goto out_bios;
 542
 543         /* Initialise instance memory, must happen before mem_init so we
 544          * know exactly how much VRAM we're able to use for "normal"
 545          * purposes.
 546          */
 547         ret = engine->instmem.init(dev);
 548         if (ret)
 549                 goto out_gpuobj_early;
 550
 551         /* Setup the memory manager */
 552         ret = nouveau_mem_init(dev);
 553         if (ret)
 554                 goto out_instmem;
 555
 556         ret = nouveau_gpuobj_init(dev);
 557         if (ret)
 558                 goto out_mem;
 559
 560         /* PMC */
 561         ret = engine->mc.init(dev);
 562         if (ret)
 563                 goto out_gpuobj;
 564
 565         /* PGPIO */
 566         ret = engine->gpio.init(dev);
 567         if (ret)
 568                 goto out_mc;
 569
 570         /* PTIMER */
 571         ret = engine->timer.init(dev);
 572         if (ret)
 573                 goto out_gpio;
 574
 575         /* PFB */
 576         ret = engine->fb.init(dev);
 577         if (ret)
 578                 goto out_timer;
 579
 580         if (nouveau_noaccel)
 581                 engine->graph.accel_blocked = true;
 582         else {
 583                 /* PGRAPH */
 584                 ret = engine->graph.init(dev);
 585                 if (ret)
 586                         goto out_fb;
 587
 588                 /* PFIFO */
 589                 ret = engine->fifo.init(dev);
 590                 if (ret)
 591                         goto out_graph;
 592         }
 593
 594         ret = engine->display.create(dev);
 595         if (ret)
 596                 goto out_fifo;
 597
 598         /* this call irq_preinstall, register irq handler and
 599          * call irq_postinstall
 600          */
 601         ret = drm_irq_install(dev);
 602         if (ret)
 603                 goto out_display;
 604
 605         ret = drm_vblank_init(dev, 0);
 606         if (ret)
 607                 goto out_irq;
 608
 609         /* what about PVIDEO/PCRTC/PRAMDAC etc? */
 610
 611         if (!engine->graph.accel_blocked) {
 612                 ret = nouveau_card_init_channel(dev);
 613                 if (ret)
 614                         goto out_irq;
 615         }
 616
 617         ret = nouveau_backlight_init(dev);
 618         if (ret)
 619                 NV_ERROR(dev, "Error %d registering backlight\n", ret);
 620
 621         nouveau_fbcon_init(dev);
 622         drm_kms_helper_poll_init(dev);
 623         return 0;
 624
 625 out_irq:
 626         drm_irq_uninstall(dev);
 627 out_display:
 628         engine->display.destroy(dev);
 629 out_fifo:
 630         if (!nouveau_noaccel)
 631                 engine->fifo.takedown(dev);
 632 out_graph:
 633         if (!nouveau_noaccel)
 634                 engine->graph.takedown(dev);
 635 out_fb:
 636         engine->fb.takedown(dev);
 637 out_timer:
 638         engine->timer.takedown(dev);
 639 out_gpio:
 640         engine->gpio.takedown(dev);
 641 out_mc:
 642         engine->mc.takedown(dev);
 643 out_gpuobj:
 644         nouveau_gpuobj_takedown(dev);
 645 out_mem:
 646         nouveau_sgdma_takedown(dev);
 647         nouveau_mem_close(dev);
 648 out_instmem:
 649         engine->instmem.takedown(dev);
 650 out_gpuobj_early:
 651         nouveau_gpuobj_late_takedown(dev);
 652 out_bios:
 653         nouveau_bios_takedown(dev);
 654 out_display_early:
 655         engine->display.late_takedown(dev);
 656 out:
 657         vga_client_register(dev->pdev, NULL, NULL, NULL);
 658         return ret;
 659 }
 660
 661 static void nouveau_card_takedown(struct drm_device *dev)
 662 {
 663         struct drm_nouveau_private *dev_priv = dev->dev_private;
 664         struct nouveau_engine *engine = &dev_priv->engine;
 665
 666         nouveau_backlight_exit(dev);
 667
 668         if (dev_priv->channel) {
 669                 nouveau_channel_free(dev_priv->channel);
 670                 dev_priv->channel = NULL;
 671         }
 672
 673         if (!nouveau_noaccel) {
 674                 engine->fifo.takedown(dev);
 675                 engine->graph.takedown(dev);
 676         }
 677         engine->fb.takedown(dev);
 678         engine->timer.takedown(dev);
 679         engine->gpio.takedown(dev);
 680         engine->mc.takedown(dev);
 681         engine->display.late_takedown(dev);
 682
 683         mutex_lock(&dev->struct_mutex);
 684         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
 685         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
 686         mutex_unlock(&dev->struct_mutex);
 687         nouveau_sgdma_takedown(dev);
 688
 689         nouveau_gpuobj_takedown(dev);
 690         nouveau_mem_close(dev);
 691         engine->instmem.takedown(dev);
 692
 693         drm_irq_uninstall(dev);
 694
 695         nouveau_gpuobj_late_takedown(dev);
 696         nouveau_bios_takedown(dev);
 697
 698         vga_client_register(dev->pdev, NULL, NULL, NULL);
 699 }
 700
 701 /* here a client dies, release the stuff that was allocated for its
 702  * file_priv */
 703 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
 704 {
 705         nouveau_channel_cleanup(dev, file_priv);
 706 }
 707
 708 /* first module load, setup the mmio/fb mapping */
 709 /* KMS: we need mmio at load time, not when the first drm client opens. */
 710 int nouveau_firstopen(struct drm_device *dev)
 711 {
 712         return 0;
 713 }
 714
 715 /* if we have an OF card, copy vbios to RAMIN */
 716 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
 717 {
 718 #if defined(__powerpc__)
 719         int size, i;
 720         const uint32_t *bios;
 721         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
 722         if (!dn) {
 723                 NV_INFO(dev, "Unable to get the OF node\n");
 724                 return;
 725         }
 726
 727         bios = of_get_property(dn, "NVDA,BMP", &size);
 728         if (bios) {
 729                 for (i = 0; i < size; i += 4)
 730                         nv_wi32(dev, i, bios[i/4]);
 731                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
 732         } else {
 733                 NV_INFO(dev, "Unable to get the OF bios\n");
 734         }
 735 #endif
 736 }
 737
 738 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
 739 {
 740         struct pci_dev *pdev = dev->pdev;
 741         struct apertures_struct *aper = alloc_apertures(3);
 742         if (!aper)
 743                 return NULL;
 744
 745         aper->ranges[0].base = pci_resource_start(pdev, 1);
 746         aper->ranges[0].size = pci_resource_len(pdev, 1);
 747         aper->count = 1;
 748
 749         if (pci_resource_len(pdev, 2)) {
 750                 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
 751                 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
 752                 aper->count++;
 753         }
 754
 755         if (pci_resource_len(pdev, 3)) {
 756                 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
 757                 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
 758                 aper->count++;
 759         }
 760
 761         return aper;
 762 }
 763
 764 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
 765 {
 766         struct drm_nouveau_private *dev_priv = dev->dev_private;
 767         bool primary = false;
 768         dev_priv->apertures = nouveau_get_apertures(dev);
 769         if (!dev_priv->apertures)
 770                 return -ENOMEM;
 771
 772 #ifdef CONFIG_X86
 773         primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 774 #endif
 775
 776         remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
 777         return 0;
 778 }
 779
 780 int nouveau_load(struct drm_device *dev, unsigned long flags)
 781 {
 782         struct drm_nouveau_private *dev_priv;
 783         uint32_t reg0;
 784         resource_size_t mmio_start_offs;
 785         int ret;
 786
 787         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 788         if (!dev_priv) {
 789                 ret = -ENOMEM;
 790                 goto err_out;
 791         }
 792         dev->dev_private = dev_priv;
 793         dev_priv->dev = dev;
 794
 795         dev_priv->flags = flags & NOUVEAU_FLAGS;
 796
 797         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
 798                  dev->pci_vendor, dev->pci_device, dev->pdev->class);
 799
 800         dev_priv->wq = create_workqueue("nouveau");
 801         if (!dev_priv->wq) {
 802                 ret = -EINVAL;
 803                 goto err_priv;
 804         }
 805
 806         /* resource 0 is mmio regs */
 807         /* resource 1 is linear FB */
 808         /* resource 2 is RAMIN (mmio regs + 0x1000000) */
 809         /* resource 6 is bios */
 810
 811         /* map the mmio regs */
 812         mmio_start_offs = pci_resource_start(dev->pdev, 0);
 813         dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
 814         if (!dev_priv->mmio) {
 815                 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
 816                          "Please report your setup to " DRIVER_EMAIL "\n");
 817                 ret = -EINVAL;
 818                 goto err_wq;
 819         }
 820         NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
 821                                         (unsigned long long)mmio_start_offs);
 822
 823 #ifdef __BIG_ENDIAN
 824         /* Put the card in BE mode if it's not */
 825         if (nv_rd32(dev, NV03_PMC_BOOT_1))
 826                 nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
 827
 828         DRM_MEMORYBARRIER();
 829 #endif
 830
 831         /* Time to determine the card architecture */
 832         reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
 833
 834         /* We're dealing with >=NV10 */
 835         if ((reg0 & 0x0f000000) > 0) {
 836                 /* Bit 27-20 contain the architecture in hex */
 837                 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
 838         /* NV04 or NV05 */
 839         } else if ((reg0 & 0xff00fff0) == 0x20004000) {
 840                 if (reg0 & 0x00f00000)
 841                         dev_priv->chipset = 0x05;
 842                 else
 843                         dev_priv->chipset = 0x04;
 844         } else
 845                 dev_priv->chipset = 0xff;
 846
 847         switch (dev_priv->chipset & 0xf0) {
 848         case 0x00:
 849         case 0x10:
 850         case 0x20:
 851         case 0x30:
 852                 dev_priv->card_type = dev_priv->chipset & 0xf0;
 853                 break;
 854         case 0x40:
 855         case 0x60:
 856                 dev_priv->card_type = NV_40;
 857                 break;
 858         case 0x50:
 859         case 0x80:
 860         case 0x90:
 861         case 0xa0:
 862                 dev_priv->card_type = NV_50;
 863                 break;
 864         case 0xc0:
 865                 dev_priv->card_type = NV_C0;
 866                 break;
 867         default:
 868                 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
 869                 ret = -EINVAL;
 870                 goto err_mmio;
 871         }
 872
 873         NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
 874                 dev_priv->card_type, reg0);
 875
 876         ret = nouveau_remove_conflicting_drivers(dev);
 877         if (ret)
 878                 goto err_mmio;
 879
 880         /* Map PRAMIN BAR, or on older cards, the aperture withing BAR0 */
 881         if (dev_priv->card_type >= NV_40) {
 882                 int ramin_bar = 2;
 883                 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
 884                         ramin_bar = 3;
 885
 886                 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
 887                 dev_priv->ramin =
 888                         ioremap(pci_resource_start(dev->pdev, ramin_bar),
 889                                 dev_priv->ramin_size);
 890                 if (!dev_priv->ramin) {
 891                         NV_ERROR(dev, "Failed to PRAMIN BAR");
 892                         ret = -ENOMEM;
 893                         goto err_mmio;
 894                 }
 895         } else {
 896                 dev_priv->ramin_size = 1 * 1024 * 1024;
 897                 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
 898                                           dev_priv->ramin_size);
 899                 if (!dev_priv->ramin) {
 900                         NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
 901                         ret = -ENOMEM;
 902                         goto err_mmio;
 903                 }
 904         }
 905
 906         nouveau_OF_copy_vbios_to_ramin(dev);
 907
 908         /* Special flags */
 909         if (dev->pci_device == 0x01a0)
 910                 dev_priv->flags |= NV_NFORCE;
 911         else if (dev->pci_device == 0x01f0)
 912                 dev_priv->flags |= NV_NFORCE2;
 913
 914         /* For kernel modesetting, init card now and bring up fbcon */
 915         ret = nouveau_card_init(dev);
 916         if (ret)
 917                 goto err_ramin;
 918
 919         return 0;
 920
 921 err_ramin:
 922         iounmap(dev_priv->ramin);
 923 err_mmio:
 924         iounmap(dev_priv->mmio);
 925 err_wq:
 926         destroy_workqueue(dev_priv->wq);
 927 err_priv:
 928         kfree(dev_priv);
 929         dev->dev_private = NULL;
 930 err_out:
 931         return ret;
 932 }
 933
 934 void nouveau_lastclose(struct drm_device *dev)
 935 {
 936 }
 937
 938 int nouveau_unload(struct drm_device *dev)
 939 {
 940         struct drm_nouveau_private *dev_priv = dev->dev_private;
 941         struct nouveau_engine *engine = &dev_priv->engine;
 942
 943         drm_kms_helper_poll_fini(dev);
 944         nouveau_fbcon_fini(dev);
 945         engine->display.destroy(dev);
 946         nouveau_card_takedown(dev);
 947
 948         iounmap(dev_priv->mmio);
 949         iounmap(dev_priv->ramin);
 950
 951         kfree(dev_priv);
 952         dev->dev_private = NULL;
 953         return 0;
 954 }
 955
 956 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
 957                                                 struct drm_file *file_priv)
 958 {
 959         struct drm_nouveau_private *dev_priv = dev->dev_private;
 960         struct drm_nouveau_getparam *getparam = data;
 961
 962         switch (getparam->param) {
 963         case NOUVEAU_GETPARAM_CHIPSET_ID:
 964                 getparam->value = dev_priv->chipset;
 965                 break;
 966         case NOUVEAU_GETPARAM_PCI_VENDOR:
 967                 getparam->value = dev->pci_vendor;
 968                 break;
 969         case NOUVEAU_GETPARAM_PCI_DEVICE:
 970                 getparam->value = dev->pci_device;
 971                 break;
 972         case NOUVEAU_GETPARAM_BUS_TYPE:
 973                 if (drm_device_is_agp(dev))
 974                         getparam->value = NV_AGP;
 975                 else if (drm_device_is_pcie(dev))
 976                         getparam->value = NV_PCIE;
 977                 else
 978                         getparam->value = NV_PCI;
 979                 break;
 980         case NOUVEAU_GETPARAM_FB_PHYSICAL:
 981                 getparam->value = dev_priv->fb_phys;
 982                 break;
 983         case NOUVEAU_GETPARAM_AGP_PHYSICAL:
 984                 getparam->value = dev_priv->gart_info.aper_base;
 985                 break;
 986         case NOUVEAU_GETPARAM_PCI_PHYSICAL:
 987                 if (dev->sg) {
 988                         getparam->value = (unsigned long)dev->sg->virtual;
 989                 } else {
 990                         NV_ERROR(dev, "Requested PCIGART address, "
 991                                         "while no PCIGART was created\n");
 992                         return -EINVAL;
 993                 }
 994                 break;
 995         case NOUVEAU_GETPARAM_FB_SIZE:
 996                 getparam->value = dev_priv->fb_available_size;
 997                 break;
 998         case NOUVEAU_GETPARAM_AGP_SIZE:
 999                 getparam->value = dev_priv->gart_info.aper_size;
1000                 break;
1001         case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1002                 getparam->value = dev_priv->vm_vram_base;
1003                 break;
1004         case NOUVEAU_GETPARAM_PTIMER_TIME:
1005                 getparam->value = dev_priv->engine.timer.read(dev);
1006                 break;
1007         case NOUVEAU_GETPARAM_GRAPH_UNITS:
1008                 /* NV40 and NV50 versions are quite different, but register
1009                  * address is the same. User is supposed to know the card
1010                  * family anyway... */
1011                 if (dev_priv->chipset >= 0x40) {
1012                         getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1013                         break;
1014                 }
1015                 /* FALLTHRU */
1016         default:
1017                 NV_ERROR(dev, "unknown parameter %lld\n", getparam->param);
1018                 return -EINVAL;
1019         }
1020
1021         return 0;
1022 }
1023
1024 int
1025 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1026                        struct drm_file *file_priv)
1027 {
1028         struct drm_nouveau_setparam *setparam = data;
1029
1030         switch (setparam->param) {
1031         default:
1032                 NV_ERROR(dev, "unknown parameter %lld\n", setparam->param);
1033                 return -EINVAL;
1034         }
1035
1036         return 0;
1037 }
1038
1039 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1040 bool nouveau_wait_until(struct drm_device *dev, uint64_t timeout,
1041                         uint32_t reg, uint32_t mask, uint32_t val)
1042 {
1043         struct drm_nouveau_private *dev_priv = dev->dev_private;
1044         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1045         uint64_t start = ptimer->read(dev);
1046
1047         do {
1048                 if ((nv_rd32(dev, reg) & mask) == val)
1049                         return true;
1050         } while (ptimer->read(dev) - start < timeout);
1051
1052         return false;
1053 }
1054
1055 /* Waits for PGRAPH to go completely idle */
1056 bool nouveau_wait_for_idle(struct drm_device *dev)
1057 {
1058         if (!nv_wait(NV04_PGRAPH_STATUS, 0xffffffff, 0x00000000)) {
1059                 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1060                          nv_rd32(dev, NV04_PGRAPH_STATUS));
1061                 return false;
1062         }
1063
1064         return true;
1065 }
1066