drivers/gpu/drm/nouveau/nouveau_state.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin
   3  * Copyright 2008 Stuart Bennett
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include <linux/swab.h>
  27 #include <linux/slab.h>
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "drm_sarea.h"
  31 #include "drm_crtc_helper.h"
  32 #include <linux/vgaarb.h>
  33 #include <linux/vga_switcheroo.h>
  34
  35 #include "nouveau_drv.h"
  36 #include "nouveau_drm.h"
  37 #include "nouveau_fbcon.h"
  38 #include "nouveau_ramht.h"
  39 #include "nouveau_gpio.h"
  40 #include "nouveau_pm.h"
  41 #include "nv50_display.h"
  42 #include "nouveau_fifo.h"
  43 #include "nouveau_fence.h"
  44 #include "nouveau_software.h"
  45
  46 static void nouveau_stub_takedown(struct drm_device *dev) {}
  47 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
  48
  49 static int nouveau_init_engine_ptrs(struct drm_device *dev)
  50 {
  51         struct drm_nouveau_private *dev_priv = dev->dev_private;
  52         struct nouveau_engine *engine = &dev_priv->engine;
  53
  54         switch (dev_priv->chipset & 0xf0) {
  55         case 0x00:
  56                 engine->instmem.init            = nv04_instmem_init;
  57                 engine->instmem.takedown        = nv04_instmem_takedown;
  58                 engine->instmem.suspend         = nv04_instmem_suspend;
  59                 engine->instmem.resume          = nv04_instmem_resume;
  60                 engine->instmem.get             = nv04_instmem_get;
  61                 engine->instmem.put             = nv04_instmem_put;
  62                 engine->instmem.map             = nv04_instmem_map;
  63                 engine->instmem.unmap           = nv04_instmem_unmap;
  64                 engine->instmem.flush           = nv04_instmem_flush;
  65                 engine->mc.init                 = nv04_mc_init;
  66                 engine->mc.takedown             = nv04_mc_takedown;
  67                 engine->timer.init              = nv04_timer_init;
  68                 engine->timer.read              = nv04_timer_read;
  69                 engine->timer.takedown          = nv04_timer_takedown;
  70                 engine->fb.init                 = nv04_fb_init;
  71                 engine->fb.takedown             = nv04_fb_takedown;
  72                 engine->display.early_init      = nv04_display_early_init;
  73                 engine->display.late_takedown   = nv04_display_late_takedown;
  74                 engine->display.create          = nv04_display_create;
  75                 engine->display.destroy         = nv04_display_destroy;
  76                 engine->display.init            = nv04_display_init;
  77                 engine->display.fini            = nv04_display_fini;
  78                 engine->pm.clocks_get           = nv04_pm_clocks_get;
  79                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
  80                 engine->pm.clocks_set           = nv04_pm_clocks_set;
  81                 engine->vram.init               = nv04_fb_vram_init;
  82                 engine->vram.takedown           = nouveau_stub_takedown;
  83                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
  84                 break;
  85         case 0x10:
  86                 engine->instmem.init            = nv04_instmem_init;
  87                 engine->instmem.takedown        = nv04_instmem_takedown;
  88                 engine->instmem.suspend         = nv04_instmem_suspend;
  89                 engine->instmem.resume          = nv04_instmem_resume;
  90                 engine->instmem.get             = nv04_instmem_get;
  91                 engine->instmem.put             = nv04_instmem_put;
  92                 engine->instmem.map             = nv04_instmem_map;
  93                 engine->instmem.unmap           = nv04_instmem_unmap;
  94                 engine->instmem.flush           = nv04_instmem_flush;
  95                 engine->mc.init                 = nv04_mc_init;
  96                 engine->mc.takedown             = nv04_mc_takedown;
  97                 engine->timer.init              = nv04_timer_init;
  98                 engine->timer.read              = nv04_timer_read;
  99                 engine->timer.takedown          = nv04_timer_takedown;
 100                 engine->fb.init                 = nv10_fb_init;
 101                 engine->fb.takedown             = nv10_fb_takedown;
 102                 engine->fb.init_tile_region     = nv10_fb_init_tile_region;
 103                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 104                 engine->fb.free_tile_region     = nv10_fb_free_tile_region;
 105                 engine->display.early_init      = nv04_display_early_init;
 106                 engine->display.late_takedown   = nv04_display_late_takedown;
 107                 engine->display.create          = nv04_display_create;
 108                 engine->display.destroy         = nv04_display_destroy;
 109                 engine->display.init            = nv04_display_init;
 110                 engine->display.fini            = nv04_display_fini;
 111                 engine->gpio.drive              = nv10_gpio_drive;
 112                 engine->gpio.sense              = nv10_gpio_sense;
 113                 engine->pm.clocks_get           = nv04_pm_clocks_get;
 114                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
 115                 engine->pm.clocks_set           = nv04_pm_clocks_set;
 116                 if (dev_priv->chipset == 0x1a ||
 117                     dev_priv->chipset == 0x1f)
 118                         engine->vram.init       = nv1a_fb_vram_init;
 119                 else
 120                         engine->vram.init       = nv10_fb_vram_init;
 121                 engine->vram.takedown           = nouveau_stub_takedown;
 122                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 123                 break;
 124         case 0x20:
 125                 engine->instmem.init            = nv04_instmem_init;
 126                 engine->instmem.takedown        = nv04_instmem_takedown;
 127                 engine->instmem.suspend         = nv04_instmem_suspend;
 128                 engine->instmem.resume          = nv04_instmem_resume;
 129                 engine->instmem.get             = nv04_instmem_get;
 130                 engine->instmem.put             = nv04_instmem_put;
 131                 engine->instmem.map             = nv04_instmem_map;
 132                 engine->instmem.unmap           = nv04_instmem_unmap;
 133                 engine->instmem.flush           = nv04_instmem_flush;
 134                 engine->mc.init                 = nv04_mc_init;
 135                 engine->mc.takedown             = nv04_mc_takedown;
 136                 engine->timer.init              = nv04_timer_init;
 137                 engine->timer.read              = nv04_timer_read;
 138                 engine->timer.takedown          = nv04_timer_takedown;
 139                 engine->fb.init                 = nv20_fb_init;
 140                 engine->fb.takedown             = nv20_fb_takedown;
 141                 engine->fb.init_tile_region     = nv20_fb_init_tile_region;
 142                 engine->fb.set_tile_region      = nv20_fb_set_tile_region;
 143                 engine->fb.free_tile_region     = nv20_fb_free_tile_region;
 144                 engine->display.early_init      = nv04_display_early_init;
 145                 engine->display.late_takedown   = nv04_display_late_takedown;
 146                 engine->display.create          = nv04_display_create;
 147                 engine->display.destroy         = nv04_display_destroy;
 148                 engine->display.init            = nv04_display_init;
 149                 engine->display.fini            = nv04_display_fini;
 150                 engine->gpio.drive              = nv10_gpio_drive;
 151                 engine->gpio.sense              = nv10_gpio_sense;
 152                 engine->pm.clocks_get           = nv04_pm_clocks_get;
 153                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
 154                 engine->pm.clocks_set           = nv04_pm_clocks_set;
 155                 engine->vram.init               = nv20_fb_vram_init;
 156                 engine->vram.takedown           = nouveau_stub_takedown;
 157                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 158                 break;
 159         case 0x30:
 160                 engine->instmem.init            = nv04_instmem_init;
 161                 engine->instmem.takedown        = nv04_instmem_takedown;
 162                 engine->instmem.suspend         = nv04_instmem_suspend;
 163                 engine->instmem.resume          = nv04_instmem_resume;
 164                 engine->instmem.get             = nv04_instmem_get;
 165                 engine->instmem.put             = nv04_instmem_put;
 166                 engine->instmem.map             = nv04_instmem_map;
 167                 engine->instmem.unmap           = nv04_instmem_unmap;
 168                 engine->instmem.flush           = nv04_instmem_flush;
 169                 engine->mc.init                 = nv04_mc_init;
 170                 engine->mc.takedown             = nv04_mc_takedown;
 171                 engine->timer.init              = nv04_timer_init;
 172                 engine->timer.read              = nv04_timer_read;
 173                 engine->timer.takedown          = nv04_timer_takedown;
 174                 engine->fb.init                 = nv30_fb_init;
 175                 engine->fb.takedown             = nv30_fb_takedown;
 176                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 177                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 178                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 179                 engine->display.early_init      = nv04_display_early_init;
 180                 engine->display.late_takedown   = nv04_display_late_takedown;
 181                 engine->display.create          = nv04_display_create;
 182                 engine->display.destroy         = nv04_display_destroy;
 183                 engine->display.init            = nv04_display_init;
 184                 engine->display.fini            = nv04_display_fini;
 185                 engine->gpio.drive              = nv10_gpio_drive;
 186                 engine->gpio.sense              = nv10_gpio_sense;
 187                 engine->pm.clocks_get           = nv04_pm_clocks_get;
 188                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
 189                 engine->pm.clocks_set           = nv04_pm_clocks_set;
 190                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 191                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 192                 engine->vram.init               = nv20_fb_vram_init;
 193                 engine->vram.takedown           = nouveau_stub_takedown;
 194                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 195                 break;
 196         case 0x40:
 197         case 0x60:
 198                 engine->instmem.init            = nv04_instmem_init;
 199                 engine->instmem.takedown        = nv04_instmem_takedown;
 200                 engine->instmem.suspend         = nv04_instmem_suspend;
 201                 engine->instmem.resume          = nv04_instmem_resume;
 202                 engine->instmem.get             = nv04_instmem_get;
 203                 engine->instmem.put             = nv04_instmem_put;
 204                 engine->instmem.map             = nv04_instmem_map;
 205                 engine->instmem.unmap           = nv04_instmem_unmap;
 206                 engine->instmem.flush           = nv04_instmem_flush;
 207                 engine->mc.init                 = nv40_mc_init;
 208                 engine->mc.takedown             = nv40_mc_takedown;
 209                 engine->timer.init              = nv04_timer_init;
 210                 engine->timer.read              = nv04_timer_read;
 211                 engine->timer.takedown          = nv04_timer_takedown;
 212                 engine->fb.init                 = nv40_fb_init;
 213                 engine->fb.takedown             = nv40_fb_takedown;
 214                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 215                 engine->fb.set_tile_region      = nv40_fb_set_tile_region;
 216                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 217                 engine->display.early_init      = nv04_display_early_init;
 218                 engine->display.late_takedown   = nv04_display_late_takedown;
 219                 engine->display.create          = nv04_display_create;
 220                 engine->display.destroy         = nv04_display_destroy;
 221                 engine->display.init            = nv04_display_init;
 222                 engine->display.fini            = nv04_display_fini;
 223                 engine->gpio.init               = nv10_gpio_init;
 224                 engine->gpio.fini               = nv10_gpio_fini;
 225                 engine->gpio.drive              = nv10_gpio_drive;
 226                 engine->gpio.sense              = nv10_gpio_sense;
 227                 engine->gpio.irq_enable         = nv10_gpio_irq_enable;
 228                 engine->pm.clocks_get           = nv40_pm_clocks_get;
 229                 engine->pm.clocks_pre           = nv40_pm_clocks_pre;
 230                 engine->pm.clocks_set           = nv40_pm_clocks_set;
 231                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 232                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 233                 engine->pm.temp_get             = nv40_temp_get;
 234                 engine->pm.pwm_get              = nv40_pm_pwm_get;
 235                 engine->pm.pwm_set              = nv40_pm_pwm_set;
 236                 engine->vram.init               = nv40_fb_vram_init;
 237                 engine->vram.takedown           = nouveau_stub_takedown;
 238                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 239                 break;
 240         case 0x50:
 241         case 0x80: /* gotta love NVIDIA's consistency.. */
 242         case 0x90:
 243         case 0xa0:
 244                 engine->instmem.init            = nv50_instmem_init;
 245                 engine->instmem.takedown        = nv50_instmem_takedown;
 246                 engine->instmem.suspend         = nv50_instmem_suspend;
 247                 engine->instmem.resume          = nv50_instmem_resume;
 248                 engine->instmem.get             = nv50_instmem_get;
 249                 engine->instmem.put             = nv50_instmem_put;
 250                 engine->instmem.map             = nv50_instmem_map;
 251                 engine->instmem.unmap           = nv50_instmem_unmap;
 252                 if (dev_priv->chipset == 0x50)
 253                         engine->instmem.flush   = nv50_instmem_flush;
 254                 else
 255                         engine->instmem.flush   = nv84_instmem_flush;
 256                 engine->mc.init                 = nv50_mc_init;
 257                 engine->mc.takedown             = nv50_mc_takedown;
 258                 engine->timer.init              = nv04_timer_init;
 259                 engine->timer.read              = nv04_timer_read;
 260                 engine->timer.takedown          = nv04_timer_takedown;
 261                 engine->fb.init                 = nv50_fb_init;
 262                 engine->fb.takedown             = nv50_fb_takedown;
 263                 engine->display.early_init      = nv50_display_early_init;
 264                 engine->display.late_takedown   = nv50_display_late_takedown;
 265                 engine->display.create          = nv50_display_create;
 266                 engine->display.destroy         = nv50_display_destroy;
 267                 engine->display.init            = nv50_display_init;
 268                 engine->display.fini            = nv50_display_fini;
 269                 engine->gpio.init               = nv50_gpio_init;
 270                 engine->gpio.fini               = nv50_gpio_fini;
 271                 engine->gpio.drive              = nv50_gpio_drive;
 272                 engine->gpio.sense              = nv50_gpio_sense;
 273                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 274                 switch (dev_priv->chipset) {
 275                 case 0x84:
 276                 case 0x86:
 277                 case 0x92:
 278                 case 0x94:
 279                 case 0x96:
 280                 case 0x98:
 281                 case 0xa0:
 282                 case 0xaa:
 283                 case 0xac:
 284                 case 0x50:
 285                         engine->pm.clocks_get   = nv50_pm_clocks_get;
 286                         engine->pm.clocks_pre   = nv50_pm_clocks_pre;
 287                         engine->pm.clocks_set   = nv50_pm_clocks_set;
 288                         break;
 289                 default:
 290                         engine->pm.clocks_get   = nva3_pm_clocks_get;
 291                         engine->pm.clocks_pre   = nva3_pm_clocks_pre;
 292                         engine->pm.clocks_set   = nva3_pm_clocks_set;
 293                         break;
 294                 }
 295                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 296                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 297                 if (dev_priv->chipset >= 0x84)
 298                         engine->pm.temp_get     = nv84_temp_get;
 299                 else
 300                         engine->pm.temp_get     = nv40_temp_get;
 301                 engine->pm.pwm_get              = nv50_pm_pwm_get;
 302                 engine->pm.pwm_set              = nv50_pm_pwm_set;
 303                 engine->vram.init               = nv50_vram_init;
 304                 engine->vram.takedown           = nv50_vram_fini;
 305                 engine->vram.get                = nv50_vram_new;
 306                 engine->vram.put                = nv50_vram_del;
 307                 engine->vram.flags_valid        = nv50_vram_flags_valid;
 308                 break;
 309         case 0xc0:
 310                 engine->instmem.init            = nvc0_instmem_init;
 311                 engine->instmem.takedown        = nvc0_instmem_takedown;
 312                 engine->instmem.suspend         = nvc0_instmem_suspend;
 313                 engine->instmem.resume          = nvc0_instmem_resume;
 314                 engine->instmem.get             = nv50_instmem_get;
 315                 engine->instmem.put             = nv50_instmem_put;
 316                 engine->instmem.map             = nv50_instmem_map;
 317                 engine->instmem.unmap           = nv50_instmem_unmap;
 318                 engine->instmem.flush           = nv84_instmem_flush;
 319                 engine->mc.init                 = nv50_mc_init;
 320                 engine->mc.takedown             = nv50_mc_takedown;
 321                 engine->timer.init              = nv04_timer_init;
 322                 engine->timer.read              = nv04_timer_read;
 323                 engine->timer.takedown          = nv04_timer_takedown;
 324                 engine->fb.init                 = nvc0_fb_init;
 325                 engine->fb.takedown             = nvc0_fb_takedown;
 326                 engine->display.early_init      = nv50_display_early_init;
 327                 engine->display.late_takedown   = nv50_display_late_takedown;
 328                 engine->display.create          = nv50_display_create;
 329                 engine->display.destroy         = nv50_display_destroy;
 330                 engine->display.init            = nv50_display_init;
 331                 engine->display.fini            = nv50_display_fini;
 332                 engine->gpio.init               = nv50_gpio_init;
 333                 engine->gpio.fini               = nv50_gpio_fini;
 334                 engine->gpio.drive              = nv50_gpio_drive;
 335                 engine->gpio.sense              = nv50_gpio_sense;
 336                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 337                 engine->vram.init               = nvc0_vram_init;
 338                 engine->vram.takedown           = nv50_vram_fini;
 339                 engine->vram.get                = nvc0_vram_new;
 340                 engine->vram.put                = nv50_vram_del;
 341                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 342                 engine->pm.temp_get             = nv84_temp_get;
 343                 engine->pm.clocks_get           = nvc0_pm_clocks_get;
 344                 engine->pm.clocks_pre           = nvc0_pm_clocks_pre;
 345                 engine->pm.clocks_set           = nvc0_pm_clocks_set;
 346                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 347                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 348                 engine->pm.pwm_get              = nv50_pm_pwm_get;
 349                 engine->pm.pwm_set              = nv50_pm_pwm_set;
 350                 break;
 351         case 0xd0:
 352                 engine->instmem.init            = nvc0_instmem_init;
 353                 engine->instmem.takedown        = nvc0_instmem_takedown;
 354                 engine->instmem.suspend         = nvc0_instmem_suspend;
 355                 engine->instmem.resume          = nvc0_instmem_resume;
 356                 engine->instmem.get             = nv50_instmem_get;
 357                 engine->instmem.put             = nv50_instmem_put;
 358                 engine->instmem.map             = nv50_instmem_map;
 359                 engine->instmem.unmap           = nv50_instmem_unmap;
 360                 engine->instmem.flush           = nv84_instmem_flush;
 361                 engine->mc.init                 = nv50_mc_init;
 362                 engine->mc.takedown             = nv50_mc_takedown;
 363                 engine->timer.init              = nv04_timer_init;
 364                 engine->timer.read              = nv04_timer_read;
 365                 engine->timer.takedown          = nv04_timer_takedown;
 366                 engine->fb.init                 = nvc0_fb_init;
 367                 engine->fb.takedown             = nvc0_fb_takedown;
 368                 engine->display.early_init      = nouveau_stub_init;
 369                 engine->display.late_takedown   = nouveau_stub_takedown;
 370                 engine->display.create          = nvd0_display_create;
 371                 engine->display.destroy         = nvd0_display_destroy;
 372                 engine->display.init            = nvd0_display_init;
 373                 engine->display.fini            = nvd0_display_fini;
 374                 engine->gpio.init               = nv50_gpio_init;
 375                 engine->gpio.fini               = nv50_gpio_fini;
 376                 engine->gpio.drive              = nvd0_gpio_drive;
 377                 engine->gpio.sense              = nvd0_gpio_sense;
 378                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 379                 engine->vram.init               = nvc0_vram_init;
 380                 engine->vram.takedown           = nv50_vram_fini;
 381                 engine->vram.get                = nvc0_vram_new;
 382                 engine->vram.put                = nv50_vram_del;
 383                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 384                 engine->pm.temp_get             = nv84_temp_get;
 385                 engine->pm.clocks_get           = nvc0_pm_clocks_get;
 386                 engine->pm.clocks_pre           = nvc0_pm_clocks_pre;
 387                 engine->pm.clocks_set           = nvc0_pm_clocks_set;
 388                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 389                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 390                 break;
 391         case 0xe0:
 392                 engine->instmem.init            = nvc0_instmem_init;
 393                 engine->instmem.takedown        = nvc0_instmem_takedown;
 394                 engine->instmem.suspend         = nvc0_instmem_suspend;
 395                 engine->instmem.resume          = nvc0_instmem_resume;
 396                 engine->instmem.get             = nv50_instmem_get;
 397                 engine->instmem.put             = nv50_instmem_put;
 398                 engine->instmem.map             = nv50_instmem_map;
 399                 engine->instmem.unmap           = nv50_instmem_unmap;
 400                 engine->instmem.flush           = nv84_instmem_flush;
 401                 engine->mc.init                 = nv50_mc_init;
 402                 engine->mc.takedown             = nv50_mc_takedown;
 403                 engine->timer.init              = nv04_timer_init;
 404                 engine->timer.read              = nv04_timer_read;
 405                 engine->timer.takedown          = nv04_timer_takedown;
 406                 engine->fb.init                 = nvc0_fb_init;
 407                 engine->fb.takedown             = nvc0_fb_takedown;
 408                 engine->display.early_init      = nouveau_stub_init;
 409                 engine->display.late_takedown   = nouveau_stub_takedown;
 410                 engine->display.create          = nvd0_display_create;
 411                 engine->display.destroy         = nvd0_display_destroy;
 412                 engine->display.init            = nvd0_display_init;
 413                 engine->display.fini            = nvd0_display_fini;
 414                 engine->gpio.init               = nv50_gpio_init;
 415                 engine->gpio.fini               = nv50_gpio_fini;
 416                 engine->gpio.drive              = nvd0_gpio_drive;
 417                 engine->gpio.sense              = nvd0_gpio_sense;
 418                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 419                 engine->vram.init               = nvc0_vram_init;
 420                 engine->vram.takedown           = nv50_vram_fini;
 421                 engine->vram.get                = nvc0_vram_new;
 422                 engine->vram.put                = nv50_vram_del;
 423                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 424                 break;
 425         default:
 426                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
 427                 return 1;
 428         }
 429
 430         /* headless mode */
 431         if (nouveau_modeset == 2) {
 432                 engine->display.early_init = nouveau_stub_init;
 433                 engine->display.late_takedown = nouveau_stub_takedown;
 434                 engine->display.create = nouveau_stub_init;
 435                 engine->display.init = nouveau_stub_init;
 436                 engine->display.destroy = nouveau_stub_takedown;
 437         }
 438
 439         return 0;
 440 }
 441
 442 static unsigned int
 443 nouveau_vga_set_decode(void *priv, bool state)
 444 {
 445         struct drm_device *dev = priv;
 446         struct drm_nouveau_private *dev_priv = dev->dev_private;
 447
 448         if (dev_priv->chipset >= 0x40)
 449                 nv_wr32(dev, 0x88054, state);
 450         else
 451                 nv_wr32(dev, 0x1854, state);
 452
 453         if (state)
 454                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 455                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 456         else
 457                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 458 }
 459
 460 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
 461                                          enum vga_switcheroo_state state)
 462 {
 463         struct drm_device *dev = pci_get_drvdata(pdev);
 464         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 465         if (state == VGA_SWITCHEROO_ON) {
 466                 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
 467                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 468                 nouveau_pci_resume(pdev);
 469                 drm_kms_helper_poll_enable(dev);
 470                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 471         } else {
 472                 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
 473                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 474                 drm_kms_helper_poll_disable(dev);
 475                 nouveau_switcheroo_optimus_dsm();
 476                 nouveau_pci_suspend(pdev, pmm);
 477                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 478         }
 479 }
 480
 481 static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
 482 {
 483         struct drm_device *dev = pci_get_drvdata(pdev);
 484         nouveau_fbcon_output_poll_changed(dev);
 485 }
 486
 487 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
 488 {
 489         struct drm_device *dev = pci_get_drvdata(pdev);
 490         bool can_switch;
 491
 492         spin_lock(&dev->count_lock);
 493         can_switch = (dev->open_count == 0);
 494         spin_unlock(&dev->count_lock);
 495         return can_switch;
 496 }
 497
 498 static void
 499 nouveau_card_channel_fini(struct drm_device *dev)
 500 {
 501         struct drm_nouveau_private *dev_priv = dev->dev_private;
 502
 503         if (dev_priv->channel)
 504                 nouveau_channel_put_unlocked(&dev_priv->channel);
 505 }
 506
 507 static int
 508 nouveau_card_channel_init(struct drm_device *dev)
 509 {
 510         struct drm_nouveau_private *dev_priv = dev->dev_private;
 511         struct nouveau_channel *chan;
 512         int ret, oclass;
 513
 514         ret = nouveau_channel_alloc(dev, &chan, NULL, NvDmaFB, NvDmaTT);
 515         dev_priv->channel = chan;
 516         if (ret)
 517                 return ret;
 518
 519         mutex_unlock(&dev_priv->channel->mutex);
 520
 521         if (dev_priv->card_type <= NV_50) {
 522                 if (dev_priv->card_type < NV_50)
 523                         oclass = 0x0039;
 524                 else
 525                         oclass = 0x5039;
 526
 527                 ret = nouveau_gpuobj_gr_new(chan, NvM2MF, oclass);
 528                 if (ret)
 529                         goto error;
 530
 531                 ret = nouveau_notifier_alloc(chan, NvNotify0, 32, 0xfe0, 0x1000,
 532                                              &chan->m2mf_ntfy);
 533                 if (ret)
 534                         goto error;
 535
 536                 ret = RING_SPACE(chan, 6);
 537                 if (ret)
 538                         goto error;
 539
 540                 BEGIN_NV04(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NAME, 1);
 541                 OUT_RING  (chan, NvM2MF);
 542                 BEGIN_NV04(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 3);
 543                 OUT_RING  (chan, NvNotify0);
 544                 OUT_RING  (chan, chan->vram_handle);
 545                 OUT_RING  (chan, chan->gart_handle);
 546         } else
 547         if (dev_priv->card_type <= NV_D0) {
 548                 ret = nouveau_gpuobj_gr_new(chan, 0x9039, 0x9039);
 549                 if (ret)
 550                         goto error;
 551
 552                 ret = RING_SPACE(chan, 2);
 553                 if (ret)
 554                         goto error;
 555
 556                 BEGIN_NVC0(chan, NvSubM2MF, 0x0000, 1);
 557                 OUT_RING  (chan, 0x00009039);
 558         } else
 559         if (dev_priv->card_type <= NV_E0) {
 560                 /* not used, but created to get a graph context */
 561                 ret = nouveau_gpuobj_gr_new(chan, 0xa040, 0xa040);
 562                 if (ret)
 563                         goto error;
 564
 565                 /* bind strange copy engine to subchannel 4 (fixed...) */
 566                 ret = RING_SPACE(chan, 2);
 567                 if (ret)
 568                         goto error;
 569
 570                 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
 571                 OUT_RING  (chan, 0x0000a0b5);
 572         }
 573
 574         FIRE_RING (chan);
 575 error:
 576         if (ret)
 577                 nouveau_card_channel_fini(dev);
 578         return ret;
 579 }
 580
 581 static const struct vga_switcheroo_client_ops nouveau_switcheroo_ops = {
 582         .set_gpu_state = nouveau_switcheroo_set_state,
 583         .reprobe = nouveau_switcheroo_reprobe,
 584         .can_switch = nouveau_switcheroo_can_switch,
 585 };
 586
 587 int
 588 nouveau_card_init(struct drm_device *dev)
 589 {
 590         struct drm_nouveau_private *dev_priv = dev->dev_private;
 591         struct nouveau_engine *engine;
 592         int ret, e = 0;
 593
 594         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
 595         vga_switcheroo_register_client(dev->pdev, &nouveau_switcheroo_ops);
 596
 597         /* Initialise internal driver API hooks */
 598         ret = nouveau_init_engine_ptrs(dev);
 599         if (ret)
 600                 goto out;
 601         engine = &dev_priv->engine;
 602         spin_lock_init(&dev_priv->channels.lock);
 603         spin_lock_init(&dev_priv->tile.lock);
 604         spin_lock_init(&dev_priv->context_switch_lock);
 605         spin_lock_init(&dev_priv->vm_lock);
 606
 607         /* Make the CRTCs and I2C buses accessible */
 608         ret = engine->display.early_init(dev);
 609         if (ret)
 610                 goto out;
 611
 612         /* Parse BIOS tables / Run init tables if card not POSTed */
 613         ret = nouveau_bios_init(dev);
 614         if (ret)
 615                 goto out_display_early;
 616
 617         /* workaround an odd issue on nvc1 by disabling the device's
 618          * nosnoop capability.  hopefully won't cause issues until a
 619          * better fix is found - assuming there is one...
 620          */
 621         if (dev_priv->chipset == 0xc1) {
 622                 nv_mask(dev, 0x00088080, 0x00000800, 0x00000000);
 623         }
 624
 625         /* PMC */
 626         ret = engine->mc.init(dev);
 627         if (ret)
 628                 goto out_bios;
 629
 630         /* PTIMER */
 631         ret = engine->timer.init(dev);
 632         if (ret)
 633                 goto out_mc;
 634
 635         /* PFB */
 636         ret = engine->fb.init(dev);
 637         if (ret)
 638                 goto out_timer;
 639
 640         ret = engine->vram.init(dev);
 641         if (ret)
 642                 goto out_fb;
 643
 644         /* PGPIO */
 645         ret = nouveau_gpio_create(dev);
 646         if (ret)
 647                 goto out_vram;
 648
 649         ret = nouveau_gpuobj_init(dev);
 650         if (ret)
 651                 goto out_gpio;
 652
 653         ret = engine->instmem.init(dev);
 654         if (ret)
 655                 goto out_gpuobj;
 656
 657         ret = nouveau_mem_vram_init(dev);
 658         if (ret)
 659                 goto out_instmem;
 660
 661         ret = nouveau_mem_gart_init(dev);
 662         if (ret)
 663                 goto out_ttmvram;
 664
 665         if (!dev_priv->noaccel) {
 666                 switch (dev_priv->card_type) {
 667                 case NV_04:
 668                         nv04_fifo_create(dev);
 669                         break;
 670                 case NV_10:
 671                 case NV_20:
 672                 case NV_30:
 673                         if (dev_priv->chipset < 0x17)
 674                                 nv10_fifo_create(dev);
 675                         else
 676                                 nv17_fifo_create(dev);
 677                         break;
 678                 case NV_40:
 679                         nv40_fifo_create(dev);
 680                         break;
 681                 case NV_50:
 682                         if (dev_priv->chipset == 0x50)
 683                                 nv50_fifo_create(dev);
 684                         else
 685                                 nv84_fifo_create(dev);
 686                         break;
 687                 case NV_C0:
 688                 case NV_D0:
 689                         nvc0_fifo_create(dev);
 690                         break;
 691                 case NV_E0:
 692                         nve0_fifo_create(dev);
 693                         break;
 694                 default:
 695                         break;
 696                 }
 697
 698                 switch (dev_priv->card_type) {
 699                 case NV_04:
 700                         nv04_fence_create(dev);
 701                         break;
 702                 case NV_10:
 703                 case NV_20:
 704                 case NV_30:
 705                 case NV_40:
 706                 case NV_50:
 707                         if (dev_priv->chipset < 0x84)
 708                                 nv10_fence_create(dev);
 709                         else
 710                                 nv84_fence_create(dev);
 711                         break;
 712                 case NV_C0:
 713                 case NV_D0:
 714                 case NV_E0:
 715                         nvc0_fence_create(dev);
 716                         break;
 717                 default:
 718                         break;
 719                 }
 720
 721                 switch (dev_priv->card_type) {
 722                 case NV_04:
 723                 case NV_10:
 724                 case NV_20:
 725                 case NV_30:
 726                 case NV_40:
 727                         nv04_software_create(dev);
 728                         break;
 729                 case NV_50:
 730                         nv50_software_create(dev);
 731                         break;
 732                 case NV_C0:
 733                 case NV_D0:
 734                 case NV_E0:
 735                         nvc0_software_create(dev);
 736                         break;
 737                 default:
 738                         break;
 739                 }
 740
 741                 switch (dev_priv->card_type) {
 742                 case NV_04:
 743                         nv04_graph_create(dev);
 744                         break;
 745                 case NV_10:
 746                         nv10_graph_create(dev);
 747                         break;
 748                 case NV_20:
 749                 case NV_30:
 750                         nv20_graph_create(dev);
 751                         break;
 752                 case NV_40:
 753                         nv40_graph_create(dev);
 754                         break;
 755                 case NV_50:
 756                         nv50_graph_create(dev);
 757                         break;
 758                 case NV_C0:
 759                 case NV_D0:
 760                         nvc0_graph_create(dev);
 761                         break;
 762                 case NV_E0:
 763                         nve0_graph_create(dev);
 764                         break;
 765                 default:
 766                         break;
 767                 }
 768
 769                 switch (dev_priv->chipset) {
 770                 case 0x84:
 771                 case 0x86:
 772                 case 0x92:
 773                 case 0x94:
 774                 case 0x96:
 775                 case 0xa0:
 776                         nv84_crypt_create(dev);
 777                         break;
 778                 case 0x98:
 779                 case 0xaa:
 780                 case 0xac:
 781                         nv98_crypt_create(dev);
 782                         break;
 783                 }
 784
 785                 switch (dev_priv->card_type) {
 786                 case NV_50:
 787                         switch (dev_priv->chipset) {
 788                         case 0xa3:
 789                         case 0xa5:
 790                         case 0xa8:
 791                         case 0xaf:
 792                                 nva3_copy_create(dev);
 793                                 break;
 794                         }
 795                         break;
 796                 case NV_C0:
 797                         nvc0_copy_create(dev, 0);
 798                         nvc0_copy_create(dev, 1);
 799                         break;
 800                 default:
 801                         break;
 802                 }
 803
 804                 if (dev_priv->chipset >= 0xa3 || dev_priv->chipset == 0x98) {
 805                         nv84_bsp_create(dev);
 806                         nv84_vp_create(dev);
 807                         nv98_ppp_create(dev);
 808                 } else
 809                 if (dev_priv->chipset >= 0x84) {
 810                         nv50_mpeg_create(dev);
 811                         nv84_bsp_create(dev);
 812                         nv84_vp_create(dev);
 813                 } else
 814                 if (dev_priv->chipset >= 0x50) {
 815                         nv50_mpeg_create(dev);
 816                 } else
 817                 if (dev_priv->card_type == NV_40 ||
 818                     dev_priv->chipset == 0x31 ||
 819                     dev_priv->chipset == 0x34 ||
 820                     dev_priv->chipset == 0x36) {
 821                         nv31_mpeg_create(dev);
 822                 }
 823
 824                 for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
 825                         if (dev_priv->eng[e]) {
 826                                 ret = dev_priv->eng[e]->init(dev, e);
 827                                 if (ret)
 828                                         goto out_engine;
 829                         }
 830                 }
 831         }
 832
 833         ret = nouveau_irq_init(dev);
 834         if (ret)
 835                 goto out_engine;
 836
 837         ret = nouveau_display_create(dev);
 838         if (ret)
 839                 goto out_irq;
 840
 841         nouveau_backlight_init(dev);
 842         nouveau_pm_init(dev);
 843
 844         if (dev_priv->eng[NVOBJ_ENGINE_GR]) {
 845                 ret = nouveau_card_channel_init(dev);
 846                 if (ret)
 847                         goto out_pm;
 848         }
 849
 850         if (dev->mode_config.num_crtc) {
 851                 ret = nouveau_display_init(dev);
 852                 if (ret)
 853                         goto out_chan;
 854
 855                 nouveau_fbcon_init(dev);
 856         }
 857
 858         return 0;
 859
 860 out_chan:
 861         nouveau_card_channel_fini(dev);
 862 out_pm:
 863         nouveau_pm_fini(dev);
 864         nouveau_backlight_exit(dev);
 865         nouveau_display_destroy(dev);
 866 out_irq:
 867         nouveau_irq_fini(dev);
 868 out_engine:
 869         if (!dev_priv->noaccel) {
 870                 for (e = e - 1; e >= 0; e--) {
 871                         if (!dev_priv->eng[e])
 872                                 continue;
 873                         dev_priv->eng[e]->fini(dev, e, false);
 874                         dev_priv->eng[e]->destroy(dev,e );
 875                 }
 876         }
 877         nouveau_mem_gart_fini(dev);
 878 out_ttmvram:
 879         nouveau_mem_vram_fini(dev);
 880 out_instmem:
 881         engine->instmem.takedown(dev);
 882 out_gpuobj:
 883         nouveau_gpuobj_takedown(dev);
 884 out_gpio:
 885         nouveau_gpio_destroy(dev);
 886 out_vram:
 887         engine->vram.takedown(dev);
 888 out_fb:
 889         engine->fb.takedown(dev);
 890 out_timer:
 891         engine->timer.takedown(dev);
 892 out_mc:
 893         engine->mc.takedown(dev);
 894 out_bios:
 895         nouveau_bios_takedown(dev);
 896 out_display_early:
 897         engine->display.late_takedown(dev);
 898 out:
 899         vga_client_register(dev->pdev, NULL, NULL, NULL);
 900         return ret;
 901 }
 902
 903 static void nouveau_card_takedown(struct drm_device *dev)
 904 {
 905         struct drm_nouveau_private *dev_priv = dev->dev_private;
 906         struct nouveau_engine *engine = &dev_priv->engine;
 907         int e;
 908
 909         if (dev->mode_config.num_crtc) {
 910                 nouveau_fbcon_fini(dev);
 911                 nouveau_display_fini(dev);
 912         }
 913
 914         nouveau_card_channel_fini(dev);
 915         nouveau_pm_fini(dev);
 916         nouveau_backlight_exit(dev);
 917         nouveau_display_destroy(dev);
 918
 919         if (!dev_priv->noaccel) {
 920                 for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
 921                         if (dev_priv->eng[e]) {
 922                                 dev_priv->eng[e]->fini(dev, e, false);
 923                                 dev_priv->eng[e]->destroy(dev,e );
 924                         }
 925                 }
 926         }
 927
 928         if (dev_priv->vga_ram) {
 929                 nouveau_bo_unpin(dev_priv->vga_ram);
 930                 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
 931         }
 932
 933         mutex_lock(&dev->struct_mutex);
 934         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
 935         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
 936         mutex_unlock(&dev->struct_mutex);
 937         nouveau_mem_gart_fini(dev);
 938         nouveau_mem_vram_fini(dev);
 939
 940         engine->instmem.takedown(dev);
 941         nouveau_gpuobj_takedown(dev);
 942
 943         nouveau_gpio_destroy(dev);
 944         engine->vram.takedown(dev);
 945         engine->fb.takedown(dev);
 946         engine->timer.takedown(dev);
 947         engine->mc.takedown(dev);
 948
 949         nouveau_bios_takedown(dev);
 950         engine->display.late_takedown(dev);
 951
 952         nouveau_irq_fini(dev);
 953
 954         vga_client_register(dev->pdev, NULL, NULL, NULL);
 955 }
 956
 957 int
 958 nouveau_open(struct drm_device *dev, struct drm_file *file_priv)
 959 {
 960         struct drm_nouveau_private *dev_priv = dev->dev_private;
 961         struct nouveau_fpriv *fpriv;
 962         int ret;
 963
 964         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 965         if (unlikely(!fpriv))
 966                 return -ENOMEM;
 967
 968         spin_lock_init(&fpriv->lock);
 969         INIT_LIST_HEAD(&fpriv->channels);
 970
 971         if (dev_priv->card_type == NV_50) {
 972                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL,
 973                                      &fpriv->vm);
 974                 if (ret) {
 975                         kfree(fpriv);
 976                         return ret;
 977                 }
 978         } else
 979         if (dev_priv->card_type >= NV_C0) {
 980                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL,
 981                                      &fpriv->vm);
 982                 if (ret) {
 983                         kfree(fpriv);
 984                         return ret;
 985                 }
 986         }
 987
 988         file_priv->driver_priv = fpriv;
 989         return 0;
 990 }
 991
 992 /* here a client dies, release the stuff that was allocated for its
 993  * file_priv */
 994 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
 995 {
 996         nouveau_channel_cleanup(dev, file_priv);
 997 }
 998
 999 void
1000 nouveau_postclose(struct drm_device *dev, struct drm_file *file_priv)
1001 {
1002         struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
1003         nouveau_vm_ref(NULL, &fpriv->vm, NULL);
1004         kfree(fpriv);
1005 }
1006
1007 /* first module load, setup the mmio/fb mapping */
1008 /* KMS: we need mmio at load time, not when the first drm client opens. */
1009 int nouveau_firstopen(struct drm_device *dev)
1010 {
1011         return 0;
1012 }
1013
1014 /* if we have an OF card, copy vbios to RAMIN */
1015 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
1016 {
1017 #if defined(__powerpc__)
1018         int size, i;
1019         const uint32_t *bios;
1020         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
1021         if (!dn) {
1022                 NV_INFO(dev, "Unable to get the OF node\n");
1023                 return;
1024         }
1025
1026         bios = of_get_property(dn, "NVDA,BMP", &size);
1027         if (bios) {
1028                 for (i = 0; i < size; i += 4)
1029                         nv_wi32(dev, i, bios[i/4]);
1030                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
1031         } else {
1032                 NV_INFO(dev, "Unable to get the OF bios\n");
1033         }
1034 #endif
1035 }
1036
1037 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
1038 {
1039         struct pci_dev *pdev = dev->pdev;
1040         struct apertures_struct *aper = alloc_apertures(3);
1041         if (!aper)
1042                 return NULL;
1043
1044         aper->ranges[0].base = pci_resource_start(pdev, 1);
1045         aper->ranges[0].size = pci_resource_len(pdev, 1);
1046         aper->count = 1;
1047
1048         if (pci_resource_len(pdev, 2)) {
1049                 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
1050                 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
1051                 aper->count++;
1052         }
1053
1054         if (pci_resource_len(pdev, 3)) {
1055                 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
1056                 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
1057                 aper->count++;
1058         }
1059
1060         return aper;
1061 }
1062
1063 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
1064 {
1065         struct drm_nouveau_private *dev_priv = dev->dev_private;
1066         bool primary = false;
1067         dev_priv->apertures = nouveau_get_apertures(dev);
1068         if (!dev_priv->apertures)
1069                 return -ENOMEM;
1070
1071 #ifdef CONFIG_X86
1072         primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1073 #endif
1074
1075         remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
1076         return 0;
1077 }
1078
1079 int nouveau_load(struct drm_device *dev, unsigned long flags)
1080 {
1081         struct drm_nouveau_private *dev_priv;
1082         unsigned long long offset, length;
1083         uint32_t reg0 = ~0, strap;
1084         int ret;
1085
1086         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1087         if (!dev_priv) {
1088                 ret = -ENOMEM;
1089                 goto err_out;
1090         }
1091         dev->dev_private = dev_priv;
1092         dev_priv->dev = dev;
1093
1094         pci_set_master(dev->pdev);
1095
1096         dev_priv->flags = flags & NOUVEAU_FLAGS;
1097
1098         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
1099                  dev->pci_vendor, dev->pci_device, dev->pdev->class);
1100
1101         /* first up, map the start of mmio and determine the chipset */
1102         dev_priv->mmio = ioremap(pci_resource_start(dev->pdev, 0), PAGE_SIZE);
1103         if (dev_priv->mmio) {
1104 #ifdef __BIG_ENDIAN
1105                 /* put the card into big-endian mode if it's not */
1106                 if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
1107                         nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
1108                 DRM_MEMORYBARRIER();
1109 #endif
1110
1111                 /* determine chipset and derive architecture from it */
1112                 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
1113                 if ((reg0 & 0x0f000000) > 0) {
1114                         dev_priv->chipset = (reg0 & 0xff00000) >> 20;
1115                         switch (dev_priv->chipset & 0xf0) {
1116                         case 0x10:
1117                         case 0x20:
1118                         case 0x30:
1119                                 dev_priv->card_type = dev_priv->chipset & 0xf0;
1120                                 break;
1121                         case 0x40:
1122                         case 0x60:
1123                                 dev_priv->card_type = NV_40;
1124                                 break;
1125                         case 0x50:
1126                         case 0x80:
1127                         case 0x90:
1128                         case 0xa0:
1129                                 dev_priv->card_type = NV_50;
1130                                 break;
1131                         case 0xc0:
1132                                 dev_priv->card_type = NV_C0;
1133                                 break;
1134                         case 0xd0:
1135                                 dev_priv->card_type = NV_D0;
1136                                 break;
1137                         case 0xe0:
1138                                 dev_priv->card_type = NV_E0;
1139                                 break;
1140                         default:
1141                                 break;
1142                         }
1143                 } else
1144                 if ((reg0 & 0xff00fff0) == 0x20004000) {
1145                         if (reg0 & 0x00f00000)
1146                                 dev_priv->chipset = 0x05;
1147                         else
1148                                 dev_priv->chipset = 0x04;
1149                         dev_priv->card_type = NV_04;
1150                 }
1151
1152                 iounmap(dev_priv->mmio);
1153         }
1154
1155         if (!dev_priv->card_type) {
1156                 NV_ERROR(dev, "unsupported chipset 0x%08x\n", reg0);
1157                 ret = -EINVAL;
1158                 goto err_priv;
1159         }
1160
1161         NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
1162                      dev_priv->card_type, reg0);
1163
1164         /* map the mmio regs, limiting the amount to preserve vmap space */
1165         offset = pci_resource_start(dev->pdev, 0);
1166         length = pci_resource_len(dev->pdev, 0);
1167         if (dev_priv->card_type < NV_E0)
1168                 length = min(length, (unsigned long long)0x00800000);
1169
1170         dev_priv->mmio = ioremap(offset, length);
1171         if (!dev_priv->mmio) {
1172                 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
1173                          "Please report your setup to " DRIVER_EMAIL "\n");
1174                 ret = -EINVAL;
1175                 goto err_priv;
1176         }
1177         NV_DEBUG(dev, "regs mapped ok at 0x%llx\n", offset);
1178
1179         /* determine frequency of timing crystal */
1180         strap = nv_rd32(dev, 0x101000);
1181         if ( dev_priv->chipset < 0x17 ||
1182             (dev_priv->chipset >= 0x20 && dev_priv->chipset <= 0x25))
1183                 strap &= 0x00000040;
1184         else
1185                 strap &= 0x00400040;
1186
1187         switch (strap) {
1188         case 0x00000000: dev_priv->crystal = 13500; break;
1189         case 0x00000040: dev_priv->crystal = 14318; break;
1190         case 0x00400000: dev_priv->crystal = 27000; break;
1191         case 0x00400040: dev_priv->crystal = 25000; break;
1192         }
1193
1194         NV_DEBUG(dev, "crystal freq: %dKHz\n", dev_priv->crystal);
1195
1196         /* Determine whether we'll attempt acceleration or not, some
1197          * cards are disabled by default here due to them being known
1198          * non-functional, or never been tested due to lack of hw.
1199          */
1200         dev_priv->noaccel = !!nouveau_noaccel;
1201         if (nouveau_noaccel == -1) {
1202                 switch (dev_priv->chipset) {
1203                 case 0xd9: /* known broken */
1204                 case 0xe4: /* needs binary driver firmware */
1205                 case 0xe7: /* needs binary driver firmware */
1206                         NV_INFO(dev, "acceleration disabled by default, pass "
1207                                      "noaccel=0 to force enable\n");
1208                         dev_priv->noaccel = true;
1209                         break;
1210                 default:
1211                         dev_priv->noaccel = false;
1212                         break;
1213                 }
1214         }
1215
1216         ret = nouveau_remove_conflicting_drivers(dev);
1217         if (ret)
1218                 goto err_mmio;
1219
1220         /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
1221         if (dev_priv->card_type >= NV_40) {
1222                 int ramin_bar = 2;
1223                 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
1224                         ramin_bar = 3;
1225
1226                 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
1227                 dev_priv->ramin =
1228                         ioremap(pci_resource_start(dev->pdev, ramin_bar),
1229                                 dev_priv->ramin_size);
1230                 if (!dev_priv->ramin) {
1231                         NV_ERROR(dev, "Failed to map PRAMIN BAR\n");
1232                         ret = -ENOMEM;
1233                         goto err_mmio;
1234                 }
1235         } else {
1236                 dev_priv->ramin_size = 1 * 1024 * 1024;
1237                 dev_priv->ramin = ioremap(offset + NV_RAMIN,
1238                                           dev_priv->ramin_size);
1239                 if (!dev_priv->ramin) {
1240                         NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
1241                         ret = -ENOMEM;
1242                         goto err_mmio;
1243                 }
1244         }
1245
1246         nouveau_OF_copy_vbios_to_ramin(dev);
1247
1248         /* Special flags */
1249         if (dev->pci_device == 0x01a0)
1250                 dev_priv->flags |= NV_NFORCE;
1251         else if (dev->pci_device == 0x01f0)
1252                 dev_priv->flags |= NV_NFORCE2;
1253
1254         /* For kernel modesetting, init card now and bring up fbcon */
1255         ret = nouveau_card_init(dev);
1256         if (ret)
1257                 goto err_ramin;
1258
1259         return 0;
1260
1261 err_ramin:
1262         iounmap(dev_priv->ramin);
1263 err_mmio:
1264         iounmap(dev_priv->mmio);
1265 err_priv:
1266         kfree(dev_priv);
1267         dev->dev_private = NULL;
1268 err_out:
1269         return ret;
1270 }
1271
1272 void nouveau_lastclose(struct drm_device *dev)
1273 {
1274         vga_switcheroo_process_delayed_switch();
1275 }
1276
1277 int nouveau_unload(struct drm_device *dev)
1278 {
1279         struct drm_nouveau_private *dev_priv = dev->dev_private;
1280
1281         nouveau_card_takedown(dev);
1282
1283         iounmap(dev_priv->mmio);
1284         iounmap(dev_priv->ramin);
1285
1286         kfree(dev_priv);
1287         dev->dev_private = NULL;
1288         return 0;
1289 }
1290
1291 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
1292                                                 struct drm_file *file_priv)
1293 {
1294         struct drm_nouveau_private *dev_priv = dev->dev_private;
1295         struct drm_nouveau_getparam *getparam = data;
1296
1297         switch (getparam->param) {
1298         case NOUVEAU_GETPARAM_CHIPSET_ID:
1299                 getparam->value = dev_priv->chipset;
1300                 break;
1301         case NOUVEAU_GETPARAM_PCI_VENDOR:
1302                 getparam->value = dev->pci_vendor;
1303                 break;
1304         case NOUVEAU_GETPARAM_PCI_DEVICE:
1305                 getparam->value = dev->pci_device;
1306                 break;
1307         case NOUVEAU_GETPARAM_BUS_TYPE:
1308                 if (drm_pci_device_is_agp(dev))
1309                         getparam->value = NV_AGP;
1310                 else if (pci_is_pcie(dev->pdev))
1311                         getparam->value = NV_PCIE;
1312                 else
1313                         getparam->value = NV_PCI;
1314                 break;
1315         case NOUVEAU_GETPARAM_FB_SIZE:
1316                 getparam->value = dev_priv->fb_available_size;
1317                 break;
1318         case NOUVEAU_GETPARAM_AGP_SIZE:
1319                 getparam->value = dev_priv->gart_info.aper_size;
1320                 break;
1321         case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1322                 getparam->value = 0; /* deprecated */
1323                 break;
1324         case NOUVEAU_GETPARAM_PTIMER_TIME:
1325                 getparam->value = dev_priv->engine.timer.read(dev);
1326                 break;
1327         case NOUVEAU_GETPARAM_HAS_BO_USAGE:
1328                 getparam->value = 1;
1329                 break;
1330         case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
1331                 getparam->value = 1;
1332                 break;
1333         case NOUVEAU_GETPARAM_GRAPH_UNITS:
1334                 /* NV40 and NV50 versions are quite different, but register
1335                  * address is the same. User is supposed to know the card
1336                  * family anyway... */
1337                 if (dev_priv->chipset >= 0x40) {
1338                         getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1339                         break;
1340                 }
1341                 /* FALLTHRU */
1342         default:
1343                 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
1344                 return -EINVAL;
1345         }
1346
1347         return 0;
1348 }
1349
1350 int
1351 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1352                        struct drm_file *file_priv)
1353 {
1354         struct drm_nouveau_setparam *setparam = data;
1355
1356         switch (setparam->param) {
1357         default:
1358                 NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
1359                 return -EINVAL;
1360         }
1361
1362         return 0;
1363 }
1364
1365 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1366 bool
1367 nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
1368                 uint32_t reg, uint32_t mask, uint32_t val)
1369 {
1370         struct drm_nouveau_private *dev_priv = dev->dev_private;
1371         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1372         uint64_t start = ptimer->read(dev);
1373
1374         do {
1375                 if ((nv_rd32(dev, reg) & mask) == val)
1376                         return true;
1377         } while (ptimer->read(dev) - start < timeout);
1378
1379         return false;
1380 }
1381
1382 /* Wait until (value(reg) & mask) != val, up until timeout has hit */
1383 bool
1384 nouveau_wait_ne(struct drm_device *dev, uint64_t timeout,
1385                 uint32_t reg, uint32_t mask, uint32_t val)
1386 {
1387         struct drm_nouveau_private *dev_priv = dev->dev_private;
1388         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1389         uint64_t start = ptimer->read(dev);
1390
1391         do {
1392                 if ((nv_rd32(dev, reg) & mask) != val)
1393                         return true;
1394         } while (ptimer->read(dev) - start < timeout);
1395
1396         return false;
1397 }
1398
1399 /* Wait until cond(data) == true, up until timeout has hit */
1400 bool
1401 nouveau_wait_cb(struct drm_device *dev, u64 timeout,
1402                 bool (*cond)(void *), void *data)
1403 {
1404         struct drm_nouveau_private *dev_priv = dev->dev_private;
1405         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1406         u64 start = ptimer->read(dev);
1407
1408         do {
1409                 if (cond(data) == true)
1410                         return true;
1411         } while (ptimer->read(dev) - start < timeout);
1412
1413         return false;
1414 }
1415
1416 /* Waits for PGRAPH to go completely idle */
1417 bool nouveau_wait_for_idle(struct drm_device *dev)
1418 {
1419         struct drm_nouveau_private *dev_priv = dev->dev_private;
1420         uint32_t mask = ~0;
1421
1422         if (dev_priv->card_type == NV_40)
1423                 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1424
1425         if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
1426                 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1427                          nv_rd32(dev, NV04_PGRAPH_STATUS));
1428                 return false;
1429         }
1430
1431         return true;
1432 }
1433