2 * Copyright 1993-2003 NVIDIA, Corporation
3 * Copyright 2006 Dave Airlie
4 * Copyright 2007 Maarten Maathuis
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
27 #include "drm_crtc_helper.h"
29 #include "nouveau_drv.h"
30 #include "nouveau_encoder.h"
31 #include "nouveau_connector.h"
32 #include "nouveau_crtc.h"
33 #include "nouveau_fb.h"
34 #include "nouveau_hw.h"
36 #include "nouveau_fbcon.h"
39 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
40 struct drm_framebuffer *old_fb);
43 crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
45 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,
46 crtcstate->CRTC[index]);
49 static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level)
51 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
52 struct drm_device *dev = crtc->dev;
53 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
55 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level;
56 if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) {
57 regp->CRTC[NV_CIO_CRE_CSB] = 0x80;
58 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2;
59 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B);
61 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB);
64 static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level)
66 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
67 struct drm_device *dev = crtc->dev;
68 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
70 nv_crtc->sharpness = level;
71 if (level < 0) /* blur is in hw range 0x3f -> 0x20 */
73 regp->ramdac_634 = level;
74 NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634);
77 #define PLLSEL_VPLL1_MASK \
78 (NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL \
79 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2)
80 #define PLLSEL_VPLL2_MASK \
81 (NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2 \
82 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2)
83 #define PLLSEL_TV_MASK \
84 (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 \
85 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1 \
86 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 \
87 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2)
89 /* NV4x 0x40.. pll notes:
90 * gpu pll: 0x4000 + 0x4004
91 * ?gpu? pll: 0x4008 + 0x400c
92 * vpll1: 0x4010 + 0x4014
93 * vpll2: 0x4018 + 0x401c
94 * mpll: 0x4020 + 0x4024
95 * mpll: 0x4038 + 0x403c
97 * the first register of each pair has some unknown details:
98 * bits 0-7: redirected values from elsewhere? (similar to PLL_SETUP_CONTROL?)
99 * bits 20-23: (mpll) something to do with post divider?
100 * bits 28-31: related to single stage mode? (bit 8/12)
103 static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock)
105 struct drm_device *dev = crtc->dev;
106 struct drm_nouveau_private *dev_priv = dev->dev_private;
107 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
108 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
109 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
110 struct nouveau_pll_vals *pv = ®p->pllvals;
111 struct nvbios_pll pll_lim;
113 if (get_pll_limits(dev, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0, &pll_lim))
116 /* NM2 == 0 is used to determine single stage mode on two stage plls */
119 /* for newer nv4x the blob uses only the first stage of the vpll below a
120 * certain clock. for a certain nv4b this is 150MHz. since the max
121 * output frequency of the first stage for this card is 300MHz, it is
122 * assumed the threshold is given by vco1 maxfreq/2
124 /* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6,
125 * not 8, others unknown), the blob always uses both plls. no problem
126 * has yet been observed in allowing the use a single stage pll on all
127 * nv43 however. the behaviour of single stage use is untested on nv40
129 if (dev_priv->chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2))
130 memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2));
132 if (!nouveau_calc_pll_mnp(dev, &pll_lim, dot_clock, pv))
135 state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK;
137 /* The blob uses this always, so let's do the same */
138 if (dev_priv->card_type == NV_40)
139 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE;
140 /* again nv40 and some nv43 act more like nv3x as described above */
141 if (dev_priv->chipset < 0x41)
142 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL |
143 NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL;
144 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK;
147 NV_DEBUG_KMS(dev, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n",
148 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P);
150 NV_DEBUG_KMS(dev, "vpll: n %d m %d log2p %d\n",
151 pv->N1, pv->M1, pv->log2P);
153 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
157 nv_crtc_dpms(struct drm_crtc *crtc, int mode)
159 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
160 struct drm_device *dev = crtc->dev;
161 unsigned char seq1 = 0, crtc17 = 0;
162 unsigned char crtc1A;
164 NV_DEBUG_KMS(dev, "Setting dpms mode %d on CRTC %d\n", mode,
167 if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */
170 nv_crtc->last_dpms = mode;
172 if (nv_two_heads(dev))
173 NVSetOwner(dev, nv_crtc->index);
175 /* nv4ref indicates these two RPC1 bits inhibit h/v sync */
176 crtc1A = NVReadVgaCrtc(dev, nv_crtc->index,
177 NV_CIO_CRE_RPC1_INDEX) & ~0xC0;
179 case DRM_MODE_DPMS_STANDBY:
180 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
185 case DRM_MODE_DPMS_SUSPEND:
186 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
191 case DRM_MODE_DPMS_OFF:
192 /* Screen: Off; HSync: Off, VSync: Off */
197 case DRM_MODE_DPMS_ON:
199 /* Screen: On; HSync: On, VSync: On */
205 NVVgaSeqReset(dev, nv_crtc->index, true);
206 /* Each head has it's own sequencer, so we can turn it off when we want */
207 seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20);
208 NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1);
209 crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80);
211 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17);
212 NVVgaSeqReset(dev, nv_crtc->index, false);
214 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A);
218 nv_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
219 struct drm_display_mode *adjusted_mode)
225 nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode)
227 struct drm_device *dev = crtc->dev;
228 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
229 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
230 struct drm_framebuffer *fb = crtc->fb;
232 /* Calculate our timings */
233 int horizDisplay = (mode->crtc_hdisplay >> 3) - 1;
234 int horizStart = (mode->crtc_hsync_start >> 3) + 1;
235 int horizEnd = (mode->crtc_hsync_end >> 3) + 1;
236 int horizTotal = (mode->crtc_htotal >> 3) - 5;
237 int horizBlankStart = (mode->crtc_hdisplay >> 3) - 1;
238 int horizBlankEnd = (mode->crtc_htotal >> 3) - 1;
239 int vertDisplay = mode->crtc_vdisplay - 1;
240 int vertStart = mode->crtc_vsync_start - 1;
241 int vertEnd = mode->crtc_vsync_end - 1;
242 int vertTotal = mode->crtc_vtotal - 2;
243 int vertBlankStart = mode->crtc_vdisplay - 1;
244 int vertBlankEnd = mode->crtc_vtotal - 1;
246 struct drm_encoder *encoder;
247 bool fp_output = false;
249 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
250 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
252 if (encoder->crtc == crtc &&
253 (nv_encoder->dcb->type == DCB_OUTPUT_LVDS ||
254 nv_encoder->dcb->type == DCB_OUTPUT_TMDS))
259 vertStart = vertTotal - 3;
260 vertEnd = vertTotal - 2;
261 vertBlankStart = vertStart;
262 horizStart = horizTotal - 5;
263 horizEnd = horizTotal - 2;
264 horizBlankEnd = horizTotal + 4;
266 if (dev->overlayAdaptor && dev_priv->card_type >= NV_10)
267 /* This reportedly works around some video overlay bandwidth problems */
272 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
276 ErrorF("horizDisplay: 0x%X \n", horizDisplay);
277 ErrorF("horizStart: 0x%X \n", horizStart);
278 ErrorF("horizEnd: 0x%X \n", horizEnd);
279 ErrorF("horizTotal: 0x%X \n", horizTotal);
280 ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
281 ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
282 ErrorF("vertDisplay: 0x%X \n", vertDisplay);
283 ErrorF("vertStart: 0x%X \n", vertStart);
284 ErrorF("vertEnd: 0x%X \n", vertEnd);
285 ErrorF("vertTotal: 0x%X \n", vertTotal);
286 ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
287 ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
291 * compute correct Hsync & Vsync polarity
293 if ((mode->flags & (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))
294 && (mode->flags & (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) {
296 regp->MiscOutReg = 0x23;
297 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
298 regp->MiscOutReg |= 0x40;
299 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
300 regp->MiscOutReg |= 0x80;
302 int vdisplay = mode->vdisplay;
303 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
306 vdisplay *= mode->vscan;
308 regp->MiscOutReg = 0xA3; /* +hsync -vsync */
309 else if (vdisplay < 480)
310 regp->MiscOutReg = 0x63; /* -hsync +vsync */
311 else if (vdisplay < 768)
312 regp->MiscOutReg = 0xE3; /* -hsync -vsync */
314 regp->MiscOutReg = 0x23; /* +hsync +vsync */
317 regp->MiscOutReg |= (mode->clock_index & 0x03) << 2;
322 regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00;
323 /* 0x20 disables the sequencer */
324 if (mode->flags & DRM_MODE_FLAG_CLKDIV2)
325 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29;
327 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21;
328 regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F;
329 regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00;
330 regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E;
335 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal;
336 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay;
337 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart;
338 regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) |
339 XLATE(horizBlankEnd, 0, NV_CIO_CR_HBE_4_0);
340 regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart;
341 regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) |
342 XLATE(horizEnd, 0, NV_CIO_CR_HRE_4_0);
343 regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal;
344 regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) |
345 XLATE(vertDisplay, 9, NV_CIO_CR_OVL_VDE_9) |
346 XLATE(vertTotal, 9, NV_CIO_CR_OVL_VDT_9) |
348 XLATE(vertBlankStart, 8, NV_CIO_CR_OVL_VBS_8) |
349 XLATE(vertStart, 8, NV_CIO_CR_OVL_VRS_8) |
350 XLATE(vertDisplay, 8, NV_CIO_CR_OVL_VDE_8) |
351 XLATE(vertTotal, 8, NV_CIO_CR_OVL_VDT_8);
352 regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00;
353 regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) |
355 XLATE(vertBlankStart, 9, NV_CIO_CR_CELL_HT_VBS_9);
356 regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00;
357 regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00;
358 regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00;
359 regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00;
360 regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00;
361 regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00;
362 regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart;
363 regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0);
364 regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay;
365 /* framebuffer can be larger than crtc scanout area. */
366 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8;
367 regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00;
368 regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart;
369 regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd;
370 regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43;
371 regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff;
374 * Some extended CRTC registers (they are not saved with the rest of the vga regs).
377 /* framebuffer can be larger than crtc scanout area. */
378 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
379 XLATE(fb->pitches[0] / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
380 regp->CRTC[NV_CIO_CRE_42] =
381 XLATE(fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11);
382 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ?
383 MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00;
384 regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) |
385 XLATE(vertBlankStart, 10, NV_CIO_CRE_LSR_VBS_10) |
386 XLATE(vertStart, 10, NV_CIO_CRE_LSR_VRS_10) |
387 XLATE(vertDisplay, 10, NV_CIO_CRE_LSR_VDE_10) |
388 XLATE(vertTotal, 10, NV_CIO_CRE_LSR_VDT_10);
389 regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) |
390 XLATE(horizBlankStart, 8, NV_CIO_CRE_HEB_HBS_8) |
391 XLATE(horizDisplay, 8, NV_CIO_CRE_HEB_HDE_8) |
392 XLATE(horizTotal, 8, NV_CIO_CRE_HEB_HDT_8);
393 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) |
394 XLATE(vertStart, 11, NV_CIO_CRE_EBR_VRS_11) |
395 XLATE(vertDisplay, 11, NV_CIO_CRE_EBR_VDE_11) |
396 XLATE(vertTotal, 11, NV_CIO_CRE_EBR_VDT_11);
398 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
399 horizTotal = (horizTotal >> 1) & ~1;
400 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal;
401 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8);
403 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */
406 * Graphics Display Controller
408 regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00;
409 regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00;
410 regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00;
411 regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00;
412 regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00;
413 regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */
414 regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */
415 regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F;
416 regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF;
418 regp->Attribute[0] = 0x00; /* standard colormap translation */
419 regp->Attribute[1] = 0x01;
420 regp->Attribute[2] = 0x02;
421 regp->Attribute[3] = 0x03;
422 regp->Attribute[4] = 0x04;
423 regp->Attribute[5] = 0x05;
424 regp->Attribute[6] = 0x06;
425 regp->Attribute[7] = 0x07;
426 regp->Attribute[8] = 0x08;
427 regp->Attribute[9] = 0x09;
428 regp->Attribute[10] = 0x0A;
429 regp->Attribute[11] = 0x0B;
430 regp->Attribute[12] = 0x0C;
431 regp->Attribute[13] = 0x0D;
432 regp->Attribute[14] = 0x0E;
433 regp->Attribute[15] = 0x0F;
434 regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */
436 regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00;
437 regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */
438 regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00;
439 regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00;
443 * Sets up registers for the given mode/adjusted_mode pair.
445 * The clocks, CRTCs and outputs attached to this CRTC must be off.
447 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
448 * be easily turned on/off after this.
451 nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode)
453 struct drm_device *dev = crtc->dev;
454 struct drm_nouveau_private *dev_priv = dev->dev_private;
455 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
456 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
457 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
458 struct drm_encoder *encoder;
459 bool lvds_output = false, tmds_output = false, tv_output = false,
460 off_chip_digital = false;
462 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
463 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
464 bool digital = false;
466 if (encoder->crtc != crtc)
469 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS)
470 digital = lvds_output = true;
471 if (nv_encoder->dcb->type == DCB_OUTPUT_TV)
473 if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS)
474 digital = tmds_output = true;
475 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && digital)
476 off_chip_digital = true;
479 /* Registers not directly related to the (s)vga mode */
481 /* What is the meaning of this register? */
482 /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
483 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5);
485 regp->crtc_eng_ctrl = 0;
486 /* Except for rare conditions I2C is enabled on the primary crtc */
487 if (nv_crtc->index == 0)
488 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C;
490 /* Set overlay to desired crtc. */
491 if (dev->overlayAdaptor) {
492 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(dev);
493 if (pPriv->overlayCRTC == nv_crtc->index)
494 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY;
498 /* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */
499 regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 |
500 NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 |
501 NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM;
502 if (dev_priv->chipset >= 0x11)
503 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32;
504 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
505 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE;
507 /* Unblock some timings */
508 regp->CRTC[NV_CIO_CRE_53] = 0;
509 regp->CRTC[NV_CIO_CRE_54] = 0;
511 /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
513 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11;
514 else if (tmds_output)
515 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88;
517 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22;
519 /* These values seem to vary */
520 /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
521 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX];
523 nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation);
525 /* probably a scratch reg, but kept for cargo-cult purposes:
526 * bit0: crtc0?, head A
528 * bit7: (only in X), head A
530 if (nv_crtc->index == 0)
531 regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80;
533 /* The blob seems to take the current value from crtc 0, add 4 to that
534 * and reuse the old value for crtc 1 */
535 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
537 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4;
539 /* the blob sometimes sets |= 0x10 (which is the same as setting |=
540 * 1 << 30 on 0x60.830), for no apparent reason */
541 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital;
543 if (dev_priv->card_type >= NV_30)
544 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1;
546 regp->crtc_830 = mode->crtc_vdisplay - 3;
547 regp->crtc_834 = mode->crtc_vdisplay - 1;
549 if (dev_priv->card_type == NV_40)
550 /* This is what the blob does */
551 regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850);
553 if (dev_priv->card_type >= NV_30)
554 regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT);
556 if (dev_priv->card_type >= NV_10)
557 regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC;
559 regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC;
562 if (dev_priv->card_type == NV_40) {
563 regp->CRTC[NV_CIO_CRE_85] = 0xFF;
564 regp->CRTC[NV_CIO_CRE_86] = 0x1;
567 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (crtc->fb->depth + 1) / 8;
568 /* Enable slaved mode (called MODE_TV in nv4ref.h) */
569 if (lvds_output || tmds_output || tv_output)
570 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7);
572 /* Generic PRAMDAC regs */
574 if (dev_priv->card_type >= NV_10)
575 /* Only bit that bios and blob set. */
576 regp->nv10_cursync = (1 << 25);
578 regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS |
579 NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL |
580 NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON;
581 if (crtc->fb->depth == 16)
582 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
583 if (dev_priv->chipset >= 0x11)
584 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG;
586 regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */
589 nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness);
591 /* Some values the blob sets */
592 regp->ramdac_8c0 = 0x100;
593 regp->ramdac_a20 = 0x0;
594 regp->ramdac_a24 = 0xfffff;
595 regp->ramdac_a34 = 0x1;
599 * Sets up registers for the given mode/adjusted_mode pair.
601 * The clocks, CRTCs and outputs attached to this CRTC must be off.
603 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
604 * be easily turned on/off after this.
607 nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
608 struct drm_display_mode *adjusted_mode,
609 int x, int y, struct drm_framebuffer *old_fb)
611 struct drm_device *dev = crtc->dev;
612 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
613 struct drm_nouveau_private *dev_priv = dev->dev_private;
615 NV_DEBUG_KMS(dev, "CTRC mode on CRTC %d:\n", nv_crtc->index);
616 drm_mode_debug_printmodeline(adjusted_mode);
618 /* unlock must come after turning off FP_TG_CONTROL in output_prepare */
619 nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1);
621 nv_crtc_mode_set_vga(crtc, adjusted_mode);
622 /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */
623 if (dev_priv->card_type == NV_40)
624 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
625 nv_crtc_mode_set_regs(crtc, adjusted_mode);
626 nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock);
630 static void nv_crtc_save(struct drm_crtc *crtc)
632 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
633 struct drm_device *dev = crtc->dev;
634 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
635 struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index];
636 struct nv04_mode_state *saved = &nv04_display(dev)->saved_reg;
637 struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index];
639 if (nv_two_heads(crtc->dev))
640 NVSetOwner(crtc->dev, nv_crtc->index);
642 nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved);
644 /* init some state to saved value */
645 state->sel_clk = saved->sel_clk & ~(0x5 << 16);
646 crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX];
647 state->pllsel = saved->pllsel & ~(PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK);
648 crtc_state->gpio_ext = crtc_saved->gpio_ext;
651 static void nv_crtc_restore(struct drm_crtc *crtc)
653 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
654 struct drm_device *dev = crtc->dev;
655 int head = nv_crtc->index;
656 uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21];
658 if (nv_two_heads(crtc->dev))
659 NVSetOwner(crtc->dev, head);
661 nouveau_hw_load_state(crtc->dev, head, &nv04_display(dev)->saved_reg);
662 nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21);
664 nv_crtc->last_dpms = NV_DPMS_CLEARED;
667 static void nv_crtc_prepare(struct drm_crtc *crtc)
669 struct drm_device *dev = crtc->dev;
670 struct drm_nouveau_private *dev_priv = dev->dev_private;
671 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
672 struct drm_crtc_helper_funcs *funcs = crtc->helper_private;
674 if (nv_two_heads(dev))
675 NVSetOwner(dev, nv_crtc->index);
677 drm_vblank_pre_modeset(dev, nv_crtc->index);
678 funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
680 NVBlankScreen(dev, nv_crtc->index, true);
682 /* Some more preparation. */
683 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA);
684 if (dev_priv->card_type == NV_40) {
685 uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900);
686 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000);
690 static void nv_crtc_commit(struct drm_crtc *crtc)
692 struct drm_device *dev = crtc->dev;
693 struct drm_crtc_helper_funcs *funcs = crtc->helper_private;
694 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
696 nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
697 nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL);
700 /* turn on LFB swapping */
702 uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR);
703 tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG);
704 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp);
708 funcs->dpms(crtc, DRM_MODE_DPMS_ON);
709 drm_vblank_post_modeset(dev, nv_crtc->index);
712 static void nv_crtc_destroy(struct drm_crtc *crtc)
714 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
716 NV_DEBUG_KMS(crtc->dev, "\n");
721 drm_crtc_cleanup(crtc);
723 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
724 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
729 nv_crtc_gamma_load(struct drm_crtc *crtc)
731 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
732 struct drm_device *dev = nv_crtc->base.dev;
733 struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs;
736 rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC;
737 for (i = 0; i < 256; i++) {
738 rgbs[i].r = nv_crtc->lut.r[i] >> 8;
739 rgbs[i].g = nv_crtc->lut.g[i] >> 8;
740 rgbs[i].b = nv_crtc->lut.b[i] >> 8;
743 nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
747 nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, uint32_t start,
750 int end = (start + size > 256) ? 256 : start + size, i;
751 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
753 for (i = start; i < end; i++) {
754 nv_crtc->lut.r[i] = r[i];
755 nv_crtc->lut.g[i] = g[i];
756 nv_crtc->lut.b[i] = b[i];
759 /* We need to know the depth before we upload, but it's possible to
760 * get called before a framebuffer is bound. If this is the case,
761 * mark the lut values as dirty by setting depth==0, and it'll be
762 * uploaded on the first mode_set_base()
764 if (!nv_crtc->base.fb) {
765 nv_crtc->lut.depth = 0;
769 nv_crtc_gamma_load(crtc);
773 nv04_crtc_do_mode_set_base(struct drm_crtc *crtc,
774 struct drm_framebuffer *passed_fb,
775 int x, int y, bool atomic)
777 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
778 struct drm_device *dev = crtc->dev;
779 struct drm_nouveau_private *dev_priv = dev->dev_private;
780 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
781 struct drm_framebuffer *drm_fb;
782 struct nouveau_framebuffer *fb;
783 int arb_burst, arb_lwm;
786 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
789 if (!atomic && !crtc->fb) {
790 NV_DEBUG_KMS(dev, "No FB bound\n");
795 /* If atomic, we want to switch to the fb we were passed, so
796 * now we update pointers to do that. (We don't pin; just
797 * assume we're already pinned and update the base address.)
801 fb = nouveau_framebuffer(passed_fb);
804 fb = nouveau_framebuffer(crtc->fb);
805 /* If not atomic, we can go ahead and pin, and unpin the
806 * old fb we were passed.
808 ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM);
813 struct nouveau_framebuffer *ofb = nouveau_framebuffer(passed_fb);
814 nouveau_bo_unpin(ofb->nvbo);
818 nv_crtc->fb.offset = fb->nvbo->bo.offset;
820 if (nv_crtc->lut.depth != drm_fb->depth) {
821 nv_crtc->lut.depth = drm_fb->depth;
822 nv_crtc_gamma_load(crtc);
825 /* Update the framebuffer format. */
826 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3;
827 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (crtc->fb->depth + 1) / 8;
828 regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
829 if (crtc->fb->depth == 16)
830 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
831 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX);
832 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL,
833 regp->ramdac_gen_ctrl);
835 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3;
836 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
837 XLATE(drm_fb->pitches[0] >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
838 regp->CRTC[NV_CIO_CRE_42] =
839 XLATE(drm_fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11);
840 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX);
841 crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX);
842 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42);
844 /* Update the framebuffer location. */
845 regp->fb_start = nv_crtc->fb.offset & ~3;
846 regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->bits_per_pixel / 8);
847 nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start);
849 /* Update the arbitration parameters. */
850 nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->bits_per_pixel,
851 &arb_burst, &arb_lwm);
853 regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst;
854 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff;
855 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX);
856 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX);
858 if (dev_priv->card_type >= NV_20) {
859 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8;
860 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47);
867 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
868 struct drm_framebuffer *old_fb)
870 return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false);
874 nv04_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
875 struct drm_framebuffer *fb,
876 int x, int y, enum mode_set_atomic state)
878 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
879 struct drm_device *dev = dev_priv->dev;
881 if (state == ENTER_ATOMIC_MODE_SET)
882 nouveau_fbcon_save_disable_accel(dev);
884 nouveau_fbcon_restore_accel(dev);
886 return nv04_crtc_do_mode_set_base(crtc, fb, x, y, true);
889 static void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src,
890 struct nouveau_bo *dst)
892 int width = nv_cursor_width(dev);
896 for (i = 0; i < width; i++) {
897 for (j = 0; j < width; j++) {
898 pixel = nouveau_bo_rd32(src, i*64 + j);
900 nouveau_bo_wr16(dst, i*width + j, (pixel & 0x80000000) >> 16
901 | (pixel & 0xf80000) >> 9
902 | (pixel & 0xf800) >> 6
903 | (pixel & 0xf8) >> 3);
908 static void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src,
909 struct nouveau_bo *dst)
914 /* nv11+ supports premultiplied (PM), or non-premultiplied (NPM) alpha
915 * cursors (though NPM in combination with fp dithering may not work on
916 * nv11, from "nv" driver history)
917 * NPM mode needs NV_PCRTC_CURSOR_CONFIG_ALPHA_BLEND set and is what the
918 * blob uses, however we get given PM cursors so we use PM mode
920 for (i = 0; i < 64 * 64; i++) {
921 pixel = nouveau_bo_rd32(src, i);
923 /* hw gets unhappy if alpha <= rgb values. for a PM image "less
924 * than" shouldn't happen; fix "equal to" case by adding one to
925 * alpha channel (slightly inaccurate, but so is attempting to
926 * get back to NPM images, due to limits of integer precision)
929 if (alpha > 0 && alpha < 255)
930 pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24);
934 struct drm_nouveau_private *dev_priv = dev->dev_private;
936 if (dev_priv->chipset == 0x11) {
937 pixel = ((pixel & 0x000000ff) << 24) |
938 ((pixel & 0x0000ff00) << 8) |
939 ((pixel & 0x00ff0000) >> 8) |
940 ((pixel & 0xff000000) >> 24);
945 nouveau_bo_wr32(dst, i, pixel);
950 nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
951 uint32_t buffer_handle, uint32_t width, uint32_t height)
953 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
954 struct drm_device *dev = dev_priv->dev;
955 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
956 struct nouveau_bo *cursor = NULL;
957 struct drm_gem_object *gem;
960 if (!buffer_handle) {
961 nv_crtc->cursor.hide(nv_crtc, true);
965 if (width != 64 || height != 64)
968 gem = drm_gem_object_lookup(dev, file_priv, buffer_handle);
971 cursor = nouveau_gem_object(gem);
973 ret = nouveau_bo_map(cursor);
977 if (dev_priv->chipset >= 0x11)
978 nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
980 nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
982 nouveau_bo_unmap(cursor);
983 nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->bo.offset;
984 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
985 nv_crtc->cursor.show(nv_crtc, true);
987 drm_gem_object_unreference_unlocked(gem);
992 nv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
994 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
996 nv_crtc->cursor.set_pos(nv_crtc, x, y);
1000 static const struct drm_crtc_funcs nv04_crtc_funcs = {
1001 .save = nv_crtc_save,
1002 .restore = nv_crtc_restore,
1003 .cursor_set = nv04_crtc_cursor_set,
1004 .cursor_move = nv04_crtc_cursor_move,
1005 .gamma_set = nv_crtc_gamma_set,
1006 .set_config = drm_crtc_helper_set_config,
1007 .page_flip = nouveau_crtc_page_flip,
1008 .destroy = nv_crtc_destroy,
1011 static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = {
1012 .dpms = nv_crtc_dpms,
1013 .prepare = nv_crtc_prepare,
1014 .commit = nv_crtc_commit,
1015 .mode_fixup = nv_crtc_mode_fixup,
1016 .mode_set = nv_crtc_mode_set,
1017 .mode_set_base = nv04_crtc_mode_set_base,
1018 .mode_set_base_atomic = nv04_crtc_mode_set_base_atomic,
1019 .load_lut = nv_crtc_gamma_load,
1023 nv04_crtc_create(struct drm_device *dev, int crtc_num)
1025 struct nouveau_crtc *nv_crtc;
1028 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
1032 for (i = 0; i < 256; i++) {
1033 nv_crtc->lut.r[i] = i << 8;
1034 nv_crtc->lut.g[i] = i << 8;
1035 nv_crtc->lut.b[i] = i << 8;
1037 nv_crtc->lut.depth = 0;
1039 nv_crtc->index = crtc_num;
1040 nv_crtc->last_dpms = NV_DPMS_CLEARED;
1042 drm_crtc_init(dev, &nv_crtc->base, &nv04_crtc_funcs);
1043 drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs);
1044 drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256);
1046 ret = nouveau_bo_new(dev, 64*64*4, 0x100, TTM_PL_FLAG_VRAM,
1047 0, 0x0000, NULL, &nv_crtc->cursor.nvbo);
1049 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
1051 ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
1053 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
1056 nv04_cursor_init(nv_crtc);