2 * Copyright 2003 NVIDIA, Corporation
3 * Copyright 2006 Dave Airlie
4 * Copyright 2007 Maarten Maathuis
5 * Copyright 2007-2009 Stuart Bennett
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 #include "drm_crtc_helper.h"
30 #include "nouveau_drv.h"
31 #include "nouveau_encoder.h"
32 #include "nouveau_connector.h"
33 #include "nouveau_crtc.h"
34 #include "nouveau_hw.h"
37 #include <subdev/bios/gpio.h>
39 int nv04_dac_output_offset(struct drm_encoder *encoder)
41 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
44 if (dcb->or & (8 | DCB_OUTPUT_C))
46 if (dcb->or & (8 | DCB_OUTPUT_B))
53 * arbitrary limit to number of sense oscillations tolerated in one sample
54 * period (observed to be at least 13 in "nvidia")
56 #define MAX_HBLANK_OSC 20
59 * arbitrary limit to number of conflicting sample pairs to tolerate at a
60 * voltage step (observed to be at least 5 in "nvidia")
62 #define MAX_SAMPLE_PAIRS 10
64 static int sample_load_twice(struct drm_device *dev, bool sense[2])
68 for (i = 0; i < 2; i++) {
69 bool sense_a, sense_b, sense_b_prime;
73 * wait for bit 0 clear -- out of hblank -- (say reg value 0x4),
74 * then wait for transition 0x4->0x5->0x4: enter hblank, leave
76 * use a 10ms timeout (guards against crtc being inactive, in
77 * which case blank state would never change)
79 if (!nouveau_wait_eq(dev, 10000000, NV_PRMCIO_INP0__COLOR,
80 0x00000001, 0x00000000))
82 if (!nouveau_wait_eq(dev, 10000000, NV_PRMCIO_INP0__COLOR,
83 0x00000001, 0x00000001))
85 if (!nouveau_wait_eq(dev, 10000000, NV_PRMCIO_INP0__COLOR,
86 0x00000001, 0x00000000))
90 /* when level triggers, sense is _LO_ */
91 sense_a = nv_rd08(dev, NV_PRMCIO_INP0) & 0x10;
93 /* take another reading until it agrees with sense_a... */
96 sense_b = nv_rd08(dev, NV_PRMCIO_INP0) & 0x10;
97 if (sense_a != sense_b) {
99 nv_rd08(dev, NV_PRMCIO_INP0) & 0x10;
100 if (sense_b == sense_b_prime) {
101 /* ... unless two consecutive subsequent
102 * samples agree; sense_a is replaced */
104 /* force mis-match so we loop */
108 } while ((sense_a != sense_b) && ++j < MAX_HBLANK_OSC);
110 if (j == MAX_HBLANK_OSC)
111 /* with so much oscillation, default to sense:LO */
120 static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder,
121 struct drm_connector *connector)
123 struct drm_device *dev = encoder->dev;
124 uint8_t saved_seq1, saved_pi, saved_rpc1, saved_cr_mode;
125 uint8_t saved_palette0[3], saved_palette_mask;
126 uint32_t saved_rtest_ctrl, saved_rgen_ctrl;
132 * for this detection to work, there needs to be a mode set up on the
133 * CRTC. this is presumed to be the case
136 if (nv_two_heads(dev))
137 /* only implemented for head A for now */
140 saved_cr_mode = NVReadVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX);
141 NVWriteVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX, saved_cr_mode | 0x80);
143 saved_seq1 = NVReadVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX);
144 NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1 & ~0x20);
146 saved_rtest_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL);
147 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL,
148 saved_rtest_ctrl & ~NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF);
152 saved_pi = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX);
153 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX,
154 saved_pi & ~(0x80 | MASK(NV_CIO_CRE_PIXEL_FORMAT)));
155 saved_rpc1 = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX);
156 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1 & ~0xc0);
158 nv_wr08(dev, NV_PRMDIO_READ_MODE_ADDRESS, 0x0);
159 for (i = 0; i < 3; i++)
160 saved_palette0[i] = nv_rd08(dev, NV_PRMDIO_PALETTE_DATA);
161 saved_palette_mask = nv_rd08(dev, NV_PRMDIO_PIXEL_MASK);
162 nv_wr08(dev, NV_PRMDIO_PIXEL_MASK, 0);
164 saved_rgen_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL);
165 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL,
166 (saved_rgen_ctrl & ~(NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS |
167 NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_75OHM)) |
168 NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON);
170 blue = 8; /* start of test range */
175 nv_wr08(dev, NV_PRMDIO_WRITE_MODE_ADDRESS, 0);
176 nv_wr08(dev, NV_PRMDIO_PALETTE_DATA, 0);
177 nv_wr08(dev, NV_PRMDIO_PALETTE_DATA, 0);
178 /* testing blue won't find monochrome monitors. I don't care */
179 nv_wr08(dev, NV_PRMDIO_PALETTE_DATA, blue);
182 /* take sample pairs until both samples in the pair agree */
184 if (sample_load_twice(dev, sense_pair))
186 } while ((sense_pair[0] != sense_pair[1]) &&
187 ++i < MAX_SAMPLE_PAIRS);
189 if (i == MAX_SAMPLE_PAIRS)
190 /* too much oscillation defaults to LO */
193 sense = sense_pair[0];
196 * if sense goes LO before blue ramps to 0x18, monitor is not connected.
197 * ergo, if blue gets to 0x18, monitor must be connected
199 } while (++blue < 0x18 && sense);
202 nv_wr08(dev, NV_PRMDIO_PIXEL_MASK, saved_palette_mask);
203 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL, saved_rgen_ctrl);
204 nv_wr08(dev, NV_PRMDIO_WRITE_MODE_ADDRESS, 0);
205 for (i = 0; i < 3; i++)
206 nv_wr08(dev, NV_PRMDIO_PALETTE_DATA, saved_palette0[i]);
207 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL, saved_rtest_ctrl);
208 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX, saved_pi);
209 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1);
210 NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1);
211 NVWriteVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX, saved_cr_mode);
214 NV_INFO(dev, "Load detected on head A\n");
215 return connector_status_connected;
218 return connector_status_disconnected;
221 uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
223 struct drm_device *dev = encoder->dev;
224 struct drm_nouveau_private *dev_priv = dev->dev_private;
225 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
226 uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder);
227 uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput,
228 saved_rtest_ctrl, saved_gpio0, saved_gpio1, temp, routput;
231 #define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
232 if (dcb->type == DCB_OUTPUT_TV) {
233 testval = RGB_TEST_DATA(0xa0, 0xa0, 0xa0);
235 if (dev_priv->vbios.tvdactestval)
236 testval = dev_priv->vbios.tvdactestval;
238 testval = RGB_TEST_DATA(0x140, 0x140, 0x140); /* 0x94050140 */
240 if (dev_priv->vbios.dactestval)
241 testval = dev_priv->vbios.dactestval;
244 saved_rtest_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
245 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset,
246 saved_rtest_ctrl & ~NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF);
248 saved_powerctrl_2 = nv_rd32(dev, NV_PBUS_POWERCTRL_2);
250 nv_wr32(dev, NV_PBUS_POWERCTRL_2, saved_powerctrl_2 & 0xd7ffffff);
251 if (regoffset == 0x68) {
252 saved_powerctrl_4 = nv_rd32(dev, NV_PBUS_POWERCTRL_4);
253 nv_wr32(dev, NV_PBUS_POWERCTRL_4, saved_powerctrl_4 & 0xffffffcf);
256 saved_gpio1 = nouveau_gpio_func_get(dev, DCB_GPIO_TVDAC1);
257 saved_gpio0 = nouveau_gpio_func_get(dev, DCB_GPIO_TVDAC0);
259 nouveau_gpio_func_set(dev, DCB_GPIO_TVDAC1, dcb->type == DCB_OUTPUT_TV);
260 nouveau_gpio_func_set(dev, DCB_GPIO_TVDAC0, dcb->type == DCB_OUTPUT_TV);
264 saved_routput = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
265 head = (saved_routput & 0x100) >> 8;
267 /* if there's a spare crtc, using it will minimise flicker */
268 if (!(NVReadVgaCrtc(dev, head, NV_CIO_CRE_RPC1_INDEX) & 0xC0))
271 /* nv driver and nv31 use 0xfffffeee, nv34 and 6600 use 0xfffffece */
272 routput = (saved_routput & 0xfffffece) | head << 8;
274 if (dev_priv->card_type >= NV_40) {
275 if (dcb->type == DCB_OUTPUT_TV)
276 routput |= 0x1a << 16;
278 routput &= ~(0x1a << 16);
281 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, routput);
284 temp = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
285 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, temp | 1);
287 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TESTPOINT_DATA,
288 NV_PRAMDAC_TESTPOINT_DATA_NOTBLANK | testval);
289 temp = NVReadRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL);
290 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL,
291 temp | NV_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED);
294 sample = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
295 /* do it again just in case it's a residual current */
296 sample &= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
298 temp = NVReadRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL);
299 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL,
300 temp & ~NV_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED);
301 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TESTPOINT_DATA, 0);
303 /* bios does something more complex for restoring, but I think this is good enough */
304 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, saved_routput);
305 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, saved_rtest_ctrl);
306 if (regoffset == 0x68)
307 nv_wr32(dev, NV_PBUS_POWERCTRL_4, saved_powerctrl_4);
308 nv_wr32(dev, NV_PBUS_POWERCTRL_2, saved_powerctrl_2);
310 nouveau_gpio_func_set(dev, DCB_GPIO_TVDAC1, saved_gpio1);
311 nouveau_gpio_func_set(dev, DCB_GPIO_TVDAC0, saved_gpio0);
316 static enum drm_connector_status
317 nv17_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
319 struct drm_device *dev = encoder->dev;
320 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
322 if (nv04_dac_in_use(encoder))
323 return connector_status_disconnected;
325 if (nv17_dac_sample_load(encoder) &
326 NV_PRAMDAC_TEST_CONTROL_SENSEB_ALLHI) {
327 NV_INFO(dev, "Load detected on output %c\n",
329 return connector_status_connected;
331 return connector_status_disconnected;
335 static bool nv04_dac_mode_fixup(struct drm_encoder *encoder,
336 const struct drm_display_mode *mode,
337 struct drm_display_mode *adjusted_mode)
339 if (nv04_dac_in_use(encoder))
345 static void nv04_dac_prepare(struct drm_encoder *encoder)
347 struct drm_encoder_helper_funcs *helper = encoder->helper_private;
348 struct drm_device *dev = encoder->dev;
349 int head = nouveau_crtc(encoder->crtc)->index;
351 helper->dpms(encoder, DRM_MODE_DPMS_OFF);
353 nv04_dfp_disable(dev, head);
356 static void nv04_dac_mode_set(struct drm_encoder *encoder,
357 struct drm_display_mode *mode,
358 struct drm_display_mode *adjusted_mode)
360 struct drm_device *dev = encoder->dev;
361 struct drm_nouveau_private *dev_priv = dev->dev_private;
362 int head = nouveau_crtc(encoder->crtc)->index;
364 if (nv_gf4_disp_arch(dev)) {
365 struct drm_encoder *rebind;
366 uint32_t dac_offset = nv04_dac_output_offset(encoder);
369 /* bit 16-19 are bits that are set on some G70 cards,
370 * but don't seem to have much effect */
371 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + dac_offset,
372 head << 8 | NV_PRAMDAC_DACCLK_SEL_DACCLK);
373 /* force any other vga encoders to bind to the other crtc */
374 list_for_each_entry(rebind, &dev->mode_config.encoder_list, head) {
375 if (rebind == encoder
376 || nouveau_encoder(rebind)->dcb->type != DCB_OUTPUT_ANALOG)
379 dac_offset = nv04_dac_output_offset(rebind);
380 otherdac = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + dac_offset);
381 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + dac_offset,
382 (otherdac & ~0x0100) | (head ^ 1) << 8);
386 /* This could use refinement for flatpanels, but it should work this way */
387 if (dev_priv->chipset < 0x44)
388 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000);
390 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000);
393 static void nv04_dac_commit(struct drm_encoder *encoder)
395 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
396 struct drm_device *dev = encoder->dev;
397 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
398 struct drm_encoder_helper_funcs *helper = encoder->helper_private;
400 helper->dpms(encoder, DRM_MODE_DPMS_ON);
402 NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
403 drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base),
404 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
407 void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable)
409 struct drm_device *dev = encoder->dev;
410 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
412 if (nv_gf4_disp_arch(dev)) {
413 uint32_t *dac_users = &nv04_display(dev)->dac_users[ffs(dcb->or) - 1];
414 int dacclk_off = NV_PRAMDAC_DACCLK + nv04_dac_output_offset(encoder);
415 uint32_t dacclk = NVReadRAMDAC(dev, 0, dacclk_off);
418 *dac_users |= 1 << dcb->index;
419 NVWriteRAMDAC(dev, 0, dacclk_off, dacclk | NV_PRAMDAC_DACCLK_SEL_DACCLK);
422 *dac_users &= ~(1 << dcb->index);
424 NVWriteRAMDAC(dev, 0, dacclk_off,
425 dacclk & ~NV_PRAMDAC_DACCLK_SEL_DACCLK);
430 /* Check if the DAC corresponding to 'encoder' is being used by
432 bool nv04_dac_in_use(struct drm_encoder *encoder)
434 struct drm_device *dev = encoder->dev;
435 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
437 return nv_gf4_disp_arch(encoder->dev) &&
438 (nv04_display(dev)->dac_users[ffs(dcb->or) - 1] & ~(1 << dcb->index));
441 static void nv04_dac_dpms(struct drm_encoder *encoder, int mode)
443 struct drm_device *dev = encoder->dev;
444 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
446 if (nv_encoder->last_dpms == mode)
448 nv_encoder->last_dpms = mode;
450 NV_INFO(dev, "Setting dpms mode %d on vga encoder (output %d)\n",
451 mode, nv_encoder->dcb->index);
453 nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON);
456 static void nv04_dac_save(struct drm_encoder *encoder)
458 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
459 struct drm_device *dev = encoder->dev;
461 if (nv_gf4_disp_arch(dev))
462 nv_encoder->restore.output = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK +
463 nv04_dac_output_offset(encoder));
466 static void nv04_dac_restore(struct drm_encoder *encoder)
468 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
469 struct drm_device *dev = encoder->dev;
471 if (nv_gf4_disp_arch(dev))
472 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + nv04_dac_output_offset(encoder),
473 nv_encoder->restore.output);
475 nv_encoder->last_dpms = NV_DPMS_CLEARED;
478 static void nv04_dac_destroy(struct drm_encoder *encoder)
480 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
482 NV_DEBUG_KMS(encoder->dev, "\n");
484 drm_encoder_cleanup(encoder);
488 static const struct drm_encoder_helper_funcs nv04_dac_helper_funcs = {
489 .dpms = nv04_dac_dpms,
490 .save = nv04_dac_save,
491 .restore = nv04_dac_restore,
492 .mode_fixup = nv04_dac_mode_fixup,
493 .prepare = nv04_dac_prepare,
494 .commit = nv04_dac_commit,
495 .mode_set = nv04_dac_mode_set,
496 .detect = nv04_dac_detect
499 static const struct drm_encoder_helper_funcs nv17_dac_helper_funcs = {
500 .dpms = nv04_dac_dpms,
501 .save = nv04_dac_save,
502 .restore = nv04_dac_restore,
503 .mode_fixup = nv04_dac_mode_fixup,
504 .prepare = nv04_dac_prepare,
505 .commit = nv04_dac_commit,
506 .mode_set = nv04_dac_mode_set,
507 .detect = nv17_dac_detect
510 static const struct drm_encoder_funcs nv04_dac_funcs = {
511 .destroy = nv04_dac_destroy,
515 nv04_dac_create(struct drm_connector *connector, struct dcb_output *entry)
517 const struct drm_encoder_helper_funcs *helper;
518 struct nouveau_encoder *nv_encoder = NULL;
519 struct drm_device *dev = connector->dev;
520 struct drm_encoder *encoder;
522 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
526 encoder = to_drm_encoder(nv_encoder);
528 nv_encoder->dcb = entry;
529 nv_encoder->or = ffs(entry->or) - 1;
531 if (nv_gf4_disp_arch(dev))
532 helper = &nv17_dac_helper_funcs;
534 helper = &nv04_dac_helper_funcs;
536 drm_encoder_init(dev, encoder, &nv04_dac_funcs, DRM_MODE_ENCODER_DAC);
537 drm_encoder_helper_add(encoder, helper);
539 encoder->possible_crtcs = entry->heads;
540 encoder->possible_clones = 0;
542 drm_mode_connector_attach_encoder(connector, encoder);