drivers/gpu/drm/nouveau/nv04_dfp.c

   1 /*
   2  * Copyright 2003 NVIDIA, Corporation
   3  * Copyright 2006 Dave Airlie
   4  * Copyright 2007 Maarten Maathuis
   5  * Copyright 2007-2009 Stuart Bennett
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  23  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm_crtc_helper.h"
  29
  30 #include "nouveau_drv.h"
  31 #include "nouveau_encoder.h"
  32 #include "nouveau_connector.h"
  33 #include "nouveau_crtc.h"
  34 #include "nouveau_hw.h"
  35 #include "nvreg.h"
  36
  37 #include "i2c/sil164.h"
  38
  39 #define FP_TG_CONTROL_ON  (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |        \
  40                            NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS |         \
  41                            NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS)
  42 #define FP_TG_CONTROL_OFF (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE |    \
  43                            NV_PRAMDAC_FP_TG_CONTROL_HSYNC_DISABLE |     \
  44                            NV_PRAMDAC_FP_TG_CONTROL_VSYNC_DISABLE)
  45
  46 static inline bool is_fpc_off(uint32_t fpc)
  47 {
  48         return ((fpc & (FP_TG_CONTROL_ON | FP_TG_CONTROL_OFF)) ==
  49                         FP_TG_CONTROL_OFF);
  50 }
  51
  52 int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent)
  53 {
  54         /* special case of nv_read_tmds to find crtc associated with an output.
  55          * this does not give a correct answer for off-chip dvi, but there's no
  56          * use for such an answer anyway
  57          */
  58         int ramdac = (dcbent->or & OUTPUT_C) >> 2;
  59
  60         NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL,
  61         NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE | 0x4);
  62         return ((NVReadRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_DATA) & 0x8) >> 3) ^ ramdac;
  63 }
  64
  65 void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
  66                         int head, bool dl)
  67 {
  68         /* The BIOS scripts don't do this for us, sadly
  69          * Luckily we do know the values ;-)
  70          *
  71          * head < 0 indicates we wish to force a setting with the overrideval
  72          * (for VT restore etc.)
  73          */
  74
  75         int ramdac = (dcbent->or & OUTPUT_C) >> 2;
  76         uint8_t tmds04 = 0x80;
  77
  78         if (head != ramdac)
  79                 tmds04 = 0x88;
  80
  81         if (dcbent->type == OUTPUT_LVDS)
  82                 tmds04 |= 0x01;
  83
  84         nv_write_tmds(dev, dcbent->or, 0, 0x04, tmds04);
  85
  86         if (dl) /* dual link */
  87                 nv_write_tmds(dev, dcbent->or, 1, 0x04, tmds04 ^ 0x08);
  88 }
  89
  90 void nv04_dfp_disable(struct drm_device *dev, int head)
  91 {
  92         struct drm_nouveau_private *dev_priv = dev->dev_private;
  93         struct nv04_crtc_reg *crtcstate = dev_priv->mode_reg.crtc_reg;
  94
  95         if (NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL) &
  96             FP_TG_CONTROL_ON) {
  97                 /* digital remnants must be cleaned before new crtc
  98                  * values programmed.  delay is time for the vga stuff
  99                  * to realise it's in control again
 100                  */
 101                 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,
 102                               FP_TG_CONTROL_OFF);
 103                 msleep(50);
 104         }
 105         /* don't inadvertently turn it on when state written later */
 106         crtcstate[head].fp_control = FP_TG_CONTROL_OFF;
 107 }
 108
 109 void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode)
 110 {
 111         struct drm_device *dev = encoder->dev;
 112         struct drm_nouveau_private *dev_priv = dev->dev_private;
 113         struct drm_crtc *crtc;
 114         struct nouveau_crtc *nv_crtc;
 115         uint32_t *fpc;
 116
 117         if (mode == DRM_MODE_DPMS_ON) {
 118                 nv_crtc = nouveau_crtc(encoder->crtc);
 119                 fpc = &dev_priv->mode_reg.crtc_reg[nv_crtc->index].fp_control;
 120
 121                 if (is_fpc_off(*fpc)) {
 122                         /* using saved value is ok, as (is_digital && dpms_on &&
 123                          * fp_control==OFF) is (at present) *only* true when
 124                          * fpc's most recent change was by below "off" code
 125                          */
 126                         *fpc = nv_crtc->dpms_saved_fp_control;
 127                 }
 128
 129                 nv_crtc->fp_users |= 1 << nouveau_encoder(encoder)->dcb->index;
 130                 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_FP_TG_CONTROL, *fpc);
 131         } else {
 132                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 133                         nv_crtc = nouveau_crtc(crtc);
 134                         fpc = &dev_priv->mode_reg.crtc_reg[nv_crtc->index].fp_control;
 135
 136                         nv_crtc->fp_users &= ~(1 << nouveau_encoder(encoder)->dcb->index);
 137                         if (!is_fpc_off(*fpc) && !nv_crtc->fp_users) {
 138                                 nv_crtc->dpms_saved_fp_control = *fpc;
 139                                 /* cut the FP output */
 140                                 *fpc &= ~FP_TG_CONTROL_ON;
 141                                 *fpc |= FP_TG_CONTROL_OFF;
 142                                 NVWriteRAMDAC(dev, nv_crtc->index,
 143                                               NV_PRAMDAC_FP_TG_CONTROL, *fpc);
 144                         }
 145                 }
 146         }
 147 }
 148
 149 static bool nv04_dfp_mode_fixup(struct drm_encoder *encoder,
 150                                 struct drm_display_mode *mode,
 151                                 struct drm_display_mode *adjusted_mode)
 152 {
 153         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 154         struct nouveau_connector *nv_connector = nouveau_encoder_connector_get(nv_encoder);
 155
 156         /* For internal panels and gpu scaling on DVI we need the native mode */
 157         if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
 158                 if (!nv_connector->native_mode)
 159                         return false;
 160                 nv_encoder->mode = *nv_connector->native_mode;
 161                 adjusted_mode->clock = nv_connector->native_mode->clock;
 162         } else {
 163                 nv_encoder->mode = *adjusted_mode;
 164         }
 165
 166         return true;
 167 }
 168
 169 static void nv04_dfp_prepare_sel_clk(struct drm_device *dev,
 170                                      struct nouveau_encoder *nv_encoder, int head)
 171 {
 172         struct drm_nouveau_private *dev_priv = dev->dev_private;
 173         struct nv04_mode_state *state = &dev_priv->mode_reg;
 174         uint32_t bits1618 = nv_encoder->dcb->or & OUTPUT_A ? 0x10000 : 0x40000;
 175
 176         if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP)
 177                 return;
 178
 179         /* SEL_CLK is only used on the primary ramdac
 180          * It toggles spread spectrum PLL output and sets the bindings of PLLs
 181          * to heads on digital outputs
 182          */
 183         if (head)
 184                 state->sel_clk |= bits1618;
 185         else
 186                 state->sel_clk &= ~bits1618;
 187
 188         /* nv30:
 189          *      bit 0           NVClk spread spectrum on/off
 190          *      bit 2           MemClk spread spectrum on/off
 191          *      bit 4           PixClk1 spread spectrum on/off toggle
 192          *      bit 6           PixClk2 spread spectrum on/off toggle
 193          *
 194          * nv40 (observations from bios behaviour and mmio traces):
 195          *      bits 4&6        as for nv30
 196          *      bits 5&7        head dependent as for bits 4&6, but do not appear with 4&6;
 197          *                      maybe a different spread mode
 198          *      bits 8&10       seen on dual-link dvi outputs, purpose unknown (set by POST scripts)
 199          *      The logic behind turning spread spectrum on/off in the first place,
 200          *      and which bit-pair to use, is unclear on nv40 (for earlier cards, the fp table
 201          *      entry has the necessary info)
 202          */
 203         if (nv_encoder->dcb->type == OUTPUT_LVDS && dev_priv->saved_reg.sel_clk & 0xf0) {
 204                 int shift = (dev_priv->saved_reg.sel_clk & 0x50) ? 0 : 1;
 205
 206                 state->sel_clk &= ~0xf0;
 207                 state->sel_clk |= (head ? 0x40 : 0x10) << shift;
 208         }
 209 }
 210
 211 static void nv04_dfp_prepare(struct drm_encoder *encoder)
 212 {
 213         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 214         struct drm_encoder_helper_funcs *helper = encoder->helper_private;
 215         struct drm_device *dev = encoder->dev;
 216         struct drm_nouveau_private *dev_priv = dev->dev_private;
 217         int head = nouveau_crtc(encoder->crtc)->index;
 218         struct nv04_crtc_reg *crtcstate = dev_priv->mode_reg.crtc_reg;
 219         uint8_t *cr_lcd = &crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX];
 220         uint8_t *cr_lcd_oth = &crtcstate[head ^ 1].CRTC[NV_CIO_CRE_LCD__INDEX];
 221
 222         helper->dpms(encoder, DRM_MODE_DPMS_OFF);
 223
 224         nv04_dfp_prepare_sel_clk(dev, nv_encoder, head);
 225
 226         /* Some NV4x have unknown values (0x3f, 0x50, 0x54, 0x6b, 0x79, 0x7f)
 227          * at LCD__INDEX which we don't alter
 228          */
 229         if (!(*cr_lcd & 0x44)) {
 230                 *cr_lcd = 0x3;
 231
 232                 if (nv_two_heads(dev)) {
 233                         if (nv_encoder->dcb->location == DCB_LOC_ON_CHIP)
 234                                 *cr_lcd |= head ? 0x0 : 0x8;
 235                         else {
 236                                 *cr_lcd |= (nv_encoder->dcb->or << 4) & 0x30;
 237                                 if (nv_encoder->dcb->type == OUTPUT_LVDS)
 238                                         *cr_lcd |= 0x30;
 239                                 if ((*cr_lcd & 0x30) == (*cr_lcd_oth & 0x30)) {
 240                                         /* avoid being connected to both crtcs */
 241                                         *cr_lcd_oth &= ~0x30;
 242                                         NVWriteVgaCrtc(dev, head ^ 1,
 243                                                        NV_CIO_CRE_LCD__INDEX,
 244                                                        *cr_lcd_oth);
 245                                 }
 246                         }
 247                 }
 248         }
 249 }
 250
 251
 252 static void nv04_dfp_mode_set(struct drm_encoder *encoder,
 253                               struct drm_display_mode *mode,
 254                               struct drm_display_mode *adjusted_mode)
 255 {
 256         struct drm_device *dev = encoder->dev;
 257         struct drm_nouveau_private *dev_priv = dev->dev_private;
 258         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 259         struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
 260         struct nv04_crtc_reg *savep = &dev_priv->saved_reg.crtc_reg[nv_crtc->index];
 261         struct nouveau_connector *nv_connector = nouveau_crtc_connector_get(nv_crtc);
 262         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 263         struct drm_display_mode *output_mode = &nv_encoder->mode;
 264         uint32_t mode_ratio, panel_ratio;
 265
 266         NV_DEBUG_KMS(dev, "Output mode on CRTC %d:\n", nv_crtc->index);
 267         drm_mode_debug_printmodeline(output_mode);
 268
 269         /* Initialize the FP registers in this CRTC. */
 270         regp->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
 271         regp->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
 272         if (!nv_gf4_disp_arch(dev) ||
 273             (output_mode->hsync_start - output_mode->hdisplay) >=
 274                                         dev_priv->vbios.digital_min_front_porch)
 275                 regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay;
 276         else
 277                 regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - dev_priv->vbios.digital_min_front_porch - 1;
 278         regp->fp_horiz_regs[FP_SYNC_START] = output_mode->hsync_start - 1;
 279         regp->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
 280         regp->fp_horiz_regs[FP_VALID_START] = output_mode->hskew;
 281         regp->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - 1;
 282
 283         regp->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
 284         regp->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
 285         regp->fp_vert_regs[FP_CRTC] = output_mode->vtotal - 5 - 1;
 286         regp->fp_vert_regs[FP_SYNC_START] = output_mode->vsync_start - 1;
 287         regp->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
 288         regp->fp_vert_regs[FP_VALID_START] = 0;
 289         regp->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - 1;
 290
 291         /* bit26: a bit seen on some g7x, no as yet discernable purpose */
 292         regp->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
 293                            (savep->fp_control & (1 << 26 | NV_PRAMDAC_FP_TG_CONTROL_READ_PROG));
 294         /* Deal with vsync/hsync polarity */
 295         /* LVDS screens do set this, but modes with +ve syncs are very rare */
 296         if (output_mode->flags & DRM_MODE_FLAG_PVSYNC)
 297                 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;
 298         if (output_mode->flags & DRM_MODE_FLAG_PHSYNC)
 299                 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;
 300         /* panel scaling first, as native would get set otherwise */
 301         if (nv_connector->scaling_mode == DRM_MODE_SCALE_NONE ||
 302             nv_connector->scaling_mode == DRM_MODE_SCALE_CENTER)        /* panel handles it */
 303                 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_CENTER;
 304         else if (adjusted_mode->hdisplay == output_mode->hdisplay &&
 305                  adjusted_mode->vdisplay == output_mode->vdisplay) /* native mode */
 306                 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE;
 307         else /* gpu needs to scale */
 308                 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE;
 309         if (nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
 310                 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
 311         if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP &&
 312             output_mode->clock > 165000)
 313                 regp->fp_control |= (2 << 24);
 314         if (nv_encoder->dcb->type == OUTPUT_LVDS) {
 315                 bool duallink, dummy;
 316
 317                 nouveau_bios_parse_lvds_table(dev, nv_connector->native_mode->
 318                                               clock, &duallink, &dummy);
 319                 if (duallink)
 320                         regp->fp_control |= (8 << 28);
 321         } else
 322         if (output_mode->clock > 165000)
 323                 regp->fp_control |= (8 << 28);
 324
 325         regp->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND |
 326                            NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND |
 327                            NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR |
 328                            NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR |
 329                            NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED |
 330                            NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE |
 331                            NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE;
 332
 333         /* We want automatic scaling */
 334         regp->fp_debug_1 = 0;
 335         /* This can override HTOTAL and VTOTAL */
 336         regp->fp_debug_2 = 0;
 337
 338         /* Use 20.12 fixed point format to avoid floats */
 339         mode_ratio = (1 << 12) * adjusted_mode->hdisplay / adjusted_mode->vdisplay;
 340         panel_ratio = (1 << 12) * output_mode->hdisplay / output_mode->vdisplay;
 341         /* if ratios are equal, SCALE_ASPECT will automatically (and correctly)
 342          * get treated the same as SCALE_FULLSCREEN */
 343         if (nv_connector->scaling_mode == DRM_MODE_SCALE_ASPECT &&
 344             mode_ratio != panel_ratio) {
 345                 uint32_t diff, scale;
 346                 bool divide_by_2 = nv_gf4_disp_arch(dev);
 347
 348                 if (mode_ratio < panel_ratio) {
 349                         /* vertical needs to expand to glass size (automatic)
 350                          * horizontal needs to be scaled at vertical scale factor
 351                          * to maintain aspect */
 352
 353                         scale = (1 << 12) * adjusted_mode->vdisplay / output_mode->vdisplay;
 354                         regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE_ENABLE |
 355                                            XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_XSCALE_VALUE);
 356
 357                         /* restrict area of screen used, horizontally */
 358                         diff = output_mode->hdisplay -
 359                                output_mode->vdisplay * mode_ratio / (1 << 12);
 360                         regp->fp_horiz_regs[FP_VALID_START] += diff / 2;
 361                         regp->fp_horiz_regs[FP_VALID_END] -= diff / 2;
 362                 }
 363
 364                 if (mode_ratio > panel_ratio) {
 365                         /* horizontal needs to expand to glass size (automatic)
 366                          * vertical needs to be scaled at horizontal scale factor
 367                          * to maintain aspect */
 368
 369                         scale = (1 << 12) * adjusted_mode->hdisplay / output_mode->hdisplay;
 370                         regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE_ENABLE |
 371                                            XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_YSCALE_VALUE);
 372
 373                         /* restrict area of screen used, vertically */
 374                         diff = output_mode->vdisplay -
 375                                (1 << 12) * output_mode->hdisplay / mode_ratio;
 376                         regp->fp_vert_regs[FP_VALID_START] += diff / 2;
 377                         regp->fp_vert_regs[FP_VALID_END] -= diff / 2;
 378                 }
 379         }
 380
 381         /* Output property. */
 382         if (nv_connector->use_dithering) {
 383                 if (dev_priv->chipset == 0x11)
 384                         regp->dither = savep->dither | 0x00010000;
 385                 else {
 386                         int i;
 387                         regp->dither = savep->dither | 0x00000001;
 388                         for (i = 0; i < 3; i++) {
 389                                 regp->dither_regs[i] = 0xe4e4e4e4;
 390                                 regp->dither_regs[i + 3] = 0x44444444;
 391                         }
 392                 }
 393         } else {
 394                 if (dev_priv->chipset != 0x11) {
 395                         /* reset them */
 396                         int i;
 397                         for (i = 0; i < 3; i++) {
 398                                 regp->dither_regs[i] = savep->dither_regs[i];
 399                                 regp->dither_regs[i + 3] = savep->dither_regs[i + 3];
 400                         }
 401                 }
 402                 regp->dither = savep->dither;
 403         }
 404
 405         regp->fp_margin_color = 0;
 406 }
 407
 408 static void nv04_dfp_commit(struct drm_encoder *encoder)
 409 {
 410         struct drm_device *dev = encoder->dev;
 411         struct drm_nouveau_private *dev_priv = dev->dev_private;
 412         struct drm_encoder_helper_funcs *helper = encoder->helper_private;
 413         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 414         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 415         struct dcb_entry *dcbe = nv_encoder->dcb;
 416         int head = nouveau_crtc(encoder->crtc)->index;
 417
 418         if (dcbe->type == OUTPUT_TMDS)
 419                 run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock);
 420         else if (dcbe->type == OUTPUT_LVDS)
 421                 call_lvds_script(dev, dcbe, head, LVDS_RESET, nv_encoder->mode.clock);
 422
 423         /* update fp_control state for any changes made by scripts,
 424          * so correct value is written at DPMS on */
 425         dev_priv->mode_reg.crtc_reg[head].fp_control =
 426                 NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
 427
 428         /* This could use refinement for flatpanels, but it should work this way */
 429         if (dev_priv->chipset < 0x44)
 430                 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000);
 431         else
 432                 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000);
 433
 434         /* Init external transmitters */
 435         if (get_slave_funcs(encoder))
 436                 get_slave_funcs(encoder)->mode_set(encoder, &nv_encoder->mode,
 437                                                    &nv_encoder->mode);
 438
 439         helper->dpms(encoder, DRM_MODE_DPMS_ON);
 440
 441         NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
 442                 drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base),
 443                 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
 444 }
 445
 446 static inline bool is_powersaving_dpms(int mode)
 447 {
 448         return (mode != DRM_MODE_DPMS_ON);
 449 }
 450
 451 static void nv04_lvds_dpms(struct drm_encoder *encoder, int mode)
 452 {
 453         struct drm_device *dev = encoder->dev;
 454         struct drm_crtc *crtc = encoder->crtc;
 455         struct drm_nouveau_private *dev_priv = dev->dev_private;
 456         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 457         bool was_powersaving = is_powersaving_dpms(nv_encoder->last_dpms);
 458
 459         if (nv_encoder->last_dpms == mode)
 460                 return;
 461         nv_encoder->last_dpms = mode;
 462
 463         NV_INFO(dev, "Setting dpms mode %d on lvds encoder (output %d)\n",
 464                      mode, nv_encoder->dcb->index);
 465
 466         if (was_powersaving && is_powersaving_dpms(mode))
 467                 return;
 468
 469         if (nv_encoder->dcb->lvdsconf.use_power_scripts) {
 470                 struct nouveau_connector *nv_connector = nouveau_encoder_connector_get(nv_encoder);
 471
 472                 /* when removing an output, crtc may not be set, but PANEL_OFF
 473                  * must still be run
 474                  */
 475                 int head = crtc ? nouveau_crtc(crtc)->index :
 476                            nv04_dfp_get_bound_head(dev, nv_encoder->dcb);
 477
 478                 if (mode == DRM_MODE_DPMS_ON) {
 479                         if (!nv_connector->native_mode) {
 480                                 NV_ERROR(dev, "Not turning on LVDS without native mode\n");
 481                                 return;
 482                         }
 483                         call_lvds_script(dev, nv_encoder->dcb, head,
 484                                          LVDS_PANEL_ON, nv_connector->native_mode->clock);
 485                 } else
 486                         /* pxclk of 0 is fine for PANEL_OFF, and for a
 487                          * disconnected LVDS encoder there is no native_mode
 488                          */
 489                         call_lvds_script(dev, nv_encoder->dcb, head,
 490                                          LVDS_PANEL_OFF, 0);
 491         }
 492
 493         nv04_dfp_update_fp_control(encoder, mode);
 494
 495         if (mode == DRM_MODE_DPMS_ON)
 496                 nv04_dfp_prepare_sel_clk(dev, nv_encoder, nouveau_crtc(crtc)->index);
 497         else {
 498                 dev_priv->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
 499                 dev_priv->mode_reg.sel_clk &= ~0xf0;
 500         }
 501         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, dev_priv->mode_reg.sel_clk);
 502 }
 503
 504 static void nv04_tmds_dpms(struct drm_encoder *encoder, int mode)
 505 {
 506         struct drm_device *dev = encoder->dev;
 507         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 508
 509         if (nv_encoder->last_dpms == mode)
 510                 return;
 511         nv_encoder->last_dpms = mode;
 512
 513         NV_INFO(dev, "Setting dpms mode %d on tmds encoder (output %d)\n",
 514                      mode, nv_encoder->dcb->index);
 515
 516         nv04_dfp_update_fp_control(encoder, mode);
 517 }
 518
 519 static void nv04_dfp_save(struct drm_encoder *encoder)
 520 {
 521         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 522         struct drm_device *dev = encoder->dev;
 523
 524         if (nv_two_heads(dev))
 525                 nv_encoder->restore.head =
 526                         nv04_dfp_get_bound_head(dev, nv_encoder->dcb);
 527 }
 528
 529 static void nv04_dfp_restore(struct drm_encoder *encoder)
 530 {
 531         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 532         struct drm_device *dev = encoder->dev;
 533         struct drm_nouveau_private *dev_priv = dev->dev_private;
 534         int head = nv_encoder->restore.head;
 535
 536         if (nv_encoder->dcb->type == OUTPUT_LVDS) {
 537                 struct drm_display_mode *native_mode = nouveau_encoder_connector_get(nv_encoder)->native_mode;
 538                 if (native_mode)
 539                         call_lvds_script(dev, nv_encoder->dcb, head, LVDS_PANEL_ON,
 540                                          native_mode->clock);
 541                 else
 542                         NV_ERROR(dev, "Not restoring LVDS without native mode\n");
 543
 544         } else if (nv_encoder->dcb->type == OUTPUT_TMDS) {
 545                 int clock = nouveau_hw_pllvals_to_clk
 546                                         (&dev_priv->saved_reg.crtc_reg[head].pllvals);
 547
 548                 run_tmds_table(dev, nv_encoder->dcb, head, clock);
 549         }
 550
 551         nv_encoder->last_dpms = NV_DPMS_CLEARED;
 552 }
 553
 554 static void nv04_dfp_destroy(struct drm_encoder *encoder)
 555 {
 556         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 557
 558         NV_DEBUG_KMS(encoder->dev, "\n");
 559
 560         if (get_slave_funcs(encoder))
 561                 get_slave_funcs(encoder)->destroy(encoder);
 562
 563         drm_encoder_cleanup(encoder);
 564         kfree(nv_encoder);
 565 }
 566
 567 static void nv04_tmds_slave_init(struct drm_encoder *encoder)
 568 {
 569         struct drm_device *dev = encoder->dev;
 570         struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
 571         struct nouveau_i2c_chan *i2c = nouveau_i2c_find(dev, 2);
 572         struct i2c_board_info info[] = {
 573                 {
 574                         .type = "sil164",
 575                         .addr = (dcb->tmdsconf.slave_addr == 0x7 ? 0x3a : 0x38),
 576                         .platform_data = &(struct sil164_encoder_params) {
 577                                 SIL164_INPUT_EDGE_RISING
 578                         }
 579                 },
 580                 { }
 581         };
 582         int type;
 583
 584         if (!nv_gf4_disp_arch(dev) || !i2c)
 585                 return;
 586
 587         type = nouveau_i2c_identify(dev, "TMDS transmitter", info, 2);
 588         if (type < 0)
 589                 return;
 590
 591         drm_i2c_encoder_init(dev, to_encoder_slave(encoder),
 592                              &i2c->adapter, &info[type]);
 593 }
 594
 595 static const struct drm_encoder_helper_funcs nv04_lvds_helper_funcs = {
 596         .dpms = nv04_lvds_dpms,
 597         .save = nv04_dfp_save,
 598         .restore = nv04_dfp_restore,
 599         .mode_fixup = nv04_dfp_mode_fixup,
 600         .prepare = nv04_dfp_prepare,
 601         .commit = nv04_dfp_commit,
 602         .mode_set = nv04_dfp_mode_set,
 603         .detect = NULL,
 604 };
 605
 606 static const struct drm_encoder_helper_funcs nv04_tmds_helper_funcs = {
 607         .dpms = nv04_tmds_dpms,
 608         .save = nv04_dfp_save,
 609         .restore = nv04_dfp_restore,
 610         .mode_fixup = nv04_dfp_mode_fixup,
 611         .prepare = nv04_dfp_prepare,
 612         .commit = nv04_dfp_commit,
 613         .mode_set = nv04_dfp_mode_set,
 614         .detect = NULL,
 615 };
 616
 617 static const struct drm_encoder_funcs nv04_dfp_funcs = {
 618         .destroy = nv04_dfp_destroy,
 619 };
 620
 621 int
 622 nv04_dfp_create(struct drm_connector *connector, struct dcb_entry *entry)
 623 {
 624         const struct drm_encoder_helper_funcs *helper;
 625         struct nouveau_encoder *nv_encoder = NULL;
 626         struct drm_encoder *encoder;
 627         int type;
 628
 629         switch (entry->type) {
 630         case OUTPUT_TMDS:
 631                 type = DRM_MODE_ENCODER_TMDS;
 632                 helper = &nv04_tmds_helper_funcs;
 633                 break;
 634         case OUTPUT_LVDS:
 635                 type = DRM_MODE_ENCODER_LVDS;
 636                 helper = &nv04_lvds_helper_funcs;
 637                 break;
 638         default:
 639                 return -EINVAL;
 640         }
 641
 642         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 643         if (!nv_encoder)
 644                 return -ENOMEM;
 645
 646         encoder = to_drm_encoder(nv_encoder);
 647
 648         nv_encoder->dcb = entry;
 649         nv_encoder->or = ffs(entry->or) - 1;
 650
 651         drm_encoder_init(connector->dev, encoder, &nv04_dfp_funcs, type);
 652         drm_encoder_helper_add(encoder, helper);
 653
 654         encoder->possible_crtcs = entry->heads;
 655         encoder->possible_clones = 0;
 656
 657         if (entry->type == OUTPUT_TMDS &&
 658             entry->location != DCB_LOC_ON_CHIP)
 659                 nv04_tmds_slave_init(encoder);
 660
 661         drm_mode_connector_attach_encoder(connector, encoder);
 662         return 0;
 663 }