drivers/gpu/drm/nouveau/nv04_dfp.c

   1 /*
   2  * Copyright 2003 NVIDIA, Corporation
   3  * Copyright 2006 Dave Airlie
   4  * Copyright 2007 Maarten Maathuis
   5  * Copyright 2007-2009 Stuart Bennett
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  23  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm_crtc_helper.h"
  29
  30 #include "nouveau_drv.h"
  31 #include "nouveau_encoder.h"
  32 #include "nouveau_connector.h"
  33 #include "nouveau_crtc.h"
  34 #include "nouveau_hw.h"
  35 #include "nvreg.h"
  36
  37 #include "i2c/sil164.h"
  38
  39 #define FP_TG_CONTROL_ON  (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |        \
  40                            NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS |         \
  41                            NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS)
  42 #define FP_TG_CONTROL_OFF (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE |    \
  43                            NV_PRAMDAC_FP_TG_CONTROL_HSYNC_DISABLE |     \
  44                            NV_PRAMDAC_FP_TG_CONTROL_VSYNC_DISABLE)
  45
  46 static inline bool is_fpc_off(uint32_t fpc)
  47 {
  48         return ((fpc & (FP_TG_CONTROL_ON | FP_TG_CONTROL_OFF)) ==
  49                         FP_TG_CONTROL_OFF);
  50 }
  51
  52 int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_output *dcbent)
  53 {
  54         /* special case of nv_read_tmds to find crtc associated with an output.
  55          * this does not give a correct answer for off-chip dvi, but there's no
  56          * use for such an answer anyway
  57          */
  58         int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2;
  59
  60         NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL,
  61         NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE | 0x4);
  62         return ((NVReadRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_DATA) & 0x8) >> 3) ^ ramdac;
  63 }
  64
  65 void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_output *dcbent,
  66                         int head, bool dl)
  67 {
  68         /* The BIOS scripts don't do this for us, sadly
  69          * Luckily we do know the values ;-)
  70          *
  71          * head < 0 indicates we wish to force a setting with the overrideval
  72          * (for VT restore etc.)
  73          */
  74
  75         int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2;
  76         uint8_t tmds04 = 0x80;
  77
  78         if (head != ramdac)
  79                 tmds04 = 0x88;
  80
  81         if (dcbent->type == DCB_OUTPUT_LVDS)
  82                 tmds04 |= 0x01;
  83
  84         nv_write_tmds(dev, dcbent->or, 0, 0x04, tmds04);
  85
  86         if (dl) /* dual link */
  87                 nv_write_tmds(dev, dcbent->or, 1, 0x04, tmds04 ^ 0x08);
  88 }
  89
  90 void nv04_dfp_disable(struct drm_device *dev, int head)
  91 {
  92         struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
  93
  94         if (NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL) &
  95             FP_TG_CONTROL_ON) {
  96                 /* digital remnants must be cleaned before new crtc
  97                  * values programmed.  delay is time for the vga stuff
  98                  * to realise it's in control again
  99                  */
 100                 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,
 101                               FP_TG_CONTROL_OFF);
 102                 msleep(50);
 103         }
 104         /* don't inadvertently turn it on when state written later */
 105         crtcstate[head].fp_control = FP_TG_CONTROL_OFF;
 106         crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX] &=
 107                 ~NV_CIO_CRE_LCD_ROUTE_MASK;
 108 }
 109
 110 void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode)
 111 {
 112         struct drm_device *dev = encoder->dev;
 113         struct drm_crtc *crtc;
 114         struct nouveau_crtc *nv_crtc;
 115         uint32_t *fpc;
 116
 117         if (mode == DRM_MODE_DPMS_ON) {
 118                 nv_crtc = nouveau_crtc(encoder->crtc);
 119                 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
 120
 121                 if (is_fpc_off(*fpc)) {
 122                         /* using saved value is ok, as (is_digital && dpms_on &&
 123                          * fp_control==OFF) is (at present) *only* true when
 124                          * fpc's most recent change was by below "off" code
 125                          */
 126                         *fpc = nv_crtc->dpms_saved_fp_control;
 127                 }
 128
 129                 nv_crtc->fp_users |= 1 << nouveau_encoder(encoder)->dcb->index;
 130                 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_FP_TG_CONTROL, *fpc);
 131         } else {
 132                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 133                         nv_crtc = nouveau_crtc(crtc);
 134                         fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
 135
 136                         nv_crtc->fp_users &= ~(1 << nouveau_encoder(encoder)->dcb->index);
 137                         if (!is_fpc_off(*fpc) && !nv_crtc->fp_users) {
 138                                 nv_crtc->dpms_saved_fp_control = *fpc;
 139                                 /* cut the FP output */
 140                                 *fpc &= ~FP_TG_CONTROL_ON;
 141                                 *fpc |= FP_TG_CONTROL_OFF;
 142                                 NVWriteRAMDAC(dev, nv_crtc->index,
 143                                               NV_PRAMDAC_FP_TG_CONTROL, *fpc);
 144                         }
 145                 }
 146         }
 147 }
 148
 149 static struct drm_encoder *get_tmds_slave(struct drm_encoder *encoder)
 150 {
 151         struct drm_device *dev = encoder->dev;
 152         struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
 153         struct drm_encoder *slave;
 154
 155         if (dcb->type != DCB_OUTPUT_TMDS || dcb->location == DCB_LOC_ON_CHIP)
 156                 return NULL;
 157
 158         /* Some BIOSes (e.g. the one in a Quadro FX1000) report several
 159          * TMDS transmitters at the same I2C address, in the same I2C
 160          * bus. This can still work because in that case one of them is
 161          * always hard-wired to a reasonable configuration using straps,
 162          * and the other one needs to be programmed.
 163          *
 164          * I don't think there's a way to know which is which, even the
 165          * blob programs the one exposed via I2C for *both* heads, so
 166          * let's do the same.
 167          */
 168         list_for_each_entry(slave, &dev->mode_config.encoder_list, head) {
 169                 struct dcb_output *slave_dcb = nouveau_encoder(slave)->dcb;
 170
 171                 if (slave_dcb->type == DCB_OUTPUT_TMDS && get_slave_funcs(slave) &&
 172                     slave_dcb->tmdsconf.slave_addr == dcb->tmdsconf.slave_addr)
 173                         return slave;
 174         }
 175
 176         return NULL;
 177 }
 178
 179 static bool nv04_dfp_mode_fixup(struct drm_encoder *encoder,
 180                                 const struct drm_display_mode *mode,
 181                                 struct drm_display_mode *adjusted_mode)
 182 {
 183         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 184         struct nouveau_connector *nv_connector = nouveau_encoder_connector_get(nv_encoder);
 185
 186         if (!nv_connector->native_mode ||
 187             nv_connector->scaling_mode == DRM_MODE_SCALE_NONE ||
 188             mode->hdisplay > nv_connector->native_mode->hdisplay ||
 189             mode->vdisplay > nv_connector->native_mode->vdisplay) {
 190                 nv_encoder->mode = *adjusted_mode;
 191
 192         } else {
 193                 nv_encoder->mode = *nv_connector->native_mode;
 194                 adjusted_mode->clock = nv_connector->native_mode->clock;
 195         }
 196
 197         return true;
 198 }
 199
 200 static void nv04_dfp_prepare_sel_clk(struct drm_device *dev,
 201                                      struct nouveau_encoder *nv_encoder, int head)
 202 {
 203         struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
 204         uint32_t bits1618 = nv_encoder->dcb->or & DCB_OUTPUT_A ? 0x10000 : 0x40000;
 205
 206         if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP)
 207                 return;
 208
 209         /* SEL_CLK is only used on the primary ramdac
 210          * It toggles spread spectrum PLL output and sets the bindings of PLLs
 211          * to heads on digital outputs
 212          */
 213         if (head)
 214                 state->sel_clk |= bits1618;
 215         else
 216                 state->sel_clk &= ~bits1618;
 217
 218         /* nv30:
 219          *      bit 0           NVClk spread spectrum on/off
 220          *      bit 2           MemClk spread spectrum on/off
 221          *      bit 4           PixClk1 spread spectrum on/off toggle
 222          *      bit 6           PixClk2 spread spectrum on/off toggle
 223          *
 224          * nv40 (observations from bios behaviour and mmio traces):
 225          *      bits 4&6        as for nv30
 226          *      bits 5&7        head dependent as for bits 4&6, but do not appear with 4&6;
 227          *                      maybe a different spread mode
 228          *      bits 8&10       seen on dual-link dvi outputs, purpose unknown (set by POST scripts)
 229          *      The logic behind turning spread spectrum on/off in the first place,
 230          *      and which bit-pair to use, is unclear on nv40 (for earlier cards, the fp table
 231          *      entry has the necessary info)
 232          */
 233         if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS && nv04_display(dev)->saved_reg.sel_clk & 0xf0) {
 234                 int shift = (nv04_display(dev)->saved_reg.sel_clk & 0x50) ? 0 : 1;
 235
 236                 state->sel_clk &= ~0xf0;
 237                 state->sel_clk |= (head ? 0x40 : 0x10) << shift;
 238         }
 239 }
 240
 241 static void nv04_dfp_prepare(struct drm_encoder *encoder)
 242 {
 243         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 244         struct drm_encoder_helper_funcs *helper = encoder->helper_private;
 245         struct drm_device *dev = encoder->dev;
 246         int head = nouveau_crtc(encoder->crtc)->index;
 247         struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
 248         uint8_t *cr_lcd = &crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX];
 249         uint8_t *cr_lcd_oth = &crtcstate[head ^ 1].CRTC[NV_CIO_CRE_LCD__INDEX];
 250
 251         helper->dpms(encoder, DRM_MODE_DPMS_OFF);
 252
 253         nv04_dfp_prepare_sel_clk(dev, nv_encoder, head);
 254
 255         *cr_lcd = (*cr_lcd & ~NV_CIO_CRE_LCD_ROUTE_MASK) | 0x3;
 256
 257         if (nv_two_heads(dev)) {
 258                 if (nv_encoder->dcb->location == DCB_LOC_ON_CHIP)
 259                         *cr_lcd |= head ? 0x0 : 0x8;
 260                 else {
 261                         *cr_lcd |= (nv_encoder->dcb->or << 4) & 0x30;
 262                         if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS)
 263                                 *cr_lcd |= 0x30;
 264                         if ((*cr_lcd & 0x30) == (*cr_lcd_oth & 0x30)) {
 265                                 /* avoid being connected to both crtcs */
 266                                 *cr_lcd_oth &= ~0x30;
 267                                 NVWriteVgaCrtc(dev, head ^ 1,
 268                                                NV_CIO_CRE_LCD__INDEX,
 269                                                *cr_lcd_oth);
 270                         }
 271                 }
 272         }
 273 }
 274
 275
 276 static void nv04_dfp_mode_set(struct drm_encoder *encoder,
 277                               struct drm_display_mode *mode,
 278                               struct drm_display_mode *adjusted_mode)
 279 {
 280         struct drm_device *dev = encoder->dev;
 281         struct drm_nouveau_private *dev_priv = dev->dev_private;
 282         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 283         struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
 284         struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
 285         struct nouveau_connector *nv_connector = nouveau_crtc_connector_get(nv_crtc);
 286         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 287         struct drm_display_mode *output_mode = &nv_encoder->mode;
 288         struct drm_connector *connector = &nv_connector->base;
 289         uint32_t mode_ratio, panel_ratio;
 290
 291         NV_DEBUG_KMS(dev, "Output mode on CRTC %d:\n", nv_crtc->index);
 292         drm_mode_debug_printmodeline(output_mode);
 293
 294         /* Initialize the FP registers in this CRTC. */
 295         regp->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
 296         regp->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
 297         if (!nv_gf4_disp_arch(dev) ||
 298             (output_mode->hsync_start - output_mode->hdisplay) >=
 299                                         dev_priv->vbios.digital_min_front_porch)
 300                 regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay;
 301         else
 302                 regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - dev_priv->vbios.digital_min_front_porch - 1;
 303         regp->fp_horiz_regs[FP_SYNC_START] = output_mode->hsync_start - 1;
 304         regp->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
 305         regp->fp_horiz_regs[FP_VALID_START] = output_mode->hskew;
 306         regp->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - 1;
 307
 308         regp->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
 309         regp->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
 310         regp->fp_vert_regs[FP_CRTC] = output_mode->vtotal - 5 - 1;
 311         regp->fp_vert_regs[FP_SYNC_START] = output_mode->vsync_start - 1;
 312         regp->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
 313         regp->fp_vert_regs[FP_VALID_START] = 0;
 314         regp->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - 1;
 315
 316         /* bit26: a bit seen on some g7x, no as yet discernable purpose */
 317         regp->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
 318                            (savep->fp_control & (1 << 26 | NV_PRAMDAC_FP_TG_CONTROL_READ_PROG));
 319         /* Deal with vsync/hsync polarity */
 320         /* LVDS screens do set this, but modes with +ve syncs are very rare */
 321         if (output_mode->flags & DRM_MODE_FLAG_PVSYNC)
 322                 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;
 323         if (output_mode->flags & DRM_MODE_FLAG_PHSYNC)
 324                 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;
 325         /* panel scaling first, as native would get set otherwise */
 326         if (nv_connector->scaling_mode == DRM_MODE_SCALE_NONE ||
 327             nv_connector->scaling_mode == DRM_MODE_SCALE_CENTER)        /* panel handles it */
 328                 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_CENTER;
 329         else if (adjusted_mode->hdisplay == output_mode->hdisplay &&
 330                  adjusted_mode->vdisplay == output_mode->vdisplay) /* native mode */
 331                 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE;
 332         else /* gpu needs to scale */
 333                 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE;
 334         if (nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
 335                 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
 336         if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP &&
 337             output_mode->clock > 165000)
 338                 regp->fp_control |= (2 << 24);
 339         if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) {
 340                 bool duallink = false, dummy;
 341                 if (nv_connector->edid &&
 342                     nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
 343                         duallink = (((u8 *)nv_connector->edid)[121] == 2);
 344                 } else {
 345                         nouveau_bios_parse_lvds_table(dev, output_mode->clock,
 346                                                       &duallink, &dummy);
 347                 }
 348
 349                 if (duallink)
 350                         regp->fp_control |= (8 << 28);
 351         } else
 352         if (output_mode->clock > 165000)
 353                 regp->fp_control |= (8 << 28);
 354
 355         regp->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND |
 356                            NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND |
 357                            NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR |
 358                            NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR |
 359                            NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED |
 360                            NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE |
 361                            NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE;
 362
 363         /* We want automatic scaling */
 364         regp->fp_debug_1 = 0;
 365         /* This can override HTOTAL and VTOTAL */
 366         regp->fp_debug_2 = 0;
 367
 368         /* Use 20.12 fixed point format to avoid floats */
 369         mode_ratio = (1 << 12) * adjusted_mode->hdisplay / adjusted_mode->vdisplay;
 370         panel_ratio = (1 << 12) * output_mode->hdisplay / output_mode->vdisplay;
 371         /* if ratios are equal, SCALE_ASPECT will automatically (and correctly)
 372          * get treated the same as SCALE_FULLSCREEN */
 373         if (nv_connector->scaling_mode == DRM_MODE_SCALE_ASPECT &&
 374             mode_ratio != panel_ratio) {
 375                 uint32_t diff, scale;
 376                 bool divide_by_2 = nv_gf4_disp_arch(dev);
 377
 378                 if (mode_ratio < panel_ratio) {
 379                         /* vertical needs to expand to glass size (automatic)
 380                          * horizontal needs to be scaled at vertical scale factor
 381                          * to maintain aspect */
 382
 383                         scale = (1 << 12) * adjusted_mode->vdisplay / output_mode->vdisplay;
 384                         regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE_ENABLE |
 385                                            XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_XSCALE_VALUE);
 386
 387                         /* restrict area of screen used, horizontally */
 388                         diff = output_mode->hdisplay -
 389                                output_mode->vdisplay * mode_ratio / (1 << 12);
 390                         regp->fp_horiz_regs[FP_VALID_START] += diff / 2;
 391                         regp->fp_horiz_regs[FP_VALID_END] -= diff / 2;
 392                 }
 393
 394                 if (mode_ratio > panel_ratio) {
 395                         /* horizontal needs to expand to glass size (automatic)
 396                          * vertical needs to be scaled at horizontal scale factor
 397                          * to maintain aspect */
 398
 399                         scale = (1 << 12) * adjusted_mode->hdisplay / output_mode->hdisplay;
 400                         regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE_ENABLE |
 401                                            XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_YSCALE_VALUE);
 402
 403                         /* restrict area of screen used, vertically */
 404                         diff = output_mode->vdisplay -
 405                                (1 << 12) * output_mode->hdisplay / mode_ratio;
 406                         regp->fp_vert_regs[FP_VALID_START] += diff / 2;
 407                         regp->fp_vert_regs[FP_VALID_END] -= diff / 2;
 408                 }
 409         }
 410
 411         /* Output property. */
 412         if ((nv_connector->dithering_mode == DITHERING_MODE_ON) ||
 413             (nv_connector->dithering_mode == DITHERING_MODE_AUTO &&
 414              encoder->crtc->fb->depth > connector->display_info.bpc * 3)) {
 415                 if (dev_priv->chipset == 0x11)
 416                         regp->dither = savep->dither | 0x00010000;
 417                 else {
 418                         int i;
 419                         regp->dither = savep->dither | 0x00000001;
 420                         for (i = 0; i < 3; i++) {
 421                                 regp->dither_regs[i] = 0xe4e4e4e4;
 422                                 regp->dither_regs[i + 3] = 0x44444444;
 423                         }
 424                 }
 425         } else {
 426                 if (dev_priv->chipset != 0x11) {
 427                         /* reset them */
 428                         int i;
 429                         for (i = 0; i < 3; i++) {
 430                                 regp->dither_regs[i] = savep->dither_regs[i];
 431                                 regp->dither_regs[i + 3] = savep->dither_regs[i + 3];
 432                         }
 433                 }
 434                 regp->dither = savep->dither;
 435         }
 436
 437         regp->fp_margin_color = 0;
 438 }
 439
 440 static void nv04_dfp_commit(struct drm_encoder *encoder)
 441 {
 442         struct drm_device *dev = encoder->dev;
 443         struct drm_nouveau_private *dev_priv = dev->dev_private;
 444         struct drm_encoder_helper_funcs *helper = encoder->helper_private;
 445         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 446         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 447         struct dcb_output *dcbe = nv_encoder->dcb;
 448         int head = nouveau_crtc(encoder->crtc)->index;
 449         struct drm_encoder *slave_encoder;
 450
 451         if (dcbe->type == DCB_OUTPUT_TMDS)
 452                 run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock);
 453         else if (dcbe->type == DCB_OUTPUT_LVDS)
 454                 call_lvds_script(dev, dcbe, head, LVDS_RESET, nv_encoder->mode.clock);
 455
 456         /* update fp_control state for any changes made by scripts,
 457          * so correct value is written at DPMS on */
 458         nv04_display(dev)->mode_reg.crtc_reg[head].fp_control =
 459                 NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
 460
 461         /* This could use refinement for flatpanels, but it should work this way */
 462         if (dev_priv->chipset < 0x44)
 463                 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000);
 464         else
 465                 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000);
 466
 467         /* Init external transmitters */
 468         slave_encoder = get_tmds_slave(encoder);
 469         if (slave_encoder)
 470                 get_slave_funcs(slave_encoder)->mode_set(
 471                         slave_encoder, &nv_encoder->mode, &nv_encoder->mode);
 472
 473         helper->dpms(encoder, DRM_MODE_DPMS_ON);
 474
 475         NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
 476                 drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base),
 477                 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
 478 }
 479
 480 static void nv04_dfp_update_backlight(struct drm_encoder *encoder, int mode)
 481 {
 482 #ifdef __powerpc__
 483         struct drm_device *dev = encoder->dev;
 484
 485         /* BIOS scripts usually take care of the backlight, thanks
 486          * Apple for your consistency.
 487          */
 488         if (dev->pci_device == 0x0179 || dev->pci_device == 0x0189 ||
 489             dev->pci_device == 0x0329) {
 490                 if (mode == DRM_MODE_DPMS_ON) {
 491                         nv_mask(dev, NV_PBUS_DEBUG_DUALHEAD_CTL, 0, 1 << 31);
 492                         nv_mask(dev, NV_PCRTC_GPIO_EXT, 3, 1);
 493                 } else {
 494                         nv_mask(dev, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 0);
 495                         nv_mask(dev, NV_PCRTC_GPIO_EXT, 3, 0);
 496                 }
 497         }
 498 #endif
 499 }
 500
 501 static inline bool is_powersaving_dpms(int mode)
 502 {
 503         return (mode != DRM_MODE_DPMS_ON);
 504 }
 505
 506 static void nv04_lvds_dpms(struct drm_encoder *encoder, int mode)
 507 {
 508         struct drm_device *dev = encoder->dev;
 509         struct drm_crtc *crtc = encoder->crtc;
 510         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 511         bool was_powersaving = is_powersaving_dpms(nv_encoder->last_dpms);
 512
 513         if (nv_encoder->last_dpms == mode)
 514                 return;
 515         nv_encoder->last_dpms = mode;
 516
 517         NV_INFO(dev, "Setting dpms mode %d on lvds encoder (output %d)\n",
 518                      mode, nv_encoder->dcb->index);
 519
 520         if (was_powersaving && is_powersaving_dpms(mode))
 521                 return;
 522
 523         if (nv_encoder->dcb->lvdsconf.use_power_scripts) {
 524                 /* when removing an output, crtc may not be set, but PANEL_OFF
 525                  * must still be run
 526                  */
 527                 int head = crtc ? nouveau_crtc(crtc)->index :
 528                            nv04_dfp_get_bound_head(dev, nv_encoder->dcb);
 529
 530                 if (mode == DRM_MODE_DPMS_ON) {
 531                         call_lvds_script(dev, nv_encoder->dcb, head,
 532                                          LVDS_PANEL_ON, nv_encoder->mode.clock);
 533                 } else
 534                         /* pxclk of 0 is fine for PANEL_OFF, and for a
 535                          * disconnected LVDS encoder there is no native_mode
 536                          */
 537                         call_lvds_script(dev, nv_encoder->dcb, head,
 538                                          LVDS_PANEL_OFF, 0);
 539         }
 540
 541         nv04_dfp_update_backlight(encoder, mode);
 542         nv04_dfp_update_fp_control(encoder, mode);
 543
 544         if (mode == DRM_MODE_DPMS_ON)
 545                 nv04_dfp_prepare_sel_clk(dev, nv_encoder, nouveau_crtc(crtc)->index);
 546         else {
 547                 nv04_display(dev)->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
 548                 nv04_display(dev)->mode_reg.sel_clk &= ~0xf0;
 549         }
 550         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
 551 }
 552
 553 static void nv04_tmds_dpms(struct drm_encoder *encoder, int mode)
 554 {
 555         struct drm_device *dev = encoder->dev;
 556         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 557
 558         if (nv_encoder->last_dpms == mode)
 559                 return;
 560         nv_encoder->last_dpms = mode;
 561
 562         NV_INFO(dev, "Setting dpms mode %d on tmds encoder (output %d)\n",
 563                      mode, nv_encoder->dcb->index);
 564
 565         nv04_dfp_update_backlight(encoder, mode);
 566         nv04_dfp_update_fp_control(encoder, mode);
 567 }
 568
 569 static void nv04_dfp_save(struct drm_encoder *encoder)
 570 {
 571         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 572         struct drm_device *dev = encoder->dev;
 573
 574         if (nv_two_heads(dev))
 575                 nv_encoder->restore.head =
 576                         nv04_dfp_get_bound_head(dev, nv_encoder->dcb);
 577 }
 578
 579 static void nv04_dfp_restore(struct drm_encoder *encoder)
 580 {
 581         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 582         struct drm_device *dev = encoder->dev;
 583         int head = nv_encoder->restore.head;
 584
 585         if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) {
 586                 struct nouveau_connector *connector =
 587                         nouveau_encoder_connector_get(nv_encoder);
 588
 589                 if (connector && connector->native_mode)
 590                         call_lvds_script(dev, nv_encoder->dcb, head,
 591                                          LVDS_PANEL_ON,
 592                                          connector->native_mode->clock);
 593
 594         } else if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS) {
 595                 int clock = nouveau_hw_pllvals_to_clk
 596                                         (&nv04_display(dev)->saved_reg.crtc_reg[head].pllvals);
 597
 598                 run_tmds_table(dev, nv_encoder->dcb, head, clock);
 599         }
 600
 601         nv_encoder->last_dpms = NV_DPMS_CLEARED;
 602 }
 603
 604 static void nv04_dfp_destroy(struct drm_encoder *encoder)
 605 {
 606         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 607
 608         NV_DEBUG_KMS(encoder->dev, "\n");
 609
 610         if (get_slave_funcs(encoder))
 611                 get_slave_funcs(encoder)->destroy(encoder);
 612
 613         drm_encoder_cleanup(encoder);
 614         kfree(nv_encoder);
 615 }
 616
 617 static void nv04_tmds_slave_init(struct drm_encoder *encoder)
 618 {
 619         struct drm_device *dev = encoder->dev;
 620         struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
 621         struct nouveau_i2c_port *i2c = nouveau_i2c_find(dev, 2);
 622         struct i2c_board_info info[] = {
 623                 {
 624                         .type = "sil164",
 625                         .addr = (dcb->tmdsconf.slave_addr == 0x7 ? 0x3a : 0x38),
 626                         .platform_data = &(struct sil164_encoder_params) {
 627                                 SIL164_INPUT_EDGE_RISING
 628                         }
 629                 },
 630                 { }
 631         };
 632         int type;
 633
 634         if (!nv_gf4_disp_arch(dev) || !i2c ||
 635             get_tmds_slave(encoder))
 636                 return;
 637
 638         type = nouveau_i2c_identify(dev, "TMDS transmitter", info, NULL, 2);
 639         if (type < 0)
 640                 return;
 641
 642         drm_i2c_encoder_init(dev, to_encoder_slave(encoder),
 643                              nouveau_i2c_adapter(i2c), &info[type]);
 644 }
 645
 646 static const struct drm_encoder_helper_funcs nv04_lvds_helper_funcs = {
 647         .dpms = nv04_lvds_dpms,
 648         .save = nv04_dfp_save,
 649         .restore = nv04_dfp_restore,
 650         .mode_fixup = nv04_dfp_mode_fixup,
 651         .prepare = nv04_dfp_prepare,
 652         .commit = nv04_dfp_commit,
 653         .mode_set = nv04_dfp_mode_set,
 654         .detect = NULL,
 655 };
 656
 657 static const struct drm_encoder_helper_funcs nv04_tmds_helper_funcs = {
 658         .dpms = nv04_tmds_dpms,
 659         .save = nv04_dfp_save,
 660         .restore = nv04_dfp_restore,
 661         .mode_fixup = nv04_dfp_mode_fixup,
 662         .prepare = nv04_dfp_prepare,
 663         .commit = nv04_dfp_commit,
 664         .mode_set = nv04_dfp_mode_set,
 665         .detect = NULL,
 666 };
 667
 668 static const struct drm_encoder_funcs nv04_dfp_funcs = {
 669         .destroy = nv04_dfp_destroy,
 670 };
 671
 672 int
 673 nv04_dfp_create(struct drm_connector *connector, struct dcb_output *entry)
 674 {
 675         const struct drm_encoder_helper_funcs *helper;
 676         struct nouveau_encoder *nv_encoder = NULL;
 677         struct drm_encoder *encoder;
 678         int type;
 679
 680         switch (entry->type) {
 681         case DCB_OUTPUT_TMDS:
 682                 type = DRM_MODE_ENCODER_TMDS;
 683                 helper = &nv04_tmds_helper_funcs;
 684                 break;
 685         case DCB_OUTPUT_LVDS:
 686                 type = DRM_MODE_ENCODER_LVDS;
 687                 helper = &nv04_lvds_helper_funcs;
 688                 break;
 689         default:
 690                 return -EINVAL;
 691         }
 692
 693         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 694         if (!nv_encoder)
 695                 return -ENOMEM;
 696
 697         encoder = to_drm_encoder(nv_encoder);
 698
 699         nv_encoder->dcb = entry;
 700         nv_encoder->or = ffs(entry->or) - 1;
 701
 702         drm_encoder_init(connector->dev, encoder, &nv04_dfp_funcs, type);
 703         drm_encoder_helper_add(encoder, helper);
 704
 705         encoder->possible_crtcs = entry->heads;
 706         encoder->possible_clones = 0;
 707
 708         if (entry->type == DCB_OUTPUT_TMDS &&
 709             entry->location != DCB_LOC_ON_CHIP)
 710                 nv04_tmds_slave_init(encoder);
 711
 712         drm_mode_connector_attach_encoder(connector, encoder);
 713         return 0;
 714 }