drivers/gpu/drm/nouveau/nv04_fifo.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30 #include "nouveau_ramht.h"
  31 #include "nouveau_util.h"
  32
  33 #define NV04_RAMFC(c) (dev_priv->ramfc->pinst + ((c) * NV04_RAMFC__SIZE))
  34 #define NV04_RAMFC__SIZE 32
  35 #define NV04_RAMFC_DMA_PUT                                       0x00
  36 #define NV04_RAMFC_DMA_GET                                       0x04
  37 #define NV04_RAMFC_DMA_INSTANCE                                  0x08
  38 #define NV04_RAMFC_DMA_STATE                                     0x0C
  39 #define NV04_RAMFC_DMA_FETCH                                     0x10
  40 #define NV04_RAMFC_ENGINE                                        0x14
  41 #define NV04_RAMFC_PULL1_ENGINE                                  0x18
  42
  43 #define RAMFC_WR(offset, val) nv_wo32(chan->ramfc, NV04_RAMFC_##offset, (val))
  44 #define RAMFC_RD(offset)      nv_ro32(chan->ramfc, NV04_RAMFC_##offset)
  45
  46 void
  47 nv04_fifo_disable(struct drm_device *dev)
  48 {
  49         uint32_t tmp;
  50
  51         tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUSH);
  52         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, tmp & ~1);
  53         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 0);
  54         tmp = nv_rd32(dev, NV03_PFIFO_CACHE1_PULL1);
  55         nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, tmp & ~1);
  56 }
  57
  58 void
  59 nv04_fifo_enable(struct drm_device *dev)
  60 {
  61         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 1);
  62         nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
  63 }
  64
  65 bool
  66 nv04_fifo_reassign(struct drm_device *dev, bool enable)
  67 {
  68         uint32_t reassign = nv_rd32(dev, NV03_PFIFO_CACHES);
  69
  70         nv_wr32(dev, NV03_PFIFO_CACHES, enable ? 1 : 0);
  71         return (reassign == 1);
  72 }
  73
  74 bool
  75 nv04_fifo_cache_pull(struct drm_device *dev, bool enable)
  76 {
  77         int pull = nv_mask(dev, NV04_PFIFO_CACHE1_PULL0, 1, enable);
  78
  79         if (!enable) {
  80                 /* In some cases the PFIFO puller may be left in an
  81                  * inconsistent state if you try to stop it when it's
  82                  * busy translating handles. Sometimes you get a
  83                  * PFIFO_CACHE_ERROR, sometimes it just fails silently
  84                  * sending incorrect instance offsets to PGRAPH after
  85                  * it's started up again. To avoid the latter we
  86                  * invalidate the most recently calculated instance.
  87                  */
  88                 if (!nv_wait(dev, NV04_PFIFO_CACHE1_PULL0,
  89                              NV04_PFIFO_CACHE1_PULL0_HASH_BUSY, 0))
  90                         NV_ERROR(dev, "Timeout idling the PFIFO puller.\n");
  91
  92                 if (nv_rd32(dev, NV04_PFIFO_CACHE1_PULL0) &
  93                     NV04_PFIFO_CACHE1_PULL0_HASH_FAILED)
  94                         nv_wr32(dev, NV03_PFIFO_INTR_0,
  95                                 NV_PFIFO_INTR_CACHE_ERROR);
  96
  97                 nv_wr32(dev, NV04_PFIFO_CACHE1_HASH, 0);
  98         }
  99
 100         return pull & 1;
 101 }
 102
 103 int
 104 nv04_fifo_channel_id(struct drm_device *dev)
 105 {
 106         return nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) &
 107                         NV03_PFIFO_CACHE1_PUSH1_CHID_MASK;
 108 }
 109
 110 #ifdef __BIG_ENDIAN
 111 #define DMA_FETCH_ENDIANNESS NV_PFIFO_CACHE1_BIG_ENDIAN
 112 #else
 113 #define DMA_FETCH_ENDIANNESS 0
 114 #endif
 115
 116 int
 117 nv04_fifo_create_context(struct nouveau_channel *chan)
 118 {
 119         struct drm_device *dev = chan->dev;
 120         struct drm_nouveau_private *dev_priv = dev->dev_private;
 121         unsigned long flags;
 122         int ret;
 123
 124         ret = nouveau_gpuobj_new_fake(dev, NV04_RAMFC(chan->id), ~0,
 125                                                 NV04_RAMFC__SIZE,
 126                                                 NVOBJ_FLAG_ZERO_ALLOC |
 127                                                 NVOBJ_FLAG_ZERO_FREE,
 128                                                 &chan->ramfc);
 129         if (ret)
 130                 return ret;
 131
 132         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 133
 134         /* Setup initial state */
 135         RAMFC_WR(DMA_PUT, chan->pushbuf_base);
 136         RAMFC_WR(DMA_GET, chan->pushbuf_base);
 137         RAMFC_WR(DMA_INSTANCE, chan->pushbuf->pinst >> 4);
 138         RAMFC_WR(DMA_FETCH, (NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
 139                              NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
 140                              NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
 141                              DMA_FETCH_ENDIANNESS));
 142
 143         /* enable the fifo dma operation */
 144         nv_wr32(dev, NV04_PFIFO_MODE,
 145                 nv_rd32(dev, NV04_PFIFO_MODE) | (1 << chan->id));
 146
 147         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 148         return 0;
 149 }
 150
 151 void
 152 nv04_fifo_destroy_context(struct nouveau_channel *chan)
 153 {
 154         struct drm_device *dev = chan->dev;
 155         struct drm_nouveau_private *dev_priv = dev->dev_private;
 156         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 157         unsigned long flags;
 158
 159         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 160         pfifo->reassign(dev, false);
 161
 162         /* Unload the context if it's the currently active one */
 163         if (pfifo->channel_id(dev) == chan->id) {
 164                 pfifo->disable(dev);
 165                 pfifo->unload_context(dev);
 166                 pfifo->enable(dev);
 167         }
 168
 169         /* Keep it from being rescheduled */
 170         nv_mask(dev, NV04_PFIFO_MODE, 1 << chan->id, 0);
 171
 172         pfifo->reassign(dev, true);
 173         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 174
 175         /* Free the channel resources */
 176         nouveau_gpuobj_ref(NULL, &chan->ramfc);
 177 }
 178
 179 static void
 180 nv04_fifo_do_load_context(struct drm_device *dev, int chid)
 181 {
 182         struct drm_nouveau_private *dev_priv = dev->dev_private;
 183         uint32_t fc = NV04_RAMFC(chid), tmp;
 184
 185         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUT, nv_ri32(dev, fc + 0));
 186         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_GET, nv_ri32(dev, fc + 4));
 187         tmp = nv_ri32(dev, fc + 8);
 188         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE, tmp & 0xFFFF);
 189         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT, tmp >> 16);
 190         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_STATE, nv_ri32(dev, fc + 12));
 191         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_FETCH, nv_ri32(dev, fc + 16));
 192         nv_wr32(dev, NV04_PFIFO_CACHE1_ENGINE, nv_ri32(dev, fc + 20));
 193         nv_wr32(dev, NV04_PFIFO_CACHE1_PULL1, nv_ri32(dev, fc + 24));
 194
 195         nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
 196         nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, 0);
 197 }
 198
 199 int
 200 nv04_fifo_load_context(struct nouveau_channel *chan)
 201 {
 202         uint32_t tmp;
 203
 204         nv_wr32(chan->dev, NV03_PFIFO_CACHE1_PUSH1,
 205                            NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id);
 206         nv04_fifo_do_load_context(chan->dev, chan->id);
 207         nv_wr32(chan->dev, NV04_PFIFO_CACHE1_DMA_PUSH, 1);
 208
 209         /* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */
 210         tmp = nv_rd32(chan->dev, NV04_PFIFO_CACHE1_DMA_CTL) & ~(1 << 31);
 211         nv_wr32(chan->dev, NV04_PFIFO_CACHE1_DMA_CTL, tmp);
 212
 213         return 0;
 214 }
 215
 216 int
 217 nv04_fifo_unload_context(struct drm_device *dev)
 218 {
 219         struct drm_nouveau_private *dev_priv = dev->dev_private;
 220         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 221         struct nouveau_channel *chan = NULL;
 222         uint32_t tmp;
 223         int chid;
 224
 225         chid = pfifo->channel_id(dev);
 226         if (chid < 0 || chid >= dev_priv->engine.fifo.channels)
 227                 return 0;
 228
 229         chan = dev_priv->channels.ptr[chid];
 230         if (!chan) {
 231                 NV_ERROR(dev, "Inactive channel on PFIFO: %d\n", chid);
 232                 return -EINVAL;
 233         }
 234
 235         RAMFC_WR(DMA_PUT, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT));
 236         RAMFC_WR(DMA_GET, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));
 237         tmp  = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16;
 238         tmp |= nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE);
 239         RAMFC_WR(DMA_INSTANCE, tmp);
 240         RAMFC_WR(DMA_STATE, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_STATE));
 241         RAMFC_WR(DMA_FETCH, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_FETCH));
 242         RAMFC_WR(ENGINE, nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE));
 243         RAMFC_WR(PULL1_ENGINE, nv_rd32(dev, NV04_PFIFO_CACHE1_PULL1));
 244
 245         nv04_fifo_do_load_context(dev, pfifo->channels - 1);
 246         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
 247         return 0;
 248 }
 249
 250 static void
 251 nv04_fifo_init_reset(struct drm_device *dev)
 252 {
 253         nv_wr32(dev, NV03_PMC_ENABLE,
 254                 nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PFIFO);
 255         nv_wr32(dev, NV03_PMC_ENABLE,
 256                 nv_rd32(dev, NV03_PMC_ENABLE) |  NV_PMC_ENABLE_PFIFO);
 257
 258         nv_wr32(dev, 0x003224, 0x000f0078);
 259         nv_wr32(dev, 0x002044, 0x0101ffff);
 260         nv_wr32(dev, 0x002040, 0x000000ff);
 261         nv_wr32(dev, 0x002500, 0x00000000);
 262         nv_wr32(dev, 0x003000, 0x00000000);
 263         nv_wr32(dev, 0x003050, 0x00000000);
 264         nv_wr32(dev, 0x003200, 0x00000000);
 265         nv_wr32(dev, 0x003250, 0x00000000);
 266         nv_wr32(dev, 0x003220, 0x00000000);
 267
 268         nv_wr32(dev, 0x003250, 0x00000000);
 269         nv_wr32(dev, 0x003270, 0x00000000);
 270         nv_wr32(dev, 0x003210, 0x00000000);
 271 }
 272
 273 static void
 274 nv04_fifo_init_ramxx(struct drm_device *dev)
 275 {
 276         struct drm_nouveau_private *dev_priv = dev->dev_private;
 277
 278         nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
 279                                        ((dev_priv->ramht->bits - 9) << 16) |
 280                                        (dev_priv->ramht->gpuobj->pinst >> 8));
 281         nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro->pinst >> 8);
 282         nv_wr32(dev, NV03_PFIFO_RAMFC, dev_priv->ramfc->pinst >> 8);
 283 }
 284
 285 static void
 286 nv04_fifo_init_intr(struct drm_device *dev)
 287 {
 288         nouveau_irq_register(dev, 8, nv04_fifo_isr);
 289         nv_wr32(dev, 0x002100, 0xffffffff);
 290         nv_wr32(dev, 0x002140, 0xffffffff);
 291 }
 292
 293 int
 294 nv04_fifo_init(struct drm_device *dev)
 295 {
 296         struct drm_nouveau_private *dev_priv = dev->dev_private;
 297         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 298         int i;
 299
 300         nv04_fifo_init_reset(dev);
 301         nv04_fifo_init_ramxx(dev);
 302
 303         nv04_fifo_do_load_context(dev, pfifo->channels - 1);
 304         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
 305
 306         nv04_fifo_init_intr(dev);
 307         pfifo->enable(dev);
 308         pfifo->reassign(dev, true);
 309
 310         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
 311                 if (dev_priv->channels.ptr[i]) {
 312                         uint32_t mode = nv_rd32(dev, NV04_PFIFO_MODE);
 313                         nv_wr32(dev, NV04_PFIFO_MODE, mode | (1 << i));
 314                 }
 315         }
 316
 317         return 0;
 318 }
 319
 320 void
 321 nv04_fifo_fini(struct drm_device *dev)
 322 {
 323         nv_wr32(dev, 0x2140, 0x00000000);
 324         nouveau_irq_unregister(dev, 8);
 325 }
 326
 327 static bool
 328 nouveau_fifo_swmthd(struct drm_device *dev, u32 chid, u32 addr, u32 data)
 329 {
 330         struct drm_nouveau_private *dev_priv = dev->dev_private;
 331         struct nouveau_channel *chan = NULL;
 332         struct nouveau_gpuobj *obj;
 333         unsigned long flags;
 334         const int subc = (addr >> 13) & 0x7;
 335         const int mthd = addr & 0x1ffc;
 336         bool handled = false;
 337         u32 engine;
 338
 339         spin_lock_irqsave(&dev_priv->channels.lock, flags);
 340         if (likely(chid >= 0 && chid < dev_priv->engine.fifo.channels))
 341                 chan = dev_priv->channels.ptr[chid];
 342         if (unlikely(!chan))
 343                 goto out;
 344
 345         switch (mthd) {
 346         case 0x0000: /* bind object to subchannel */
 347                 obj = nouveau_ramht_find(chan, data);
 348                 if (unlikely(!obj || obj->engine != NVOBJ_ENGINE_SW))
 349                         break;
 350
 351                 chan->sw_subchannel[subc] = obj->class;
 352                 engine = 0x0000000f << (subc * 4);
 353
 354                 nv_mask(dev, NV04_PFIFO_CACHE1_ENGINE, engine, 0x00000000);
 355                 handled = true;
 356                 break;
 357         default:
 358                 engine = nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE);
 359                 if (unlikely(((engine >> (subc * 4)) & 0xf) != 0))
 360                         break;
 361
 362                 if (!nouveau_gpuobj_mthd_call(chan, chan->sw_subchannel[subc],
 363                                               mthd, data))
 364                         handled = true;
 365                 break;
 366         }
 367
 368 out:
 369         spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
 370         return handled;
 371 }
 372
 373 void
 374 nv04_fifo_isr(struct drm_device *dev)
 375 {
 376         struct drm_nouveau_private *dev_priv = dev->dev_private;
 377         struct nouveau_engine *engine = &dev_priv->engine;
 378         uint32_t status, reassign;
 379         int cnt = 0;
 380
 381         reassign = nv_rd32(dev, NV03_PFIFO_CACHES) & 1;
 382         while ((status = nv_rd32(dev, NV03_PFIFO_INTR_0)) && (cnt++ < 100)) {
 383                 uint32_t chid, get;
 384
 385                 nv_wr32(dev, NV03_PFIFO_CACHES, 0);
 386
 387                 chid = engine->fifo.channel_id(dev);
 388                 get  = nv_rd32(dev, NV03_PFIFO_CACHE1_GET);
 389
 390                 if (status & NV_PFIFO_INTR_CACHE_ERROR) {
 391                         uint32_t mthd, data;
 392                         int ptr;
 393
 394                         /* NV_PFIFO_CACHE1_GET actually goes to 0xffc before
 395                          * wrapping on my G80 chips, but CACHE1 isn't big
 396                          * enough for this much data.. Tests show that it
 397                          * wraps around to the start at GET=0x800.. No clue
 398                          * as to why..
 399                          */
 400                         ptr = (get & 0x7ff) >> 2;
 401
 402                         if (dev_priv->card_type < NV_40) {
 403                                 mthd = nv_rd32(dev,
 404                                         NV04_PFIFO_CACHE1_METHOD(ptr));
 405                                 data = nv_rd32(dev,
 406                                         NV04_PFIFO_CACHE1_DATA(ptr));
 407                         } else {
 408                                 mthd = nv_rd32(dev,
 409                                         NV40_PFIFO_CACHE1_METHOD(ptr));
 410                                 data = nv_rd32(dev,
 411                                         NV40_PFIFO_CACHE1_DATA(ptr));
 412                         }
 413
 414                         if (!nouveau_fifo_swmthd(dev, chid, mthd, data)) {
 415                                 NV_INFO(dev, "PFIFO_CACHE_ERROR - Ch %d/%d "
 416                                              "Mthd 0x%04x Data 0x%08x\n",
 417                                         chid, (mthd >> 13) & 7, mthd & 0x1ffc,
 418                                         data);
 419                         }
 420
 421                         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 0);
 422                         nv_wr32(dev, NV03_PFIFO_INTR_0,
 423                                                 NV_PFIFO_INTR_CACHE_ERROR);
 424
 425                         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0,
 426                                 nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH0) & ~1);
 427                         nv_wr32(dev, NV03_PFIFO_CACHE1_GET, get + 4);
 428                         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0,
 429                                 nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH0) | 1);
 430                         nv_wr32(dev, NV04_PFIFO_CACHE1_HASH, 0);
 431
 432                         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH,
 433                                 nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
 434                         nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
 435
 436                         status &= ~NV_PFIFO_INTR_CACHE_ERROR;
 437                 }
 438
 439                 if (status & NV_PFIFO_INTR_DMA_PUSHER) {
 440                         u32 dma_get = nv_rd32(dev, 0x003244);
 441                         u32 dma_put = nv_rd32(dev, 0x003240);
 442                         u32 push = nv_rd32(dev, 0x003220);
 443                         u32 state = nv_rd32(dev, 0x003228);
 444
 445                         if (dev_priv->card_type == NV_50) {
 446                                 u32 ho_get = nv_rd32(dev, 0x003328);
 447                                 u32 ho_put = nv_rd32(dev, 0x003320);
 448                                 u32 ib_get = nv_rd32(dev, 0x003334);
 449                                 u32 ib_put = nv_rd32(dev, 0x003330);
 450
 451                                 if (nouveau_ratelimit())
 452                                         NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d Get 0x%02x%08x "
 453                                              "Put 0x%02x%08x IbGet 0x%08x IbPut 0x%08x "
 454                                              "State 0x%08x Push 0x%08x\n",
 455                                                 chid, ho_get, dma_get, ho_put,
 456                                                 dma_put, ib_get, ib_put, state,
 457                                                 push);
 458
 459                                 /* METHOD_COUNT, in DMA_STATE on earlier chipsets */
 460                                 nv_wr32(dev, 0x003364, 0x00000000);
 461                                 if (dma_get != dma_put || ho_get != ho_put) {
 462                                         nv_wr32(dev, 0x003244, dma_put);
 463                                         nv_wr32(dev, 0x003328, ho_put);
 464                                 } else
 465                                 if (ib_get != ib_put) {
 466                                         nv_wr32(dev, 0x003334, ib_put);
 467                                 }
 468                         } else {
 469                                 NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d Get 0x%08x "
 470                                              "Put 0x%08x State 0x%08x Push 0x%08x\n",
 471                                         chid, dma_get, dma_put, state, push);
 472
 473                                 if (dma_get != dma_put)
 474                                         nv_wr32(dev, 0x003244, dma_put);
 475                         }
 476
 477                         nv_wr32(dev, 0x003228, 0x00000000);
 478                         nv_wr32(dev, 0x003220, 0x00000001);
 479                         nv_wr32(dev, 0x002100, NV_PFIFO_INTR_DMA_PUSHER);
 480                         status &= ~NV_PFIFO_INTR_DMA_PUSHER;
 481                 }
 482
 483                 if (status & NV_PFIFO_INTR_SEMAPHORE) {
 484                         uint32_t sem;
 485
 486                         status &= ~NV_PFIFO_INTR_SEMAPHORE;
 487                         nv_wr32(dev, NV03_PFIFO_INTR_0,
 488                                 NV_PFIFO_INTR_SEMAPHORE);
 489
 490                         sem = nv_rd32(dev, NV10_PFIFO_CACHE1_SEMAPHORE);
 491                         nv_wr32(dev, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1);
 492
 493                         nv_wr32(dev, NV03_PFIFO_CACHE1_GET, get + 4);
 494                         nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
 495                 }
 496
 497                 if (dev_priv->card_type == NV_50) {
 498                         if (status & 0x00000010) {
 499                                 nv50_fb_vm_trap(dev, 1, "PFIFO_BAR_FAULT");
 500                                 status &= ~0x00000010;
 501                                 nv_wr32(dev, 0x002100, 0x00000010);
 502                         }
 503                 }
 504
 505                 if (status) {
 506                         if (nouveau_ratelimit())
 507                                 NV_INFO(dev, "PFIFO_INTR 0x%08x - Ch %d\n",
 508                                         status, chid);
 509                         nv_wr32(dev, NV03_PFIFO_INTR_0, status);
 510                         status = 0;
 511                 }
 512
 513                 nv_wr32(dev, NV03_PFIFO_CACHES, reassign);
 514         }
 515
 516         if (status) {
 517                 NV_INFO(dev, "PFIFO still angry after %d spins, halt\n", cnt);
 518                 nv_wr32(dev, 0x2140, 0);
 519                 nv_wr32(dev, 0x140, 0);
 520         }
 521
 522         nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PFIFO_PENDING);
 523 }