drivers/gpu/drm/nouveau/nv04_graph.c

   1 /*
   2  * Copyright 2007 Stephane Marchesin
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "drmP.h"
  26 #include "drm.h"
  27 #include "nouveau_drm.h"
  28 #include "nouveau_drv.h"
  29 #include "nouveau_hw.h"
  30 #include "nouveau_util.h"
  31 #include "nouveau_ramht.h"
  32
  33 struct nv04_graph_engine {
  34         struct nouveau_exec_engine base;
  35 };
  36
  37 static uint32_t nv04_graph_ctx_regs[] = {
  38         0x0040053c,
  39         0x00400544,
  40         0x00400540,
  41         0x00400548,
  42         NV04_PGRAPH_CTX_SWITCH1,
  43         NV04_PGRAPH_CTX_SWITCH2,
  44         NV04_PGRAPH_CTX_SWITCH3,
  45         NV04_PGRAPH_CTX_SWITCH4,
  46         NV04_PGRAPH_CTX_CACHE1,
  47         NV04_PGRAPH_CTX_CACHE2,
  48         NV04_PGRAPH_CTX_CACHE3,
  49         NV04_PGRAPH_CTX_CACHE4,
  50         0x00400184,
  51         0x004001a4,
  52         0x004001c4,
  53         0x004001e4,
  54         0x00400188,
  55         0x004001a8,
  56         0x004001c8,
  57         0x004001e8,
  58         0x0040018c,
  59         0x004001ac,
  60         0x004001cc,
  61         0x004001ec,
  62         0x00400190,
  63         0x004001b0,
  64         0x004001d0,
  65         0x004001f0,
  66         0x00400194,
  67         0x004001b4,
  68         0x004001d4,
  69         0x004001f4,
  70         0x00400198,
  71         0x004001b8,
  72         0x004001d8,
  73         0x004001f8,
  74         0x0040019c,
  75         0x004001bc,
  76         0x004001dc,
  77         0x004001fc,
  78         0x00400174,
  79         NV04_PGRAPH_DMA_START_0,
  80         NV04_PGRAPH_DMA_START_1,
  81         NV04_PGRAPH_DMA_LENGTH,
  82         NV04_PGRAPH_DMA_MISC,
  83         NV04_PGRAPH_DMA_PITCH,
  84         NV04_PGRAPH_BOFFSET0,
  85         NV04_PGRAPH_BBASE0,
  86         NV04_PGRAPH_BLIMIT0,
  87         NV04_PGRAPH_BOFFSET1,
  88         NV04_PGRAPH_BBASE1,
  89         NV04_PGRAPH_BLIMIT1,
  90         NV04_PGRAPH_BOFFSET2,
  91         NV04_PGRAPH_BBASE2,
  92         NV04_PGRAPH_BLIMIT2,
  93         NV04_PGRAPH_BOFFSET3,
  94         NV04_PGRAPH_BBASE3,
  95         NV04_PGRAPH_BLIMIT3,
  96         NV04_PGRAPH_BOFFSET4,
  97         NV04_PGRAPH_BBASE4,
  98         NV04_PGRAPH_BLIMIT4,
  99         NV04_PGRAPH_BOFFSET5,
 100         NV04_PGRAPH_BBASE5,
 101         NV04_PGRAPH_BLIMIT5,
 102         NV04_PGRAPH_BPITCH0,
 103         NV04_PGRAPH_BPITCH1,
 104         NV04_PGRAPH_BPITCH2,
 105         NV04_PGRAPH_BPITCH3,
 106         NV04_PGRAPH_BPITCH4,
 107         NV04_PGRAPH_SURFACE,
 108         NV04_PGRAPH_STATE,
 109         NV04_PGRAPH_BSWIZZLE2,
 110         NV04_PGRAPH_BSWIZZLE5,
 111         NV04_PGRAPH_BPIXEL,
 112         NV04_PGRAPH_NOTIFY,
 113         NV04_PGRAPH_PATT_COLOR0,
 114         NV04_PGRAPH_PATT_COLOR1,
 115         NV04_PGRAPH_PATT_COLORRAM+0x00,
 116         NV04_PGRAPH_PATT_COLORRAM+0x04,
 117         NV04_PGRAPH_PATT_COLORRAM+0x08,
 118         NV04_PGRAPH_PATT_COLORRAM+0x0c,
 119         NV04_PGRAPH_PATT_COLORRAM+0x10,
 120         NV04_PGRAPH_PATT_COLORRAM+0x14,
 121         NV04_PGRAPH_PATT_COLORRAM+0x18,
 122         NV04_PGRAPH_PATT_COLORRAM+0x1c,
 123         NV04_PGRAPH_PATT_COLORRAM+0x20,
 124         NV04_PGRAPH_PATT_COLORRAM+0x24,
 125         NV04_PGRAPH_PATT_COLORRAM+0x28,
 126         NV04_PGRAPH_PATT_COLORRAM+0x2c,
 127         NV04_PGRAPH_PATT_COLORRAM+0x30,
 128         NV04_PGRAPH_PATT_COLORRAM+0x34,
 129         NV04_PGRAPH_PATT_COLORRAM+0x38,
 130         NV04_PGRAPH_PATT_COLORRAM+0x3c,
 131         NV04_PGRAPH_PATT_COLORRAM+0x40,
 132         NV04_PGRAPH_PATT_COLORRAM+0x44,
 133         NV04_PGRAPH_PATT_COLORRAM+0x48,
 134         NV04_PGRAPH_PATT_COLORRAM+0x4c,
 135         NV04_PGRAPH_PATT_COLORRAM+0x50,
 136         NV04_PGRAPH_PATT_COLORRAM+0x54,
 137         NV04_PGRAPH_PATT_COLORRAM+0x58,
 138         NV04_PGRAPH_PATT_COLORRAM+0x5c,
 139         NV04_PGRAPH_PATT_COLORRAM+0x60,
 140         NV04_PGRAPH_PATT_COLORRAM+0x64,
 141         NV04_PGRAPH_PATT_COLORRAM+0x68,
 142         NV04_PGRAPH_PATT_COLORRAM+0x6c,
 143         NV04_PGRAPH_PATT_COLORRAM+0x70,
 144         NV04_PGRAPH_PATT_COLORRAM+0x74,
 145         NV04_PGRAPH_PATT_COLORRAM+0x78,
 146         NV04_PGRAPH_PATT_COLORRAM+0x7c,
 147         NV04_PGRAPH_PATT_COLORRAM+0x80,
 148         NV04_PGRAPH_PATT_COLORRAM+0x84,
 149         NV04_PGRAPH_PATT_COLORRAM+0x88,
 150         NV04_PGRAPH_PATT_COLORRAM+0x8c,
 151         NV04_PGRAPH_PATT_COLORRAM+0x90,
 152         NV04_PGRAPH_PATT_COLORRAM+0x94,
 153         NV04_PGRAPH_PATT_COLORRAM+0x98,
 154         NV04_PGRAPH_PATT_COLORRAM+0x9c,
 155         NV04_PGRAPH_PATT_COLORRAM+0xa0,
 156         NV04_PGRAPH_PATT_COLORRAM+0xa4,
 157         NV04_PGRAPH_PATT_COLORRAM+0xa8,
 158         NV04_PGRAPH_PATT_COLORRAM+0xac,
 159         NV04_PGRAPH_PATT_COLORRAM+0xb0,
 160         NV04_PGRAPH_PATT_COLORRAM+0xb4,
 161         NV04_PGRAPH_PATT_COLORRAM+0xb8,
 162         NV04_PGRAPH_PATT_COLORRAM+0xbc,
 163         NV04_PGRAPH_PATT_COLORRAM+0xc0,
 164         NV04_PGRAPH_PATT_COLORRAM+0xc4,
 165         NV04_PGRAPH_PATT_COLORRAM+0xc8,
 166         NV04_PGRAPH_PATT_COLORRAM+0xcc,
 167         NV04_PGRAPH_PATT_COLORRAM+0xd0,
 168         NV04_PGRAPH_PATT_COLORRAM+0xd4,
 169         NV04_PGRAPH_PATT_COLORRAM+0xd8,
 170         NV04_PGRAPH_PATT_COLORRAM+0xdc,
 171         NV04_PGRAPH_PATT_COLORRAM+0xe0,
 172         NV04_PGRAPH_PATT_COLORRAM+0xe4,
 173         NV04_PGRAPH_PATT_COLORRAM+0xe8,
 174         NV04_PGRAPH_PATT_COLORRAM+0xec,
 175         NV04_PGRAPH_PATT_COLORRAM+0xf0,
 176         NV04_PGRAPH_PATT_COLORRAM+0xf4,
 177         NV04_PGRAPH_PATT_COLORRAM+0xf8,
 178         NV04_PGRAPH_PATT_COLORRAM+0xfc,
 179         NV04_PGRAPH_PATTERN,
 180         0x0040080c,
 181         NV04_PGRAPH_PATTERN_SHAPE,
 182         0x00400600,
 183         NV04_PGRAPH_ROP3,
 184         NV04_PGRAPH_CHROMA,
 185         NV04_PGRAPH_BETA_AND,
 186         NV04_PGRAPH_BETA_PREMULT,
 187         NV04_PGRAPH_CONTROL0,
 188         NV04_PGRAPH_CONTROL1,
 189         NV04_PGRAPH_CONTROL2,
 190         NV04_PGRAPH_BLEND,
 191         NV04_PGRAPH_STORED_FMT,
 192         NV04_PGRAPH_SOURCE_COLOR,
 193         0x00400560,
 194         0x00400568,
 195         0x00400564,
 196         0x0040056c,
 197         0x00400400,
 198         0x00400480,
 199         0x00400404,
 200         0x00400484,
 201         0x00400408,
 202         0x00400488,
 203         0x0040040c,
 204         0x0040048c,
 205         0x00400410,
 206         0x00400490,
 207         0x00400414,
 208         0x00400494,
 209         0x00400418,
 210         0x00400498,
 211         0x0040041c,
 212         0x0040049c,
 213         0x00400420,
 214         0x004004a0,
 215         0x00400424,
 216         0x004004a4,
 217         0x00400428,
 218         0x004004a8,
 219         0x0040042c,
 220         0x004004ac,
 221         0x00400430,
 222         0x004004b0,
 223         0x00400434,
 224         0x004004b4,
 225         0x00400438,
 226         0x004004b8,
 227         0x0040043c,
 228         0x004004bc,
 229         0x00400440,
 230         0x004004c0,
 231         0x00400444,
 232         0x004004c4,
 233         0x00400448,
 234         0x004004c8,
 235         0x0040044c,
 236         0x004004cc,
 237         0x00400450,
 238         0x004004d0,
 239         0x00400454,
 240         0x004004d4,
 241         0x00400458,
 242         0x004004d8,
 243         0x0040045c,
 244         0x004004dc,
 245         0x00400460,
 246         0x004004e0,
 247         0x00400464,
 248         0x004004e4,
 249         0x00400468,
 250         0x004004e8,
 251         0x0040046c,
 252         0x004004ec,
 253         0x00400470,
 254         0x004004f0,
 255         0x00400474,
 256         0x004004f4,
 257         0x00400478,
 258         0x004004f8,
 259         0x0040047c,
 260         0x004004fc,
 261         0x00400534,
 262         0x00400538,
 263         0x00400514,
 264         0x00400518,
 265         0x0040051c,
 266         0x00400520,
 267         0x00400524,
 268         0x00400528,
 269         0x0040052c,
 270         0x00400530,
 271         0x00400d00,
 272         0x00400d40,
 273         0x00400d80,
 274         0x00400d04,
 275         0x00400d44,
 276         0x00400d84,
 277         0x00400d08,
 278         0x00400d48,
 279         0x00400d88,
 280         0x00400d0c,
 281         0x00400d4c,
 282         0x00400d8c,
 283         0x00400d10,
 284         0x00400d50,
 285         0x00400d90,
 286         0x00400d14,
 287         0x00400d54,
 288         0x00400d94,
 289         0x00400d18,
 290         0x00400d58,
 291         0x00400d98,
 292         0x00400d1c,
 293         0x00400d5c,
 294         0x00400d9c,
 295         0x00400d20,
 296         0x00400d60,
 297         0x00400da0,
 298         0x00400d24,
 299         0x00400d64,
 300         0x00400da4,
 301         0x00400d28,
 302         0x00400d68,
 303         0x00400da8,
 304         0x00400d2c,
 305         0x00400d6c,
 306         0x00400dac,
 307         0x00400d30,
 308         0x00400d70,
 309         0x00400db0,
 310         0x00400d34,
 311         0x00400d74,
 312         0x00400db4,
 313         0x00400d38,
 314         0x00400d78,
 315         0x00400db8,
 316         0x00400d3c,
 317         0x00400d7c,
 318         0x00400dbc,
 319         0x00400590,
 320         0x00400594,
 321         0x00400598,
 322         0x0040059c,
 323         0x004005a8,
 324         0x004005ac,
 325         0x004005b0,
 326         0x004005b4,
 327         0x004005c0,
 328         0x004005c4,
 329         0x004005c8,
 330         0x004005cc,
 331         0x004005d0,
 332         0x004005d4,
 333         0x004005d8,
 334         0x004005dc,
 335         0x004005e0,
 336         NV04_PGRAPH_PASSTHRU_0,
 337         NV04_PGRAPH_PASSTHRU_1,
 338         NV04_PGRAPH_PASSTHRU_2,
 339         NV04_PGRAPH_DVD_COLORFMT,
 340         NV04_PGRAPH_SCALED_FORMAT,
 341         NV04_PGRAPH_MISC24_0,
 342         NV04_PGRAPH_MISC24_1,
 343         NV04_PGRAPH_MISC24_2,
 344         0x00400500,
 345         0x00400504,
 346         NV04_PGRAPH_VALID1,
 347         NV04_PGRAPH_VALID2,
 348         NV04_PGRAPH_DEBUG_3
 349 };
 350
 351 struct graph_state {
 352         uint32_t nv04[ARRAY_SIZE(nv04_graph_ctx_regs)];
 353 };
 354
 355 static struct nouveau_channel *
 356 nv04_graph_channel(struct drm_device *dev)
 357 {
 358         struct drm_nouveau_private *dev_priv = dev->dev_private;
 359         int chid = dev_priv->engine.fifo.channels;
 360
 361         if (nv_rd32(dev, NV04_PGRAPH_CTX_CONTROL) & 0x00010000)
 362                 chid = nv_rd32(dev, NV04_PGRAPH_CTX_USER) >> 24;
 363
 364         if (chid >= dev_priv->engine.fifo.channels)
 365                 return NULL;
 366
 367         return dev_priv->channels.ptr[chid];
 368 }
 369
 370 static uint32_t *ctx_reg(struct graph_state *ctx, uint32_t reg)
 371 {
 372         int i;
 373
 374         for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++) {
 375                 if (nv04_graph_ctx_regs[i] == reg)
 376                         return &ctx->nv04[i];
 377         }
 378
 379         return NULL;
 380 }
 381
 382 static int
 383 nv04_graph_load_context(struct nouveau_channel *chan)
 384 {
 385         struct graph_state *pgraph_ctx = chan->engctx[NVOBJ_ENGINE_GR];
 386         struct drm_device *dev = chan->dev;
 387         uint32_t tmp;
 388         int i;
 389
 390         for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++)
 391                 nv_wr32(dev, nv04_graph_ctx_regs[i], pgraph_ctx->nv04[i]);
 392
 393         nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL, 0x10010100);
 394
 395         tmp  = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff;
 396         nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp | chan->id << 24);
 397
 398         tmp = nv_rd32(dev, NV04_PGRAPH_FFINTFC_ST2);
 399         nv_wr32(dev, NV04_PGRAPH_FFINTFC_ST2, tmp & 0x000fffff);
 400
 401         return 0;
 402 }
 403
 404 static int
 405 nv04_graph_unload_context(struct drm_device *dev)
 406 {
 407         struct drm_nouveau_private *dev_priv = dev->dev_private;
 408         struct nouveau_channel *chan = NULL;
 409         struct graph_state *ctx;
 410         uint32_t tmp;
 411         int i;
 412
 413         chan = nv04_graph_channel(dev);
 414         if (!chan)
 415                 return 0;
 416         ctx = chan->engctx[NVOBJ_ENGINE_GR];
 417
 418         for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++)
 419                 ctx->nv04[i] = nv_rd32(dev, nv04_graph_ctx_regs[i]);
 420
 421         nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL, 0x10000000);
 422         tmp  = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff;
 423         tmp |= (dev_priv->engine.fifo.channels - 1) << 24;
 424         nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp);
 425         return 0;
 426 }
 427
 428 static int
 429 nv04_graph_context_new(struct nouveau_channel *chan, int engine)
 430 {
 431         struct graph_state *pgraph_ctx;
 432         NV_DEBUG(chan->dev, "nv04_graph_context_create %d\n", chan->id);
 433
 434         pgraph_ctx = kzalloc(sizeof(*pgraph_ctx), GFP_KERNEL);
 435         if (pgraph_ctx == NULL)
 436                 return -ENOMEM;
 437
 438         *ctx_reg(pgraph_ctx, NV04_PGRAPH_DEBUG_3) = 0xfad4ff31;
 439
 440         chan->engctx[engine] = pgraph_ctx;
 441         return 0;
 442 }
 443
 444 static void
 445 nv04_graph_context_del(struct nouveau_channel *chan, int engine)
 446 {
 447         struct drm_device *dev = chan->dev;
 448         struct drm_nouveau_private *dev_priv = dev->dev_private;
 449         struct graph_state *pgraph_ctx = chan->engctx[engine];
 450         unsigned long flags;
 451
 452         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 453         nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
 454
 455         /* Unload the context if it's the currently active one */
 456         if (nv04_graph_channel(dev) == chan)
 457                 nv04_graph_unload_context(dev);
 458
 459         nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
 460         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 461
 462         /* Free the context resources */
 463         kfree(pgraph_ctx);
 464         chan->engctx[engine] = NULL;
 465 }
 466
 467 int
 468 nv04_graph_object_new(struct nouveau_channel *chan, int engine,
 469                       u32 handle, u16 class)
 470 {
 471         struct drm_device *dev = chan->dev;
 472         struct nouveau_gpuobj *obj = NULL;
 473         int ret;
 474
 475         ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
 476         if (ret)
 477                 return ret;
 478         obj->engine = 1;
 479         obj->class  = class;
 480
 481 #ifdef __BIG_ENDIAN
 482         nv_wo32(obj, 0x00, 0x00080000 | class);
 483 #else
 484         nv_wo32(obj, 0x00, class);
 485 #endif
 486         nv_wo32(obj, 0x04, 0x00000000);
 487         nv_wo32(obj, 0x08, 0x00000000);
 488         nv_wo32(obj, 0x0c, 0x00000000);
 489
 490         ret = nouveau_ramht_insert(chan, handle, obj);
 491         nouveau_gpuobj_ref(NULL, &obj);
 492         return ret;
 493 }
 494
 495 static int
 496 nv04_graph_init(struct drm_device *dev, int engine)
 497 {
 498         struct drm_nouveau_private *dev_priv = dev->dev_private;
 499         uint32_t tmp;
 500
 501         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
 502                         ~NV_PMC_ENABLE_PGRAPH);
 503         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
 504                          NV_PMC_ENABLE_PGRAPH);
 505
 506         /* Enable PGRAPH interrupts */
 507         nv_wr32(dev, NV03_PGRAPH_INTR, 0xFFFFFFFF);
 508         nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
 509
 510         nv_wr32(dev, NV04_PGRAPH_VALID1, 0);
 511         nv_wr32(dev, NV04_PGRAPH_VALID2, 0);
 512         /*nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x000001FF);
 513         nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/
 514         nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x1231c000);
 515         /*1231C000 blob, 001 haiku*/
 516         /*V_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);*/
 517         nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x72111100);
 518         /*0x72111100 blob , 01 haiku*/
 519         /*nv_wr32(dev, NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/
 520         nv_wr32(dev, NV04_PGRAPH_DEBUG_2, 0x11d5f071);
 521         /*haiku same*/
 522
 523         /*nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/
 524         nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xf0d4ff31);
 525         /*haiku and blob 10d4*/
 526
 527         nv_wr32(dev, NV04_PGRAPH_STATE        , 0xFFFFFFFF);
 528         nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL  , 0x10000100);
 529         tmp  = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff;
 530         tmp |= (dev_priv->engine.fifo.channels - 1) << 24;
 531         nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp);
 532
 533         /* These don't belong here, they're part of a per-channel context */
 534         nv_wr32(dev, NV04_PGRAPH_PATTERN_SHAPE, 0x00000000);
 535         nv_wr32(dev, NV04_PGRAPH_BETA_AND     , 0xFFFFFFFF);
 536
 537         return 0;
 538 }
 539
 540 static int
 541 nv04_graph_fini(struct drm_device *dev, int engine, bool suspend)
 542 {
 543         nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
 544         if (!nv_wait(dev, NV04_PGRAPH_STATUS, ~0, 0) && suspend) {
 545                 nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
 546                 return -EBUSY;
 547         }
 548         nv04_graph_unload_context(dev);
 549         nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0x00000000);
 550         return 0;
 551 }
 552
 553 /*
 554  * Software methods, why they are needed, and how they all work:
 555  *
 556  * NV04 and NV05 keep most of the state in PGRAPH context itself, but some
 557  * 2d engine settings are kept inside the grobjs themselves. The grobjs are
 558  * 3 words long on both. grobj format on NV04 is:
 559  *
 560  * word 0:
 561  *  - bits 0-7: class
 562  *  - bit 12: color key active
 563  *  - bit 13: clip rect active
 564  *  - bit 14: if set, destination surface is swizzled and taken from buffer 5
 565  *            [set by NV04_SWIZZLED_SURFACE], otherwise it's linear and taken
 566  *            from buffer 0 [set by NV04_CONTEXT_SURFACES_2D or
 567  *            NV03_CONTEXT_SURFACE_DST].
 568  *  - bits 15-17: 2d operation [aka patch config]
 569  *  - bit 24: patch valid [enables rendering using this object]
 570  *  - bit 25: surf3d valid [for tex_tri and multitex_tri only]
 571  * word 1:
 572  *  - bits 0-1: mono format
 573  *  - bits 8-13: color format
 574  *  - bits 16-31: DMA_NOTIFY instance
 575  * word 2:
 576  *  - bits 0-15: DMA_A instance
 577  *  - bits 16-31: DMA_B instance
 578  *
 579  * On NV05 it's:
 580  *
 581  * word 0:
 582  *  - bits 0-7: class
 583  *  - bit 12: color key active
 584  *  - bit 13: clip rect active
 585  *  - bit 14: if set, destination surface is swizzled and taken from buffer 5
 586  *            [set by NV04_SWIZZLED_SURFACE], otherwise it's linear and taken
 587  *            from buffer 0 [set by NV04_CONTEXT_SURFACES_2D or
 588  *            NV03_CONTEXT_SURFACE_DST].
 589  *  - bits 15-17: 2d operation [aka patch config]
 590  *  - bits 20-22: dither mode
 591  *  - bit 24: patch valid [enables rendering using this object]
 592  *  - bit 25: surface_dst/surface_color/surf2d/surf3d valid
 593  *  - bit 26: surface_src/surface_zeta valid
 594  *  - bit 27: pattern valid
 595  *  - bit 28: rop valid
 596  *  - bit 29: beta1 valid
 597  *  - bit 30: beta4 valid
 598  * word 1:
 599  *  - bits 0-1: mono format
 600  *  - bits 8-13: color format
 601  *  - bits 16-31: DMA_NOTIFY instance
 602  * word 2:
 603  *  - bits 0-15: DMA_A instance
 604  *  - bits 16-31: DMA_B instance
 605  *
 606  * NV05 will set/unset the relevant valid bits when you poke the relevant
 607  * object-binding methods with object of the proper type, or with the NULL
 608  * type. It'll only allow rendering using the grobj if all needed objects
 609  * are bound. The needed set of objects depends on selected operation: for
 610  * example rop object is needed by ROP_AND, but not by SRCCOPY_AND.
 611  *
 612  * NV04 doesn't have these methods implemented at all, and doesn't have the
 613  * relevant bits in grobj. Instead, it'll allow rendering whenever bit 24
 614  * is set. So we have to emulate them in software, internally keeping the
 615  * same bits as NV05 does. Since grobjs are aligned to 16 bytes on nv04,
 616  * but the last word isn't actually used for anything, we abuse it for this
 617  * purpose.
 618  *
 619  * Actually, NV05 can optionally check bit 24 too, but we disable this since
 620  * there's no use for it.
 621  *
 622  * For unknown reasons, NV04 implements surf3d binding in hardware as an
 623  * exception. Also for unknown reasons, NV04 doesn't implement the clipping
 624  * methods on the surf3d object, so we have to emulate them too.
 625  */
 626
 627 static void
 628 nv04_graph_set_ctx1(struct nouveau_channel *chan, u32 mask, u32 value)
 629 {
 630         struct drm_device *dev = chan->dev;
 631         u32 instance = (nv_rd32(dev, NV04_PGRAPH_CTX_SWITCH4) & 0xffff) << 4;
 632         int subc = (nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7;
 633         u32 tmp;
 634
 635         tmp  = nv_ri32(dev, instance);
 636         tmp &= ~mask;
 637         tmp |= value;
 638
 639         nv_wi32(dev, instance, tmp);
 640         nv_wr32(dev, NV04_PGRAPH_CTX_SWITCH1, tmp);
 641         nv_wr32(dev, NV04_PGRAPH_CTX_CACHE1 + (subc<<2), tmp);
 642 }
 643
 644 static void
 645 nv04_graph_set_ctx_val(struct nouveau_channel *chan, u32 mask, u32 value)
 646 {
 647         struct drm_device *dev = chan->dev;
 648         u32 instance = (nv_rd32(dev, NV04_PGRAPH_CTX_SWITCH4) & 0xffff) << 4;
 649         u32 tmp, ctx1;
 650         int class, op, valid = 1;
 651
 652         ctx1 = nv_ri32(dev, instance);
 653         class = ctx1 & 0xff;
 654         op = (ctx1 >> 15) & 7;
 655         tmp  = nv_ri32(dev, instance + 0xc);
 656         tmp &= ~mask;
 657         tmp |= value;
 658         nv_wi32(dev, instance + 0xc, tmp);
 659
 660         /* check for valid surf2d/surf_dst/surf_color */
 661         if (!(tmp & 0x02000000))
 662                 valid = 0;
 663         /* check for valid surf_src/surf_zeta */
 664         if ((class == 0x1f || class == 0x48) && !(tmp & 0x04000000))
 665                 valid = 0;
 666
 667         switch (op) {
 668         /* SRCCOPY_AND, SRCCOPY: no extra objects required */
 669         case 0:
 670         case 3:
 671                 break;
 672         /* ROP_AND: requires pattern and rop */
 673         case 1:
 674                 if (!(tmp & 0x18000000))
 675                         valid = 0;
 676                 break;
 677         /* BLEND_AND: requires beta1 */
 678         case 2:
 679                 if (!(tmp & 0x20000000))
 680                         valid = 0;
 681                 break;
 682         /* SRCCOPY_PREMULT, BLEND_PREMULT: beta4 required */
 683         case 4:
 684         case 5:
 685                 if (!(tmp & 0x40000000))
 686                         valid = 0;
 687                 break;
 688         }
 689
 690         nv04_graph_set_ctx1(chan, 0x01000000, valid << 24);
 691 }
 692
 693 static int
 694 nv04_graph_mthd_set_operation(struct nouveau_channel *chan,
 695                               u32 class, u32 mthd, u32 data)
 696 {
 697         if (data > 5)
 698                 return 1;
 699         /* Old versions of the objects only accept first three operations. */
 700         if (data > 2 && class < 0x40)
 701                 return 1;
 702         nv04_graph_set_ctx1(chan, 0x00038000, data << 15);
 703         /* changing operation changes set of objects needed for validation */
 704         nv04_graph_set_ctx_val(chan, 0, 0);
 705         return 0;
 706 }
 707
 708 static int
 709 nv04_graph_mthd_surf3d_clip_h(struct nouveau_channel *chan,
 710                               u32 class, u32 mthd, u32 data)
 711 {
 712         uint32_t min = data & 0xffff, max;
 713         uint32_t w = data >> 16;
 714         if (min & 0x8000)
 715                 /* too large */
 716                 return 1;
 717         if (w & 0x8000)
 718                 /* yes, it accepts negative for some reason. */
 719                 w |= 0xffff0000;
 720         max = min + w;
 721         max &= 0x3ffff;
 722         nv_wr32(chan->dev, 0x40053c, min);
 723         nv_wr32(chan->dev, 0x400544, max);
 724         return 0;
 725 }
 726
 727 static int
 728 nv04_graph_mthd_surf3d_clip_v(struct nouveau_channel *chan,
 729                               u32 class, u32 mthd, u32 data)
 730 {
 731         uint32_t min = data & 0xffff, max;
 732         uint32_t w = data >> 16;
 733         if (min & 0x8000)
 734                 /* too large */
 735                 return 1;
 736         if (w & 0x8000)
 737                 /* yes, it accepts negative for some reason. */
 738                 w |= 0xffff0000;
 739         max = min + w;
 740         max &= 0x3ffff;
 741         nv_wr32(chan->dev, 0x400540, min);
 742         nv_wr32(chan->dev, 0x400548, max);
 743         return 0;
 744 }
 745
 746 static int
 747 nv04_graph_mthd_bind_surf2d(struct nouveau_channel *chan,
 748                             u32 class, u32 mthd, u32 data)
 749 {
 750         switch (nv_ri32(chan->dev, data << 4) & 0xff) {
 751         case 0x30:
 752                 nv04_graph_set_ctx1(chan, 0x00004000, 0);
 753                 nv04_graph_set_ctx_val(chan, 0x02000000, 0);
 754                 return 0;
 755         case 0x42:
 756                 nv04_graph_set_ctx1(chan, 0x00004000, 0);
 757                 nv04_graph_set_ctx_val(chan, 0x02000000, 0x02000000);
 758                 return 0;
 759         }
 760         return 1;
 761 }
 762
 763 static int
 764 nv04_graph_mthd_bind_surf2d_swzsurf(struct nouveau_channel *chan,
 765                                     u32 class, u32 mthd, u32 data)
 766 {
 767         switch (nv_ri32(chan->dev, data << 4) & 0xff) {
 768         case 0x30:
 769                 nv04_graph_set_ctx1(chan, 0x00004000, 0);
 770                 nv04_graph_set_ctx_val(chan, 0x02000000, 0);
 771                 return 0;
 772         case 0x42:
 773                 nv04_graph_set_ctx1(chan, 0x00004000, 0);
 774                 nv04_graph_set_ctx_val(chan, 0x02000000, 0x02000000);
 775                 return 0;
 776         case 0x52:
 777                 nv04_graph_set_ctx1(chan, 0x00004000, 0x00004000);
 778                 nv04_graph_set_ctx_val(chan, 0x02000000, 0x02000000);
 779                 return 0;
 780         }
 781         return 1;
 782 }
 783
 784 static int
 785 nv04_graph_mthd_bind_nv01_patt(struct nouveau_channel *chan,
 786                                u32 class, u32 mthd, u32 data)
 787 {
 788         switch (nv_ri32(chan->dev, data << 4) & 0xff) {
 789         case 0x30:
 790                 nv04_graph_set_ctx_val(chan, 0x08000000, 0);
 791                 return 0;
 792         case 0x18:
 793                 nv04_graph_set_ctx_val(chan, 0x08000000, 0x08000000);
 794                 return 0;
 795         }
 796         return 1;
 797 }
 798
 799 static int
 800 nv04_graph_mthd_bind_nv04_patt(struct nouveau_channel *chan,
 801                                u32 class, u32 mthd, u32 data)
 802 {
 803         switch (nv_ri32(chan->dev, data << 4) & 0xff) {
 804         case 0x30:
 805                 nv04_graph_set_ctx_val(chan, 0x08000000, 0);
 806                 return 0;
 807         case 0x44:
 808                 nv04_graph_set_ctx_val(chan, 0x08000000, 0x08000000);
 809                 return 0;
 810         }
 811         return 1;
 812 }
 813
 814 static int
 815 nv04_graph_mthd_bind_rop(struct nouveau_channel *chan,
 816                          u32 class, u32 mthd, u32 data)
 817 {
 818         switch (nv_ri32(chan->dev, data << 4) & 0xff) {
 819         case 0x30:
 820                 nv04_graph_set_ctx_val(chan, 0x10000000, 0);
 821                 return 0;
 822         case 0x43:
 823                 nv04_graph_set_ctx_val(chan, 0x10000000, 0x10000000);
 824                 return 0;
 825         }
 826         return 1;
 827 }
 828
 829 static int
 830 nv04_graph_mthd_bind_beta1(struct nouveau_channel *chan,
 831                            u32 class, u32 mthd, u32 data)
 832 {
 833         switch (nv_ri32(chan->dev, data << 4) & 0xff) {
 834         case 0x30:
 835                 nv04_graph_set_ctx_val(chan, 0x20000000, 0);
 836                 return 0;
 837         case 0x12:
 838                 nv04_graph_set_ctx_val(chan, 0x20000000, 0x20000000);
 839                 return 0;
 840         }
 841         return 1;
 842 }
 843
 844 static int
 845 nv04_graph_mthd_bind_beta4(struct nouveau_channel *chan,
 846                            u32 class, u32 mthd, u32 data)
 847 {
 848         switch (nv_ri32(chan->dev, data << 4) & 0xff) {
 849         case 0x30:
 850                 nv04_graph_set_ctx_val(chan, 0x40000000, 0);
 851                 return 0;
 852         case 0x72:
 853                 nv04_graph_set_ctx_val(chan, 0x40000000, 0x40000000);
 854                 return 0;
 855         }
 856         return 1;
 857 }
 858
 859 static int
 860 nv04_graph_mthd_bind_surf_dst(struct nouveau_channel *chan,
 861                               u32 class, u32 mthd, u32 data)
 862 {
 863         switch (nv_ri32(chan->dev, data << 4) & 0xff) {
 864         case 0x30:
 865                 nv04_graph_set_ctx_val(chan, 0x02000000, 0);
 866                 return 0;
 867         case 0x58:
 868                 nv04_graph_set_ctx_val(chan, 0x02000000, 0x02000000);
 869                 return 0;
 870         }
 871         return 1;
 872 }
 873
 874 static int
 875 nv04_graph_mthd_bind_surf_src(struct nouveau_channel *chan,
 876                               u32 class, u32 mthd, u32 data)
 877 {
 878         switch (nv_ri32(chan->dev, data << 4) & 0xff) {
 879         case 0x30:
 880                 nv04_graph_set_ctx_val(chan, 0x04000000, 0);
 881                 return 0;
 882         case 0x59:
 883                 nv04_graph_set_ctx_val(chan, 0x04000000, 0x04000000);
 884                 return 0;
 885         }
 886         return 1;
 887 }
 888
 889 static int
 890 nv04_graph_mthd_bind_surf_color(struct nouveau_channel *chan,
 891                                 u32 class, u32 mthd, u32 data)
 892 {
 893         switch (nv_ri32(chan->dev, data << 4) & 0xff) {
 894         case 0x30:
 895                 nv04_graph_set_ctx_val(chan, 0x02000000, 0);
 896                 return 0;
 897         case 0x5a:
 898                 nv04_graph_set_ctx_val(chan, 0x02000000, 0x02000000);
 899                 return 0;
 900         }
 901         return 1;
 902 }
 903
 904 static int
 905 nv04_graph_mthd_bind_surf_zeta(struct nouveau_channel *chan,
 906                                u32 class, u32 mthd, u32 data)
 907 {
 908         switch (nv_ri32(chan->dev, data << 4) & 0xff) {
 909         case 0x30:
 910                 nv04_graph_set_ctx_val(chan, 0x04000000, 0);
 911                 return 0;
 912         case 0x5b:
 913                 nv04_graph_set_ctx_val(chan, 0x04000000, 0x04000000);
 914                 return 0;
 915         }
 916         return 1;
 917 }
 918
 919 static int
 920 nv04_graph_mthd_bind_clip(struct nouveau_channel *chan,
 921                           u32 class, u32 mthd, u32 data)
 922 {
 923         switch (nv_ri32(chan->dev, data << 4) & 0xff) {
 924         case 0x30:
 925                 nv04_graph_set_ctx1(chan, 0x2000, 0);
 926                 return 0;
 927         case 0x19:
 928                 nv04_graph_set_ctx1(chan, 0x2000, 0x2000);
 929                 return 0;
 930         }
 931         return 1;
 932 }
 933
 934 static int
 935 nv04_graph_mthd_bind_chroma(struct nouveau_channel *chan,
 936                             u32 class, u32 mthd, u32 data)
 937 {
 938         switch (nv_ri32(chan->dev, data << 4) & 0xff) {
 939         case 0x30:
 940                 nv04_graph_set_ctx1(chan, 0x1000, 0);
 941                 return 0;
 942         /* Yes, for some reason even the old versions of objects
 943          * accept 0x57 and not 0x17. Consistency be damned.
 944          */
 945         case 0x57:
 946                 nv04_graph_set_ctx1(chan, 0x1000, 0x1000);
 947                 return 0;
 948         }
 949         return 1;
 950 }
 951
 952 static struct nouveau_bitfield nv04_graph_intr[] = {
 953         { NV_PGRAPH_INTR_NOTIFY, "NOTIFY" },
 954         {}
 955 };
 956
 957 static struct nouveau_bitfield nv04_graph_nstatus[] = {
 958         { NV04_PGRAPH_NSTATUS_STATE_IN_USE,       "STATE_IN_USE" },
 959         { NV04_PGRAPH_NSTATUS_INVALID_STATE,      "INVALID_STATE" },
 960         { NV04_PGRAPH_NSTATUS_BAD_ARGUMENT,       "BAD_ARGUMENT" },
 961         { NV04_PGRAPH_NSTATUS_PROTECTION_FAULT,   "PROTECTION_FAULT" },
 962         {}
 963 };
 964
 965 struct nouveau_bitfield nv04_graph_nsource[] = {
 966         { NV03_PGRAPH_NSOURCE_NOTIFICATION,       "NOTIFICATION" },
 967         { NV03_PGRAPH_NSOURCE_DATA_ERROR,         "DATA_ERROR" },
 968         { NV03_PGRAPH_NSOURCE_PROTECTION_ERROR,   "PROTECTION_ERROR" },
 969         { NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION,    "RANGE_EXCEPTION" },
 970         { NV03_PGRAPH_NSOURCE_LIMIT_COLOR,        "LIMIT_COLOR" },
 971         { NV03_PGRAPH_NSOURCE_LIMIT_ZETA,         "LIMIT_ZETA" },
 972         { NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD,       "ILLEGAL_MTHD" },
 973         { NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION,   "DMA_R_PROTECTION" },
 974         { NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION,   "DMA_W_PROTECTION" },
 975         { NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION,   "FORMAT_EXCEPTION" },
 976         { NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION,    "PATCH_EXCEPTION" },
 977         { NV03_PGRAPH_NSOURCE_STATE_INVALID,      "STATE_INVALID" },
 978         { NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY,      "DOUBLE_NOTIFY" },
 979         { NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE,      "NOTIFY_IN_USE" },
 980         { NV03_PGRAPH_NSOURCE_METHOD_CNT,         "METHOD_CNT" },
 981         { NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION,   "BFR_NOTIFICATION" },
 982         { NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" },
 983         { NV03_PGRAPH_NSOURCE_DMA_WIDTH_A,        "DMA_WIDTH_A" },
 984         { NV03_PGRAPH_NSOURCE_DMA_WIDTH_B,        "DMA_WIDTH_B" },
 985         {}
 986 };
 987
 988 static void
 989 nv04_graph_context_switch(struct drm_device *dev)
 990 {
 991         struct drm_nouveau_private *dev_priv = dev->dev_private;
 992         struct nouveau_channel *chan = NULL;
 993         int chid;
 994
 995         nouveau_wait_for_idle(dev);
 996
 997         /* If previous context is valid, we need to save it */
 998         nv04_graph_unload_context(dev);
 999
1000         /* Load context for next channel */
1001         chid = nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) &
1002                             NV03_PFIFO_CACHE1_PUSH1_CHID_MASK;
1003         chan = dev_priv->channels.ptr[chid];
1004         if (chan)
1005                 nv04_graph_load_context(chan);
1006 }
1007
1008 static void
1009 nv04_graph_isr(struct drm_device *dev)
1010 {
1011         u32 stat;
1012
1013         while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
1014                 u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
1015                 u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
1016                 u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
1017                 u32 chid = (addr & 0x0f000000) >> 24;
1018                 u32 subc = (addr & 0x0000e000) >> 13;
1019                 u32 mthd = (addr & 0x00001ffc);
1020                 u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
1021                 u32 class = nv_rd32(dev, 0x400180 + subc * 4) & 0xff;
1022                 u32 show = stat;
1023
1024                 if (stat & NV_PGRAPH_INTR_NOTIFY) {
1025                         if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
1026                                 if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
1027                                         show &= ~NV_PGRAPH_INTR_NOTIFY;
1028                         }
1029                 }
1030
1031                 if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
1032                         nv_wr32(dev, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
1033                         stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
1034                         show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
1035                         nv04_graph_context_switch(dev);
1036                 }
1037
1038                 nv_wr32(dev, NV03_PGRAPH_INTR, stat);
1039                 nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
1040
1041                 if (show && nouveau_ratelimit()) {
1042                         NV_INFO(dev, "PGRAPH -");
1043                         nouveau_bitfield_print(nv04_graph_intr, show);
1044                         printk(" nsource:");
1045                         nouveau_bitfield_print(nv04_graph_nsource, nsource);
1046                         printk(" nstatus:");
1047                         nouveau_bitfield_print(nv04_graph_nstatus, nstatus);
1048                         printk("\n");
1049                         NV_INFO(dev, "PGRAPH - ch %d/%d class 0x%04x "
1050                                      "mthd 0x%04x data 0x%08x\n",
1051                                 chid, subc, class, mthd, data);
1052                 }
1053         }
1054 }
1055
1056 static void
1057 nv04_graph_destroy(struct drm_device *dev, int engine)
1058 {
1059         struct nv04_graph_engine *pgraph = nv_engine(dev, engine);
1060
1061         nouveau_irq_unregister(dev, 12);
1062
1063         NVOBJ_ENGINE_DEL(dev, GR);
1064         kfree(pgraph);
1065 }
1066
1067 int
1068 nv04_graph_create(struct drm_device *dev)
1069 {
1070         struct nv04_graph_engine *pgraph;
1071
1072         pgraph = kzalloc(sizeof(*pgraph), GFP_KERNEL);
1073         if (!pgraph)
1074                 return -ENOMEM;
1075
1076         pgraph->base.destroy = nv04_graph_destroy;
1077         pgraph->base.init = nv04_graph_init;
1078         pgraph->base.fini = nv04_graph_fini;
1079         pgraph->base.context_new = nv04_graph_context_new;
1080         pgraph->base.context_del = nv04_graph_context_del;
1081         pgraph->base.object_new = nv04_graph_object_new;
1082
1083         NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
1084         nouveau_irq_register(dev, 12, nv04_graph_isr);
1085
1086         /* dvd subpicture */
1087         NVOBJ_CLASS(dev, 0x0038, GR);
1088
1089         /* m2mf */
1090         NVOBJ_CLASS(dev, 0x0039, GR);
1091
1092         /* nv03 gdirect */
1093         NVOBJ_CLASS(dev, 0x004b, GR);
1094         NVOBJ_MTHD (dev, 0x004b, 0x0184, nv04_graph_mthd_bind_nv01_patt);
1095         NVOBJ_MTHD (dev, 0x004b, 0x0188, nv04_graph_mthd_bind_rop);
1096         NVOBJ_MTHD (dev, 0x004b, 0x018c, nv04_graph_mthd_bind_beta1);
1097         NVOBJ_MTHD (dev, 0x004b, 0x0190, nv04_graph_mthd_bind_surf_dst);
1098         NVOBJ_MTHD (dev, 0x004b, 0x02fc, nv04_graph_mthd_set_operation);
1099
1100         /* nv04 gdirect */
1101         NVOBJ_CLASS(dev, 0x004a, GR);
1102         NVOBJ_MTHD (dev, 0x004a, 0x0188, nv04_graph_mthd_bind_nv04_patt);
1103         NVOBJ_MTHD (dev, 0x004a, 0x018c, nv04_graph_mthd_bind_rop);
1104         NVOBJ_MTHD (dev, 0x004a, 0x0190, nv04_graph_mthd_bind_beta1);
1105         NVOBJ_MTHD (dev, 0x004a, 0x0194, nv04_graph_mthd_bind_beta4);
1106         NVOBJ_MTHD (dev, 0x004a, 0x0198, nv04_graph_mthd_bind_surf2d);
1107         NVOBJ_MTHD (dev, 0x004a, 0x02fc, nv04_graph_mthd_set_operation);
1108
1109         /* nv01 imageblit */
1110         NVOBJ_CLASS(dev, 0x001f, GR);
1111         NVOBJ_MTHD (dev, 0x001f, 0x0184, nv04_graph_mthd_bind_chroma);
1112         NVOBJ_MTHD (dev, 0x001f, 0x0188, nv04_graph_mthd_bind_clip);
1113         NVOBJ_MTHD (dev, 0x001f, 0x018c, nv04_graph_mthd_bind_nv01_patt);
1114         NVOBJ_MTHD (dev, 0x001f, 0x0190, nv04_graph_mthd_bind_rop);
1115         NVOBJ_MTHD (dev, 0x001f, 0x0194, nv04_graph_mthd_bind_beta1);
1116         NVOBJ_MTHD (dev, 0x001f, 0x0198, nv04_graph_mthd_bind_surf_dst);
1117         NVOBJ_MTHD (dev, 0x001f, 0x019c, nv04_graph_mthd_bind_surf_src);
1118         NVOBJ_MTHD (dev, 0x001f, 0x02fc, nv04_graph_mthd_set_operation);
1119
1120         /* nv04 imageblit */
1121         NVOBJ_CLASS(dev, 0x005f, GR);
1122         NVOBJ_MTHD (dev, 0x005f, 0x0184, nv04_graph_mthd_bind_chroma);
1123         NVOBJ_MTHD (dev, 0x005f, 0x0188, nv04_graph_mthd_bind_clip);
1124         NVOBJ_MTHD (dev, 0x005f, 0x018c, nv04_graph_mthd_bind_nv04_patt);
1125         NVOBJ_MTHD (dev, 0x005f, 0x0190, nv04_graph_mthd_bind_rop);
1126         NVOBJ_MTHD (dev, 0x005f, 0x0194, nv04_graph_mthd_bind_beta1);
1127         NVOBJ_MTHD (dev, 0x005f, 0x0198, nv04_graph_mthd_bind_beta4);
1128         NVOBJ_MTHD (dev, 0x005f, 0x019c, nv04_graph_mthd_bind_surf2d);
1129         NVOBJ_MTHD (dev, 0x005f, 0x02fc, nv04_graph_mthd_set_operation);
1130
1131         /* nv04 iifc */
1132         NVOBJ_CLASS(dev, 0x0060, GR);
1133         NVOBJ_MTHD (dev, 0x0060, 0x0188, nv04_graph_mthd_bind_chroma);
1134         NVOBJ_MTHD (dev, 0x0060, 0x018c, nv04_graph_mthd_bind_clip);
1135         NVOBJ_MTHD (dev, 0x0060, 0x0190, nv04_graph_mthd_bind_nv04_patt);
1136         NVOBJ_MTHD (dev, 0x0060, 0x0194, nv04_graph_mthd_bind_rop);
1137         NVOBJ_MTHD (dev, 0x0060, 0x0198, nv04_graph_mthd_bind_beta1);
1138         NVOBJ_MTHD (dev, 0x0060, 0x019c, nv04_graph_mthd_bind_beta4);
1139         NVOBJ_MTHD (dev, 0x0060, 0x01a0, nv04_graph_mthd_bind_surf2d_swzsurf);
1140         NVOBJ_MTHD (dev, 0x0060, 0x03e4, nv04_graph_mthd_set_operation);
1141
1142         /* nv05 iifc */
1143         NVOBJ_CLASS(dev, 0x0064, GR);
1144
1145         /* nv01 ifc */
1146         NVOBJ_CLASS(dev, 0x0021, GR);
1147         NVOBJ_MTHD (dev, 0x0021, 0x0184, nv04_graph_mthd_bind_chroma);
1148         NVOBJ_MTHD (dev, 0x0021, 0x0188, nv04_graph_mthd_bind_clip);
1149         NVOBJ_MTHD (dev, 0x0021, 0x018c, nv04_graph_mthd_bind_nv01_patt);
1150         NVOBJ_MTHD (dev, 0x0021, 0x0190, nv04_graph_mthd_bind_rop);
1151         NVOBJ_MTHD (dev, 0x0021, 0x0194, nv04_graph_mthd_bind_beta1);
1152         NVOBJ_MTHD (dev, 0x0021, 0x0198, nv04_graph_mthd_bind_surf_dst);
1153         NVOBJ_MTHD (dev, 0x0021, 0x02fc, nv04_graph_mthd_set_operation);
1154
1155         /* nv04 ifc */
1156         NVOBJ_CLASS(dev, 0x0061, GR);
1157         NVOBJ_MTHD (dev, 0x0061, 0x0184, nv04_graph_mthd_bind_chroma);
1158         NVOBJ_MTHD (dev, 0x0061, 0x0188, nv04_graph_mthd_bind_clip);
1159         NVOBJ_MTHD (dev, 0x0061, 0x018c, nv04_graph_mthd_bind_nv04_patt);
1160         NVOBJ_MTHD (dev, 0x0061, 0x0190, nv04_graph_mthd_bind_rop);
1161         NVOBJ_MTHD (dev, 0x0061, 0x0194, nv04_graph_mthd_bind_beta1);
1162         NVOBJ_MTHD (dev, 0x0061, 0x0198, nv04_graph_mthd_bind_beta4);
1163         NVOBJ_MTHD (dev, 0x0061, 0x019c, nv04_graph_mthd_bind_surf2d);
1164         NVOBJ_MTHD (dev, 0x0061, 0x02fc, nv04_graph_mthd_set_operation);
1165
1166         /* nv05 ifc */
1167         NVOBJ_CLASS(dev, 0x0065, GR);
1168
1169         /* nv03 sifc */
1170         NVOBJ_CLASS(dev, 0x0036, GR);
1171         NVOBJ_MTHD (dev, 0x0036, 0x0184, nv04_graph_mthd_bind_chroma);
1172         NVOBJ_MTHD (dev, 0x0036, 0x0188, nv04_graph_mthd_bind_nv01_patt);
1173         NVOBJ_MTHD (dev, 0x0036, 0x018c, nv04_graph_mthd_bind_rop);
1174         NVOBJ_MTHD (dev, 0x0036, 0x0190, nv04_graph_mthd_bind_beta1);
1175         NVOBJ_MTHD (dev, 0x0036, 0x0194, nv04_graph_mthd_bind_surf_dst);
1176         NVOBJ_MTHD (dev, 0x0036, 0x02fc, nv04_graph_mthd_set_operation);
1177
1178         /* nv04 sifc */
1179         NVOBJ_CLASS(dev, 0x0076, GR);
1180         NVOBJ_MTHD (dev, 0x0076, 0x0184, nv04_graph_mthd_bind_chroma);
1181         NVOBJ_MTHD (dev, 0x0076, 0x0188, nv04_graph_mthd_bind_nv04_patt);
1182         NVOBJ_MTHD (dev, 0x0076, 0x018c, nv04_graph_mthd_bind_rop);
1183         NVOBJ_MTHD (dev, 0x0076, 0x0190, nv04_graph_mthd_bind_beta1);
1184         NVOBJ_MTHD (dev, 0x0076, 0x0194, nv04_graph_mthd_bind_beta4);
1185         NVOBJ_MTHD (dev, 0x0076, 0x0198, nv04_graph_mthd_bind_surf2d);
1186         NVOBJ_MTHD (dev, 0x0076, 0x02fc, nv04_graph_mthd_set_operation);
1187
1188         /* nv05 sifc */
1189         NVOBJ_CLASS(dev, 0x0066, GR);
1190
1191         /* nv03 sifm */
1192         NVOBJ_CLASS(dev, 0x0037, GR);
1193         NVOBJ_MTHD (dev, 0x0037, 0x0188, nv04_graph_mthd_bind_nv01_patt);
1194         NVOBJ_MTHD (dev, 0x0037, 0x018c, nv04_graph_mthd_bind_rop);
1195         NVOBJ_MTHD (dev, 0x0037, 0x0190, nv04_graph_mthd_bind_beta1);
1196         NVOBJ_MTHD (dev, 0x0037, 0x0194, nv04_graph_mthd_bind_surf_dst);
1197         NVOBJ_MTHD (dev, 0x0037, 0x0304, nv04_graph_mthd_set_operation);
1198
1199         /* nv04 sifm */
1200         NVOBJ_CLASS(dev, 0x0077, GR);
1201         NVOBJ_MTHD (dev, 0x0077, 0x0188, nv04_graph_mthd_bind_nv04_patt);
1202         NVOBJ_MTHD (dev, 0x0077, 0x018c, nv04_graph_mthd_bind_rop);
1203         NVOBJ_MTHD (dev, 0x0077, 0x0190, nv04_graph_mthd_bind_beta1);
1204         NVOBJ_MTHD (dev, 0x0077, 0x0194, nv04_graph_mthd_bind_beta4);
1205         NVOBJ_MTHD (dev, 0x0077, 0x0198, nv04_graph_mthd_bind_surf2d_swzsurf);
1206         NVOBJ_MTHD (dev, 0x0077, 0x0304, nv04_graph_mthd_set_operation);
1207
1208         /* null */
1209         NVOBJ_CLASS(dev, 0x0030, GR);
1210
1211         /* surf2d */
1212         NVOBJ_CLASS(dev, 0x0042, GR);
1213
1214         /* rop */
1215         NVOBJ_CLASS(dev, 0x0043, GR);
1216
1217         /* beta1 */
1218         NVOBJ_CLASS(dev, 0x0012, GR);
1219
1220         /* beta4 */
1221         NVOBJ_CLASS(dev, 0x0072, GR);
1222
1223         /* cliprect */
1224         NVOBJ_CLASS(dev, 0x0019, GR);
1225
1226         /* nv01 pattern */
1227         NVOBJ_CLASS(dev, 0x0018, GR);
1228
1229         /* nv04 pattern */
1230         NVOBJ_CLASS(dev, 0x0044, GR);
1231
1232         /* swzsurf */
1233         NVOBJ_CLASS(dev, 0x0052, GR);
1234
1235         /* surf3d */
1236         NVOBJ_CLASS(dev, 0x0053, GR);
1237         NVOBJ_MTHD (dev, 0x0053, 0x02f8, nv04_graph_mthd_surf3d_clip_h);
1238         NVOBJ_MTHD (dev, 0x0053, 0x02fc, nv04_graph_mthd_surf3d_clip_v);
1239
1240         /* nv03 tex_tri */
1241         NVOBJ_CLASS(dev, 0x0048, GR);
1242         NVOBJ_MTHD (dev, 0x0048, 0x0188, nv04_graph_mthd_bind_clip);
1243         NVOBJ_MTHD (dev, 0x0048, 0x018c, nv04_graph_mthd_bind_surf_color);
1244         NVOBJ_MTHD (dev, 0x0048, 0x0190, nv04_graph_mthd_bind_surf_zeta);
1245
1246         /* tex_tri */
1247         NVOBJ_CLASS(dev, 0x0054, GR);
1248
1249         /* multitex_tri */
1250         NVOBJ_CLASS(dev, 0x0055, GR);
1251
1252         /* nv01 chroma */
1253         NVOBJ_CLASS(dev, 0x0017, GR);
1254
1255         /* nv04 chroma */
1256         NVOBJ_CLASS(dev, 0x0057, GR);
1257
1258         /* surf_dst */
1259         NVOBJ_CLASS(dev, 0x0058, GR);
1260
1261         /* surf_src */
1262         NVOBJ_CLASS(dev, 0x0059, GR);
1263
1264         /* surf_color */
1265         NVOBJ_CLASS(dev, 0x005a, GR);
1266
1267         /* surf_zeta */
1268         NVOBJ_CLASS(dev, 0x005b, GR);
1269
1270         /* nv01 line */
1271         NVOBJ_CLASS(dev, 0x001c, GR);
1272         NVOBJ_MTHD (dev, 0x001c, 0x0184, nv04_graph_mthd_bind_clip);
1273         NVOBJ_MTHD (dev, 0x001c, 0x0188, nv04_graph_mthd_bind_nv01_patt);
1274         NVOBJ_MTHD (dev, 0x001c, 0x018c, nv04_graph_mthd_bind_rop);
1275         NVOBJ_MTHD (dev, 0x001c, 0x0190, nv04_graph_mthd_bind_beta1);
1276         NVOBJ_MTHD (dev, 0x001c, 0x0194, nv04_graph_mthd_bind_surf_dst);
1277         NVOBJ_MTHD (dev, 0x001c, 0x02fc, nv04_graph_mthd_set_operation);
1278
1279         /* nv04 line */
1280         NVOBJ_CLASS(dev, 0x005c, GR);
1281         NVOBJ_MTHD (dev, 0x005c, 0x0184, nv04_graph_mthd_bind_clip);
1282         NVOBJ_MTHD (dev, 0x005c, 0x0188, nv04_graph_mthd_bind_nv04_patt);
1283         NVOBJ_MTHD (dev, 0x005c, 0x018c, nv04_graph_mthd_bind_rop);
1284         NVOBJ_MTHD (dev, 0x005c, 0x0190, nv04_graph_mthd_bind_beta1);
1285         NVOBJ_MTHD (dev, 0x005c, 0x0194, nv04_graph_mthd_bind_beta4);
1286         NVOBJ_MTHD (dev, 0x005c, 0x0198, nv04_graph_mthd_bind_surf2d);
1287         NVOBJ_MTHD (dev, 0x005c, 0x02fc, nv04_graph_mthd_set_operation);
1288
1289         /* nv01 tri */
1290         NVOBJ_CLASS(dev, 0x001d, GR);
1291         NVOBJ_MTHD (dev, 0x001d, 0x0184, nv04_graph_mthd_bind_clip);
1292         NVOBJ_MTHD (dev, 0x001d, 0x0188, nv04_graph_mthd_bind_nv01_patt);
1293         NVOBJ_MTHD (dev, 0x001d, 0x018c, nv04_graph_mthd_bind_rop);
1294         NVOBJ_MTHD (dev, 0x001d, 0x0190, nv04_graph_mthd_bind_beta1);
1295         NVOBJ_MTHD (dev, 0x001d, 0x0194, nv04_graph_mthd_bind_surf_dst);
1296         NVOBJ_MTHD (dev, 0x001d, 0x02fc, nv04_graph_mthd_set_operation);
1297
1298         /* nv04 tri */
1299         NVOBJ_CLASS(dev, 0x005d, GR);
1300         NVOBJ_MTHD (dev, 0x005d, 0x0184, nv04_graph_mthd_bind_clip);
1301         NVOBJ_MTHD (dev, 0x005d, 0x0188, nv04_graph_mthd_bind_nv04_patt);
1302         NVOBJ_MTHD (dev, 0x005d, 0x018c, nv04_graph_mthd_bind_rop);
1303         NVOBJ_MTHD (dev, 0x005d, 0x0190, nv04_graph_mthd_bind_beta1);
1304         NVOBJ_MTHD (dev, 0x005d, 0x0194, nv04_graph_mthd_bind_beta4);
1305         NVOBJ_MTHD (dev, 0x005d, 0x0198, nv04_graph_mthd_bind_surf2d);
1306         NVOBJ_MTHD (dev, 0x005d, 0x02fc, nv04_graph_mthd_set_operation);
1307
1308         /* nv01 rect */
1309         NVOBJ_CLASS(dev, 0x001e, GR);
1310         NVOBJ_MTHD (dev, 0x001e, 0x0184, nv04_graph_mthd_bind_clip);
1311         NVOBJ_MTHD (dev, 0x001e, 0x0188, nv04_graph_mthd_bind_nv01_patt);
1312         NVOBJ_MTHD (dev, 0x001e, 0x018c, nv04_graph_mthd_bind_rop);
1313         NVOBJ_MTHD (dev, 0x001e, 0x0190, nv04_graph_mthd_bind_beta1);
1314         NVOBJ_MTHD (dev, 0x001e, 0x0194, nv04_graph_mthd_bind_surf_dst);
1315         NVOBJ_MTHD (dev, 0x001e, 0x02fc, nv04_graph_mthd_set_operation);
1316
1317         /* nv04 rect */
1318         NVOBJ_CLASS(dev, 0x005e, GR);
1319         NVOBJ_MTHD (dev, 0x005e, 0x0184, nv04_graph_mthd_bind_clip);
1320         NVOBJ_MTHD (dev, 0x005e, 0x0188, nv04_graph_mthd_bind_nv04_patt);
1321         NVOBJ_MTHD (dev, 0x005e, 0x018c, nv04_graph_mthd_bind_rop);
1322         NVOBJ_MTHD (dev, 0x005e, 0x0190, nv04_graph_mthd_bind_beta1);
1323         NVOBJ_MTHD (dev, 0x005e, 0x0194, nv04_graph_mthd_bind_beta4);
1324         NVOBJ_MTHD (dev, 0x005e, 0x0198, nv04_graph_mthd_bind_surf2d);
1325         NVOBJ_MTHD (dev, 0x005e, 0x02fc, nv04_graph_mthd_set_operation);
1326
1327         return 0;
1328 }