3 #include "nouveau_drv.h"
5 /* returns the size of fifo context */
7 nouveau_fifo_ctx_size(struct drm_device *dev)
9 struct drm_nouveau_private *dev_priv = dev->dev_private;
11 if (dev_priv->chipset >= 0x40)
14 if (dev_priv->chipset >= 0x17)
21 nv04_instmem_determine_amount(struct drm_device *dev)
23 struct drm_nouveau_private *dev_priv = dev->dev_private;
26 /* Figure out how much instance memory we need */
27 if (dev_priv->card_type >= NV_40) {
28 /* We'll want more instance memory than this on some NV4x cards.
29 * There's a 16MB aperture to play with that maps onto the end
30 * of vram. For now, only reserve a small piece until we know
31 * more about what each chipset requires.
33 switch (dev_priv->chipset) {
38 dev_priv->ramin_rsvd_vram = (2 * 1024 * 1024);
41 dev_priv->ramin_rsvd_vram = (1 * 1024 * 1024);
45 /*XXX: what *are* the limits on <NV40 cards?
47 dev_priv->ramin_rsvd_vram = (512 * 1024);
49 NV_DEBUG(dev, "RAMIN size: %dKiB\n", dev_priv->ramin_rsvd_vram >> 10);
51 /* Clear all of it, except the BIOS image that's in the first 64KiB */
52 dev_priv->engine.instmem.prepare_access(dev, true);
53 for (i = 64 * 1024; i < dev_priv->ramin_rsvd_vram; i += 4)
54 nv_wi32(dev, i, 0x00000000);
55 dev_priv->engine.instmem.finish_access(dev);
59 nv04_instmem_configure_fixed_tables(struct drm_device *dev)
61 struct drm_nouveau_private *dev_priv = dev->dev_private;
62 struct nouveau_engine *engine = &dev_priv->engine;
64 /* FIFO hash table (RAMHT)
65 * use 4k hash table at RAMIN+0x10000
66 * TODO: extend the hash table
68 dev_priv->ramht_offset = 0x10000;
69 dev_priv->ramht_bits = 9;
70 dev_priv->ramht_size = (1 << dev_priv->ramht_bits); /* nr entries */
71 dev_priv->ramht_size *= 8; /* 2 32-bit values per entry in RAMHT */
72 NV_DEBUG(dev, "RAMHT offset=0x%x, size=%d\n", dev_priv->ramht_offset,
73 dev_priv->ramht_size);
75 /* FIFO runout table (RAMRO) - 512k at 0x11200 */
76 dev_priv->ramro_offset = 0x11200;
77 dev_priv->ramro_size = 512;
78 NV_DEBUG(dev, "RAMRO offset=0x%x, size=%d\n", dev_priv->ramro_offset,
79 dev_priv->ramro_size);
81 /* FIFO context table (RAMFC)
82 * NV40 : Not sure exactly how to position RAMFC on some cards,
83 * 0x30002 seems to position it at RAMIN+0x20000 on these
84 * cards. RAMFC is 4kb (32 fifos, 128byte entries).
85 * Others: Position RAMFC at RAMIN+0x11400
87 dev_priv->ramfc_size = engine->fifo.channels *
88 nouveau_fifo_ctx_size(dev);
89 switch (dev_priv->card_type) {
91 dev_priv->ramfc_offset = 0x20000;
98 dev_priv->ramfc_offset = 0x11400;
101 NV_DEBUG(dev, "RAMFC offset=0x%x, size=%d\n", dev_priv->ramfc_offset,
102 dev_priv->ramfc_size);
105 int nv04_instmem_init(struct drm_device *dev)
107 struct drm_nouveau_private *dev_priv = dev->dev_private;
111 nv04_instmem_determine_amount(dev);
112 nv04_instmem_configure_fixed_tables(dev);
114 /* Create a heap to manage RAMIN allocations, we don't allocate
115 * the space that was reserved for RAMHT/FC/RO.
117 offset = dev_priv->ramfc_offset + dev_priv->ramfc_size;
119 /* It appears RAMRO (or something?) is controlled by 0x2220/0x2230
120 * on certain NV4x chipsets as well as RAMFC. When 0x2230 == 0
121 * ("new style" control) the upper 16-bits of 0x2220 points at this
122 * other mysterious table that's clobbering important things.
124 * We're now pointing this at RAMIN+0x30000 to avoid RAMFC getting
125 * smashed to pieces on us, so reserve 0x30000-0x40000 too..
127 if (dev_priv->card_type >= NV_40) {
128 if (offset < 0x40000)
132 ret = nouveau_mem_init_heap(&dev_priv->ramin_heap,
133 offset, dev_priv->ramin_rsvd_vram - offset);
135 dev_priv->ramin_heap = NULL;
136 NV_ERROR(dev, "Failed to init RAMIN heap\n");
143 nv04_instmem_takedown(struct drm_device *dev)
148 nv04_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj, uint32_t *sz)
150 if (gpuobj->im_backing)
157 nv04_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
159 struct drm_nouveau_private *dev_priv = dev->dev_private;
161 if (gpuobj && gpuobj->im_backing) {
162 if (gpuobj->im_bound)
163 dev_priv->engine.instmem.unbind(dev, gpuobj);
164 gpuobj->im_backing = NULL;
169 nv04_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
171 if (!gpuobj->im_pramin || gpuobj->im_bound)
174 gpuobj->im_bound = 1;
179 nv04_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
181 if (gpuobj->im_bound == 0)
184 gpuobj->im_bound = 0;
189 nv04_instmem_prepare_access(struct drm_device *dev, bool write)
194 nv04_instmem_finish_access(struct drm_device *dev)
199 nv04_instmem_suspend(struct drm_device *dev)
205 nv04_instmem_resume(struct drm_device *dev)