2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
25 #include <core/object.h>
26 #include <core/class.h>
28 #include "nouveau_drm.h"
29 #include "nouveau_dma.h"
30 #include "nouveau_fence.h"
32 struct nv10_fence_chan {
33 struct nouveau_fence_chan base;
36 struct nv10_fence_priv {
37 struct nouveau_fence_priv base;
38 struct nouveau_bo *bo;
44 nv10_fence_emit(struct nouveau_fence *fence)
46 struct nouveau_channel *chan = fence->channel;
47 int ret = RING_SPACE(chan, 2);
49 BEGIN_NV04(chan, 0, NV10_SUBCHAN_REF_CNT, 1);
50 OUT_RING (chan, fence->sequence);
58 nv10_fence_sync(struct nouveau_fence *fence,
59 struct nouveau_channel *prev, struct nouveau_channel *chan)
65 nv17_fence_sync(struct nouveau_fence *fence,
66 struct nouveau_channel *prev, struct nouveau_channel *chan)
68 struct nv10_fence_priv *priv = chan->drm->fence;
72 if (!mutex_trylock(&prev->cli->mutex))
75 spin_lock(&priv->lock);
76 value = priv->sequence;
78 spin_unlock(&priv->lock);
80 ret = RING_SPACE(prev, 5);
82 BEGIN_NV04(prev, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4);
83 OUT_RING (prev, NvSema);
85 OUT_RING (prev, value + 0);
86 OUT_RING (prev, value + 1);
90 if (!ret && !(ret = RING_SPACE(chan, 5))) {
91 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4);
92 OUT_RING (chan, NvSema);
94 OUT_RING (chan, value + 1);
95 OUT_RING (chan, value + 2);
99 mutex_unlock(&prev->cli->mutex);
104 nv10_fence_read(struct nouveau_channel *chan)
106 return nv_ro32(chan->object, 0x0048);
110 nv10_fence_context_del(struct nouveau_channel *chan)
112 struct nv10_fence_chan *fctx = chan->fence;
113 nouveau_fence_context_del(&fctx->base);
119 nv10_fence_context_new(struct nouveau_channel *chan)
121 struct nv10_fence_priv *priv = chan->drm->fence;
122 struct nv10_fence_chan *fctx;
125 fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
129 nouveau_fence_context_new(&fctx->base);
132 struct ttm_mem_reg *mem = &priv->bo->bo.mem;
133 struct nouveau_object *object;
134 u32 start = mem->start * PAGE_SIZE;
135 u32 limit = mem->start + mem->size - 1;
137 ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
139 &(struct nv_dma_class) {
140 .flags = NV_DMA_TARGET_VRAM |
144 }, sizeof(struct nv_dma_class),
149 nv10_fence_context_del(chan);
154 nv10_fence_destroy(struct nouveau_drm *drm)
156 struct nv10_fence_priv *priv = drm->fence;
157 nouveau_bo_unmap(priv->bo);
158 nouveau_bo_ref(NULL, &priv->bo);
164 nv10_fence_create(struct nouveau_drm *drm)
166 struct nv10_fence_priv *priv;
169 priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
173 priv->base.dtor = nv10_fence_destroy;
174 priv->base.context_new = nv10_fence_context_new;
175 priv->base.context_del = nv10_fence_context_del;
176 priv->base.emit = nv10_fence_emit;
177 priv->base.read = nv10_fence_read;
178 priv->base.sync = nv10_fence_sync;
179 spin_lock_init(&priv->lock);
181 if (nv_device(drm->device)->chipset >= 0x17) {
182 ret = nouveau_bo_new(drm->dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
183 0, 0x0000, NULL, &priv->bo);
185 ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
187 ret = nouveau_bo_map(priv->bo);
189 nouveau_bo_ref(NULL, &priv->bo);
193 nouveau_bo_wr32(priv->bo, 0x000, 0x00000000);
194 priv->base.sync = nv17_fence_sync;
199 nv10_fence_destroy(drm);