drivers/gpu/drm/nouveau/nv10_fifo.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30 #include "nouveau_ramht.h"
  31
  32 #define NV10_RAMFC(c) (dev_priv->ramfc->pinst + ((c) * NV10_RAMFC__SIZE))
  33 #define NV10_RAMFC__SIZE ((dev_priv->chipset) >= 0x17 ? 64 : 32)
  34
  35 int
  36 nv10_fifo_channel_id(struct drm_device *dev)
  37 {
  38         return nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) &
  39                         NV10_PFIFO_CACHE1_PUSH1_CHID_MASK;
  40 }
  41
  42 int
  43 nv10_fifo_create_context(struct nouveau_channel *chan)
  44 {
  45         struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
  46         struct drm_device *dev = chan->dev;
  47         uint32_t fc = NV10_RAMFC(chan->id);
  48         int ret;
  49
  50         ret = nouveau_gpuobj_new_fake(dev, NV10_RAMFC(chan->id), ~0,
  51                                       NV10_RAMFC__SIZE, NVOBJ_FLAG_ZERO_ALLOC |
  52                                       NVOBJ_FLAG_ZERO_FREE, &chan->ramfc);
  53         if (ret)
  54                 return ret;
  55
  56         /* Fill entries that are seen filled in dumps of nvidia driver just
  57          * after channel's is put into DMA mode
  58          */
  59         nv_wi32(dev, fc +  0, chan->pushbuf_base);
  60         nv_wi32(dev, fc +  4, chan->pushbuf_base);
  61         nv_wi32(dev, fc + 12, chan->pushbuf->pinst >> 4);
  62         nv_wi32(dev, fc + 20, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
  63                               NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
  64                               NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
  65 #ifdef __BIG_ENDIAN
  66                               NV_PFIFO_CACHE1_BIG_ENDIAN |
  67 #endif
  68                               0);
  69
  70         /* enable the fifo dma operation */
  71         nv_wr32(dev, NV04_PFIFO_MODE,
  72                 nv_rd32(dev, NV04_PFIFO_MODE) | (1 << chan->id));
  73         return 0;
  74 }
  75
  76 static void
  77 nv10_fifo_do_load_context(struct drm_device *dev, int chid)
  78 {
  79         struct drm_nouveau_private *dev_priv = dev->dev_private;
  80         uint32_t fc = NV10_RAMFC(chid), tmp;
  81
  82         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUT, nv_ri32(dev, fc + 0));
  83         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_GET, nv_ri32(dev, fc + 4));
  84         nv_wr32(dev, NV10_PFIFO_CACHE1_REF_CNT, nv_ri32(dev, fc + 8));
  85
  86         tmp = nv_ri32(dev, fc + 12);
  87         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE, tmp & 0xFFFF);
  88         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT, tmp >> 16);
  89
  90         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_STATE, nv_ri32(dev, fc + 16));
  91         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_FETCH, nv_ri32(dev, fc + 20));
  92         nv_wr32(dev, NV04_PFIFO_CACHE1_ENGINE, nv_ri32(dev, fc + 24));
  93         nv_wr32(dev, NV04_PFIFO_CACHE1_PULL1, nv_ri32(dev, fc + 28));
  94
  95         if (dev_priv->chipset < 0x17)
  96                 goto out;
  97
  98         nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_VALUE, nv_ri32(dev, fc + 32));
  99         tmp = nv_ri32(dev, fc + 36);
 100         nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP, tmp);
 101         nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT, nv_ri32(dev, fc + 40));
 102         nv_wr32(dev, NV10_PFIFO_CACHE1_SEMAPHORE, nv_ri32(dev, fc + 44));
 103         nv_wr32(dev, NV10_PFIFO_CACHE1_DMA_SUBROUTINE, nv_ri32(dev, fc + 48));
 104
 105 out:
 106         nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
 107         nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, 0);
 108 }
 109
 110 int
 111 nv10_fifo_load_context(struct nouveau_channel *chan)
 112 {
 113         struct drm_device *dev = chan->dev;
 114         uint32_t tmp;
 115
 116         nv10_fifo_do_load_context(dev, chan->id);
 117
 118         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1,
 119                      NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id);
 120         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 1);
 121
 122         /* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */
 123         tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_CTL) & ~(1 << 31);
 124         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_CTL, tmp);
 125
 126         return 0;
 127 }
 128
 129 int
 130 nv10_fifo_unload_context(struct drm_device *dev)
 131 {
 132         struct drm_nouveau_private *dev_priv = dev->dev_private;
 133         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 134         uint32_t fc, tmp;
 135         int chid;
 136
 137         chid = pfifo->channel_id(dev);
 138         if (chid < 0 || chid >= dev_priv->engine.fifo.channels)
 139                 return 0;
 140         fc = NV10_RAMFC(chid);
 141
 142         nv_wi32(dev, fc +  0, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT));
 143         nv_wi32(dev, fc +  4, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));
 144         nv_wi32(dev, fc +  8, nv_rd32(dev, NV10_PFIFO_CACHE1_REF_CNT));
 145         tmp  = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE) & 0xFFFF;
 146         tmp |= (nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16);
 147         nv_wi32(dev, fc + 12, tmp);
 148         nv_wi32(dev, fc + 16, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_STATE));
 149         nv_wi32(dev, fc + 20, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_FETCH));
 150         nv_wi32(dev, fc + 24, nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE));
 151         nv_wi32(dev, fc + 28, nv_rd32(dev, NV04_PFIFO_CACHE1_PULL1));
 152
 153         if (dev_priv->chipset < 0x17)
 154                 goto out;
 155
 156         nv_wi32(dev, fc + 32, nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
 157         tmp = nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP);
 158         nv_wi32(dev, fc + 36, tmp);
 159         nv_wi32(dev, fc + 40, nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
 160         nv_wi32(dev, fc + 44, nv_rd32(dev, NV10_PFIFO_CACHE1_SEMAPHORE));
 161         nv_wi32(dev, fc + 48, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));
 162
 163 out:
 164         nv10_fifo_do_load_context(dev, pfifo->channels - 1);
 165         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
 166         return 0;
 167 }
 168
 169 static void
 170 nv10_fifo_init_reset(struct drm_device *dev)
 171 {
 172         nv_wr32(dev, NV03_PMC_ENABLE,
 173                 nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PFIFO);
 174         nv_wr32(dev, NV03_PMC_ENABLE,
 175                 nv_rd32(dev, NV03_PMC_ENABLE) |  NV_PMC_ENABLE_PFIFO);
 176
 177         nv_wr32(dev, 0x003224, 0x000f0078);
 178         nv_wr32(dev, 0x002044, 0x0101ffff);
 179         nv_wr32(dev, 0x002040, 0x000000ff);
 180         nv_wr32(dev, 0x002500, 0x00000000);
 181         nv_wr32(dev, 0x003000, 0x00000000);
 182         nv_wr32(dev, 0x003050, 0x00000000);
 183
 184         nv_wr32(dev, 0x003258, 0x00000000);
 185         nv_wr32(dev, 0x003210, 0x00000000);
 186         nv_wr32(dev, 0x003270, 0x00000000);
 187 }
 188
 189 static void
 190 nv10_fifo_init_ramxx(struct drm_device *dev)
 191 {
 192         struct drm_nouveau_private *dev_priv = dev->dev_private;
 193
 194         nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
 195                                        ((dev_priv->ramht->bits - 9) << 16) |
 196                                        (dev_priv->ramht->gpuobj->pinst >> 8));
 197         nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro->pinst >> 8);
 198
 199         if (dev_priv->chipset < 0x17) {
 200                 nv_wr32(dev, NV03_PFIFO_RAMFC, dev_priv->ramfc->pinst >> 8);
 201         } else {
 202                 nv_wr32(dev, NV03_PFIFO_RAMFC, (dev_priv->ramfc->pinst >> 8) |
 203                                                (1 << 16) /* 64 Bytes entry*/);
 204                 /* XXX nvidia blob set bit 18, 21,23 for nv20 & nv30 */
 205         }
 206 }
 207
 208 static void
 209 nv10_fifo_init_intr(struct drm_device *dev)
 210 {
 211         nouveau_irq_register(dev, 8, nv04_fifo_isr);
 212         nv_wr32(dev, 0x002100, 0xffffffff);
 213         nv_wr32(dev, 0x002140, 0xffffffff);
 214 }
 215
 216 int
 217 nv10_fifo_init(struct drm_device *dev)
 218 {
 219         struct drm_nouveau_private *dev_priv = dev->dev_private;
 220         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 221         int i;
 222
 223         nv10_fifo_init_reset(dev);
 224         nv10_fifo_init_ramxx(dev);
 225
 226         nv10_fifo_do_load_context(dev, pfifo->channels - 1);
 227         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
 228
 229         nv10_fifo_init_intr(dev);
 230         pfifo->enable(dev);
 231         pfifo->reassign(dev, true);
 232
 233         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
 234                 if (dev_priv->channels.ptr[i]) {
 235                         uint32_t mode = nv_rd32(dev, NV04_PFIFO_MODE);
 236                         nv_wr32(dev, NV04_PFIFO_MODE, mode | (1 << i));
 237                 }
 238         }
 239
 240         return 0;
 241 }