2 * Copyright (C) 2012 Ben Skeggs.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "nouveau_drv.h"
30 #include "nouveau_fifo.h"
31 #include "nouveau_util.h"
32 #include "nouveau_ramht.h"
34 static struct ramfc_desc {
41 { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT },
42 { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET },
43 { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT },
44 { 32, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
45 { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
46 { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_STATE },
47 { 28, 0, 0x18, 0, NV04_PFIFO_CACHE1_DMA_FETCH },
48 { 2, 28, 0x18, 28, 0x002058 },
49 { 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_ENGINE },
50 { 32, 0, 0x20, 0, NV04_PFIFO_CACHE1_PULL1 },
51 { 32, 0, 0x24, 0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE },
52 { 32, 0, 0x28, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP },
53 { 32, 0, 0x2c, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT },
54 { 32, 0, 0x30, 0, NV10_PFIFO_CACHE1_SEMAPHORE },
55 { 32, 0, 0x34, 0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE },
56 { 32, 0, 0x38, 0, NV40_PFIFO_GRCTX_INSTANCE },
57 { 17, 0, 0x3c, 0, NV04_PFIFO_DMA_TIMESLICE },
58 { 32, 0, 0x40, 0, 0x0032e4 },
59 { 32, 0, 0x44, 0, 0x0032e8 },
60 { 32, 0, 0x4c, 0, 0x002088 },
61 { 32, 0, 0x50, 0, 0x003300 },
62 { 32, 0, 0x54, 0, 0x00330c },
66 struct nv40_fifo_priv {
67 struct nouveau_fifo_priv base;
68 struct ramfc_desc *ramfc_desc;
71 struct nv40_fifo_chan {
72 struct nouveau_fifo_chan base;
73 struct nouveau_gpuobj *ramfc;
77 nv40_fifo_context_new(struct nouveau_channel *chan, int engine)
79 struct drm_device *dev = chan->dev;
80 struct drm_nouveau_private *dev_priv = dev->dev_private;
81 struct nv40_fifo_priv *priv = nv_engine(dev, engine);
82 struct nv40_fifo_chan *fctx;
86 fctx = chan->engctx[engine] = kzalloc(sizeof(*fctx), GFP_KERNEL);
90 /* map channel control registers */
91 chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
92 NV03_USER(chan->id), PAGE_SIZE);
98 /* initialise default fifo context */
99 ret = nouveau_gpuobj_new_fake(dev, dev_priv->ramfc->pinst +
100 chan->id * 128, ~0, 128,
101 NVOBJ_FLAG_ZERO_ALLOC |
102 NVOBJ_FLAG_ZERO_FREE, &fctx->ramfc);
106 nv_wo32(fctx->ramfc, 0x00, chan->pushbuf_base);
107 nv_wo32(fctx->ramfc, 0x04, chan->pushbuf_base);
108 nv_wo32(fctx->ramfc, 0x0c, chan->pushbuf->pinst >> 4);
109 nv_wo32(fctx->ramfc, 0x18, 0x30000000 |
110 NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
111 NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
113 NV_PFIFO_CACHE1_BIG_ENDIAN |
115 NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
116 nv_wo32(fctx->ramfc, 0x3c, 0x0001ffff);
118 /* enable dma mode on the channel */
119 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
120 nv_mask(dev, NV04_PFIFO_MODE, (1 << chan->id), (1 << chan->id));
121 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
123 /*XXX: remove this later, need fifo engine context commit hook */
124 nouveau_gpuobj_ref(fctx->ramfc, &chan->ramfc);
128 priv->base.base.context_del(chan, engine);
133 nv40_fifo_init(struct drm_device *dev, int engine)
135 struct drm_nouveau_private *dev_priv = dev->dev_private;
136 struct nv40_fifo_priv *priv = nv_engine(dev, engine);
139 nv_mask(dev, NV03_PMC_ENABLE, NV_PMC_ENABLE_PFIFO, 0);
140 nv_mask(dev, NV03_PMC_ENABLE, NV_PMC_ENABLE_PFIFO, NV_PMC_ENABLE_PFIFO);
142 nv_wr32(dev, 0x002040, 0x000000ff);
143 nv_wr32(dev, 0x002044, 0x2101ffff);
144 nv_wr32(dev, 0x002058, 0x00000001);
146 nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
147 ((dev_priv->ramht->bits - 9) << 16) |
148 (dev_priv->ramht->gpuobj->pinst >> 8));
149 nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro->pinst >> 8);
151 switch (dev_priv->chipset) {
155 nv_wr32(dev, 0x002230, 0x00000001);
162 nv_wr32(dev, 0x002220, 0x00030002);
165 nv_wr32(dev, 0x002230, 0x00000000);
166 nv_wr32(dev, 0x002220, ((dev_priv->vram_size - 512 * 1024 +
167 dev_priv->ramfc->pinst) >> 16) |
172 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, priv->base.channels);
174 nv_wr32(dev, NV03_PFIFO_INTR_0, 0xffffffff);
175 nv_wr32(dev, NV03_PFIFO_INTR_EN_0, 0xffffffff);
177 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 1);
178 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
179 nv_wr32(dev, NV03_PFIFO_CACHES, 1);
181 for (i = 0; i < priv->base.channels; i++) {
182 if (dev_priv->channels.ptr[i])
183 nv_mask(dev, NV04_PFIFO_MODE, (1 << i), (1 << i));
190 nv40_fifo_create(struct drm_device *dev)
192 struct drm_nouveau_private *dev_priv = dev->dev_private;
193 struct nv40_fifo_priv *priv;
195 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
199 priv->base.base.destroy = nv04_fifo_destroy;
200 priv->base.base.init = nv40_fifo_init;
201 priv->base.base.fini = nv04_fifo_fini;
202 priv->base.base.context_new = nv40_fifo_context_new;
203 priv->base.base.context_del = nv04_fifo_context_del;
204 priv->base.channels = 31;
205 priv->ramfc_desc = nv40_ramfc;
206 dev_priv->eng[NVOBJ_ENGINE_FIFO] = &priv->base.base;
208 nouveau_irq_register(dev, 8, nv04_fifo_isr);