2 * Copyright (C) 2007 Ben Skeggs.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "nouveau_drv.h"
30 #include "nouveau_grctx.h"
32 struct nouveau_channel *
33 nv40_graph_channel(struct drm_device *dev)
35 struct drm_nouveau_private *dev_priv = dev->dev_private;
39 inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
40 if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
42 inst = (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) << 4;
44 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
45 struct nouveau_channel *chan = dev_priv->fifos[i];
47 if (chan && chan->ramin_grctx &&
48 chan->ramin_grctx->instance == inst)
56 nv40_graph_create_context(struct nouveau_channel *chan)
58 struct drm_device *dev = chan->dev;
59 struct drm_nouveau_private *dev_priv = dev->dev_private;
60 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
63 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pgraph->grctx_size,
64 16, NVOBJ_FLAG_ZERO_ALLOC,
69 /* Initialise default context values */
70 dev_priv->engine.instmem.prepare_access(dev, true);
71 if (!pgraph->ctxprog) {
72 struct nouveau_grctx ctx = {};
75 ctx.mode = NOUVEAU_GRCTX_VALS;
76 ctx.data = chan->ramin_grctx->gpuobj;
77 nv40_grctx_init(&ctx);
79 nouveau_grctx_vals_load(dev, chan->ramin_grctx->gpuobj);
81 nv_wo32(dev, chan->ramin_grctx->gpuobj, 0,
82 chan->ramin_grctx->gpuobj->im_pramin->start);
83 dev_priv->engine.instmem.finish_access(dev);
88 nv40_graph_destroy_context(struct nouveau_channel *chan)
90 nouveau_gpuobj_ref_del(chan->dev, &chan->ramin_grctx);
94 nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
96 uint32_t old_cp, tv = 1000, tmp;
99 old_cp = nv_rd32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER);
100 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
102 tmp = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0310);
103 tmp |= save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
104 NV40_PGRAPH_CTXCTL_0310_XFER_LOAD;
105 nv_wr32(dev, NV40_PGRAPH_CTXCTL_0310, tmp);
107 tmp = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0304);
108 tmp |= NV40_PGRAPH_CTXCTL_0304_XFER_CTX;
109 nv_wr32(dev, NV40_PGRAPH_CTXCTL_0304, tmp);
111 nouveau_wait_for_idle(dev);
113 for (i = 0; i < tv; i++) {
114 if (nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C) == 0)
118 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp);
121 uint32_t ucstat = nv_rd32(dev, NV40_PGRAPH_CTXCTL_UCODE_STAT);
122 NV_ERROR(dev, "Failed: Instance=0x%08x Save=%d\n", inst, save);
123 NV_ERROR(dev, "IP: 0x%02x, Opcode: 0x%08x\n",
124 ucstat >> NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT,
125 ucstat & NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK);
126 NV_ERROR(dev, "0x40030C = 0x%08x\n",
127 nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C));
134 /* Restore the context for a specific channel into PGRAPH */
136 nv40_graph_load_context(struct nouveau_channel *chan)
138 struct drm_device *dev = chan->dev;
142 if (!chan->ramin_grctx)
144 inst = chan->ramin_grctx->instance >> 4;
146 ret = nv40_graph_transfer_context(dev, inst, 0);
150 /* 0x40032C, no idea of it's exact function. Could simply be a
151 * record of the currently active PGRAPH context. It's currently
152 * unknown as to what bit 24 does. The nv ddx has it set, so we will
155 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
156 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR,
157 (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) |
158 NV40_PGRAPH_CTXCTL_CUR_LOADED);
159 /* 0x32E0 records the instance address of the active FIFO's PGRAPH
160 * context. If at any time this doesn't match 0x40032C, you will
161 * recieve PGRAPH_INTR_CONTEXT_SWITCH
163 nv_wr32(dev, NV40_PFIFO_GRCTX_INSTANCE, inst);
168 nv40_graph_unload_context(struct drm_device *dev)
173 inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
174 if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
176 inst &= NV40_PGRAPH_CTXCTL_CUR_INSTANCE;
178 ret = nv40_graph_transfer_context(dev, inst, 1);
180 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, inst);
185 nv40_graph_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
186 uint32_t size, uint32_t pitch)
188 struct drm_nouveau_private *dev_priv = dev->dev_private;
189 uint32_t limit = max(1u, addr + size) - 1;
194 switch (dev_priv->chipset) {
198 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch);
199 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit);
200 nv_wr32(dev, NV20_PGRAPH_TILE(i), addr);
207 nv_wr32(dev, NV47_PGRAPH_TSIZE(i), pitch);
208 nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), limit);
209 nv_wr32(dev, NV47_PGRAPH_TILE(i), addr);
210 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch);
211 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit);
212 nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr);
216 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch);
217 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit);
218 nv_wr32(dev, NV20_PGRAPH_TILE(i), addr);
219 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch);
220 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit);
221 nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr);
236 nv40_graph_init(struct drm_device *dev)
238 struct drm_nouveau_private *dev_priv =
239 (struct drm_nouveau_private *)dev->dev_private;
240 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
244 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
245 ~NV_PMC_ENABLE_PGRAPH);
246 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
247 NV_PMC_ENABLE_PGRAPH);
250 nouveau_grctx_prog_load(dev);
251 dev_priv->engine.graph.grctx_size = 175 * 1024;
254 if (!dev_priv->engine.graph.ctxprog) {
255 struct nouveau_grctx ctx = {};
259 ctx.mode = NOUVEAU_GRCTX_PROG;
261 ctx.ctxprog_max = 256;
262 nv40_grctx_init(&ctx);
263 dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
265 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
266 for (i = 0; i < ctx.ctxprog_len; i++)
267 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
270 /* No context present currently */
271 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
273 nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
274 nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
276 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
277 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
278 nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0);
279 nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
280 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000);
281 nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
283 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
284 nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF);
286 j = nv_rd32(dev, 0x1540) & 0xff;
288 for (i = 0; !(j & 1); j >>= 1, i++)
290 nv_wr32(dev, 0x405000, i);
293 if (dev_priv->chipset == 0x40) {
294 nv_wr32(dev, 0x4009b0, 0x83280fff);
295 nv_wr32(dev, 0x4009b4, 0x000000a0);
297 nv_wr32(dev, 0x400820, 0x83280eff);
298 nv_wr32(dev, 0x400824, 0x000000a0);
301 switch (dev_priv->chipset) {
304 nv_wr32(dev, 0x4009b8, 0x0078e366);
305 nv_wr32(dev, 0x4009bc, 0x0000014c);
308 case 0x42: /* pciid also 0x00Cx */
309 /* case 0x0120: XXX (pciid) */
310 nv_wr32(dev, 0x400828, 0x007596ff);
311 nv_wr32(dev, 0x40082c, 0x00000108);
314 nv_wr32(dev, 0x400828, 0x0072cb77);
315 nv_wr32(dev, 0x40082c, 0x00000108);
320 case 0x4c: /* G7x-based C51 */
322 nv_wr32(dev, 0x400860, 0);
323 nv_wr32(dev, 0x400864, 0);
328 nv_wr32(dev, 0x400828, 0x07830610);
329 nv_wr32(dev, 0x40082c, 0x0000016A);
335 nv_wr32(dev, 0x400b38, 0x2ffff800);
336 nv_wr32(dev, 0x400b3c, 0x00006000);
338 /* Tiling related stuff. */
339 switch (dev_priv->chipset) {
342 nv_wr32(dev, 0x400bc4, 0x1003d888);
343 nv_wr32(dev, 0x400bbc, 0xb7a7b500);
346 nv_wr32(dev, 0x400bc4, 0x0000e024);
347 nv_wr32(dev, 0x400bbc, 0xb7a7b520);
352 nv_wr32(dev, 0x400bc4, 0x1003d888);
353 nv_wr32(dev, 0x400bbc, 0xb7a7b540);
359 /* Turn all the tiling regions off. */
360 for (i = 0; i < pfb->num_tiles; i++)
361 nv40_graph_set_region_tiling(dev, i, 0, 0, 0);
363 /* begin RAM config */
364 vramsz = drm_get_resource_len(dev, 0) - 1;
365 switch (dev_priv->chipset) {
367 nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
368 nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
369 nv_wr32(dev, 0x4069A4, nv_rd32(dev, NV04_PFB_CFG0));
370 nv_wr32(dev, 0x4069A8, nv_rd32(dev, NV04_PFB_CFG1));
371 nv_wr32(dev, 0x400820, 0);
372 nv_wr32(dev, 0x400824, 0);
373 nv_wr32(dev, 0x400864, vramsz);
374 nv_wr32(dev, 0x400868, vramsz);
377 switch (dev_priv->chipset) {
382 nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0));
383 nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1));
386 nv_wr32(dev, 0x4009F0, nv_rd32(dev, NV04_PFB_CFG0));
387 nv_wr32(dev, 0x4009F4, nv_rd32(dev, NV04_PFB_CFG1));
390 nv_wr32(dev, 0x4069F0, nv_rd32(dev, NV04_PFB_CFG0));
391 nv_wr32(dev, 0x4069F4, nv_rd32(dev, NV04_PFB_CFG1));
392 nv_wr32(dev, 0x400840, 0);
393 nv_wr32(dev, 0x400844, 0);
394 nv_wr32(dev, 0x4008A0, vramsz);
395 nv_wr32(dev, 0x4008A4, vramsz);
402 void nv40_graph_takedown(struct drm_device *dev)
404 nouveau_grctx_fini(dev);
407 struct nouveau_pgraph_object_class nv40_graph_grclass[] = {
408 { 0x0030, false, NULL }, /* null */
409 { 0x0039, false, NULL }, /* m2mf */
410 { 0x004a, false, NULL }, /* gdirect */
411 { 0x009f, false, NULL }, /* imageblit (nv12) */
412 { 0x008a, false, NULL }, /* ifc */
413 { 0x0089, false, NULL }, /* sifm */
414 { 0x3089, false, NULL }, /* sifm (nv40) */
415 { 0x0062, false, NULL }, /* surf2d */
416 { 0x3062, false, NULL }, /* surf2d (nv40) */
417 { 0x0043, false, NULL }, /* rop */
418 { 0x0012, false, NULL }, /* beta1 */
419 { 0x0072, false, NULL }, /* beta4 */
420 { 0x0019, false, NULL }, /* cliprect */
421 { 0x0044, false, NULL }, /* pattern */
422 { 0x309e, false, NULL }, /* swzsurf */
423 { 0x4097, false, NULL }, /* curie (nv40) */
424 { 0x4497, false, NULL }, /* curie (nv44) */