2 * Copyright (C) 2007 Ben Skeggs.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "nouveau_drv.h"
30 #include "nouveau_grctx.h"
32 static int nv40_graph_register(struct drm_device *);
33 static void nv40_graph_isr(struct drm_device *);
35 struct nouveau_channel *
36 nv40_graph_channel(struct drm_device *dev)
38 struct drm_nouveau_private *dev_priv = dev->dev_private;
42 inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
43 if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
45 inst = (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) << 4;
47 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
48 struct nouveau_channel *chan = dev_priv->channels.ptr[i];
50 if (chan && chan->ramin_grctx &&
51 chan->ramin_grctx->pinst == inst)
59 nv40_graph_create_context(struct nouveau_channel *chan)
61 struct drm_device *dev = chan->dev;
62 struct drm_nouveau_private *dev_priv = dev->dev_private;
63 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
64 struct nouveau_grctx ctx = {};
68 ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 16,
69 NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin_grctx);
73 /* Initialise default context values */
75 ctx.mode = NOUVEAU_GRCTX_VALS;
76 ctx.data = chan->ramin_grctx;
77 nv40_grctx_init(&ctx);
79 nv_wo32(chan->ramin_grctx, 0, chan->ramin_grctx->pinst);
81 /* init grctx pointer in ramfc, and on PFIFO if channel is
82 * already active there
84 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
85 nv_wo32(chan->ramfc, 0x38, chan->ramin_grctx->pinst >> 4);
86 nv_mask(dev, 0x002500, 0x00000001, 0x00000000);
87 if ((nv_rd32(dev, 0x003204) & 0x0000001f) == chan->id)
88 nv_wr32(dev, 0x0032e0, chan->ramin_grctx->pinst >> 4);
89 nv_mask(dev, 0x002500, 0x00000001, 0x00000001);
90 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
95 nv40_graph_destroy_context(struct nouveau_channel *chan)
97 struct drm_device *dev = chan->dev;
98 struct drm_nouveau_private *dev_priv = dev->dev_private;
99 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
102 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
103 pgraph->fifo_access(dev, false);
105 /* Unload the context if it's the currently active one */
106 if (pgraph->channel(dev) == chan)
107 pgraph->unload_context(dev);
109 pgraph->fifo_access(dev, true);
110 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
112 /* Free the context resources */
113 nouveau_gpuobj_ref(NULL, &chan->ramin_grctx);
117 nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
119 uint32_t old_cp, tv = 1000, tmp;
122 old_cp = nv_rd32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER);
123 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
125 tmp = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0310);
126 tmp |= save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
127 NV40_PGRAPH_CTXCTL_0310_XFER_LOAD;
128 nv_wr32(dev, NV40_PGRAPH_CTXCTL_0310, tmp);
130 tmp = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0304);
131 tmp |= NV40_PGRAPH_CTXCTL_0304_XFER_CTX;
132 nv_wr32(dev, NV40_PGRAPH_CTXCTL_0304, tmp);
134 nouveau_wait_for_idle(dev);
136 for (i = 0; i < tv; i++) {
137 if (nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C) == 0)
141 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp);
144 uint32_t ucstat = nv_rd32(dev, NV40_PGRAPH_CTXCTL_UCODE_STAT);
145 NV_ERROR(dev, "Failed: Instance=0x%08x Save=%d\n", inst, save);
146 NV_ERROR(dev, "IP: 0x%02x, Opcode: 0x%08x\n",
147 ucstat >> NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT,
148 ucstat & NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK);
149 NV_ERROR(dev, "0x40030C = 0x%08x\n",
150 nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C));
157 /* Restore the context for a specific channel into PGRAPH */
159 nv40_graph_load_context(struct nouveau_channel *chan)
161 struct drm_device *dev = chan->dev;
165 if (!chan->ramin_grctx)
167 inst = chan->ramin_grctx->pinst >> 4;
169 ret = nv40_graph_transfer_context(dev, inst, 0);
173 /* 0x40032C, no idea of it's exact function. Could simply be a
174 * record of the currently active PGRAPH context. It's currently
175 * unknown as to what bit 24 does. The nv ddx has it set, so we will
178 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
179 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR,
180 (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) |
181 NV40_PGRAPH_CTXCTL_CUR_LOADED);
182 /* 0x32E0 records the instance address of the active FIFO's PGRAPH
183 * context. If at any time this doesn't match 0x40032C, you will
184 * recieve PGRAPH_INTR_CONTEXT_SWITCH
186 nv_wr32(dev, NV40_PFIFO_GRCTX_INSTANCE, inst);
191 nv40_graph_unload_context(struct drm_device *dev)
196 inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
197 if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
199 inst &= NV40_PGRAPH_CTXCTL_CUR_INSTANCE;
201 ret = nv40_graph_transfer_context(dev, inst, 1);
203 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, inst);
208 nv40_graph_set_tile_region(struct drm_device *dev, int i)
210 struct drm_nouveau_private *dev_priv = dev->dev_private;
211 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
213 switch (dev_priv->chipset) {
217 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
218 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
219 nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
226 nv_wr32(dev, NV47_PGRAPH_TSIZE(i), tile->pitch);
227 nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), tile->limit);
228 nv_wr32(dev, NV47_PGRAPH_TILE(i), tile->addr);
229 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
230 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
231 nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
235 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
236 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
237 nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
238 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
239 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
240 nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
255 nv40_graph_init(struct drm_device *dev)
257 struct drm_nouveau_private *dev_priv =
258 (struct drm_nouveau_private *)dev->dev_private;
259 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
260 struct nouveau_grctx ctx = {};
261 uint32_t vramsz, *cp;
264 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
265 ~NV_PMC_ENABLE_PGRAPH);
266 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
267 NV_PMC_ENABLE_PGRAPH);
269 cp = kmalloc(sizeof(*cp) * 256, GFP_KERNEL);
274 ctx.mode = NOUVEAU_GRCTX_PROG;
276 ctx.ctxprog_max = 256;
277 nv40_grctx_init(&ctx);
278 dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
280 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
281 for (i = 0; i < ctx.ctxprog_len; i++)
282 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
286 ret = nv40_graph_register(dev);
290 /* No context present currently */
291 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
293 nouveau_irq_register(dev, 12, nv40_graph_isr);
294 nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
295 nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
297 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
298 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
299 nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0);
300 nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
301 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000);
302 nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
304 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
305 nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF);
307 j = nv_rd32(dev, 0x1540) & 0xff;
309 for (i = 0; !(j & 1); j >>= 1, i++)
311 nv_wr32(dev, 0x405000, i);
314 if (dev_priv->chipset == 0x40) {
315 nv_wr32(dev, 0x4009b0, 0x83280fff);
316 nv_wr32(dev, 0x4009b4, 0x000000a0);
318 nv_wr32(dev, 0x400820, 0x83280eff);
319 nv_wr32(dev, 0x400824, 0x000000a0);
322 switch (dev_priv->chipset) {
325 nv_wr32(dev, 0x4009b8, 0x0078e366);
326 nv_wr32(dev, 0x4009bc, 0x0000014c);
329 case 0x42: /* pciid also 0x00Cx */
330 /* case 0x0120: XXX (pciid) */
331 nv_wr32(dev, 0x400828, 0x007596ff);
332 nv_wr32(dev, 0x40082c, 0x00000108);
335 nv_wr32(dev, 0x400828, 0x0072cb77);
336 nv_wr32(dev, 0x40082c, 0x00000108);
341 case 0x4c: /* G7x-based C51 */
343 nv_wr32(dev, 0x400860, 0);
344 nv_wr32(dev, 0x400864, 0);
349 nv_wr32(dev, 0x400828, 0x07830610);
350 nv_wr32(dev, 0x40082c, 0x0000016A);
356 nv_wr32(dev, 0x400b38, 0x2ffff800);
357 nv_wr32(dev, 0x400b3c, 0x00006000);
359 /* Tiling related stuff. */
360 switch (dev_priv->chipset) {
363 nv_wr32(dev, 0x400bc4, 0x1003d888);
364 nv_wr32(dev, 0x400bbc, 0xb7a7b500);
367 nv_wr32(dev, 0x400bc4, 0x0000e024);
368 nv_wr32(dev, 0x400bbc, 0xb7a7b520);
373 nv_wr32(dev, 0x400bc4, 0x1003d888);
374 nv_wr32(dev, 0x400bbc, 0xb7a7b540);
380 /* Turn all the tiling regions off. */
381 for (i = 0; i < pfb->num_tiles; i++)
382 nv40_graph_set_tile_region(dev, i);
384 /* begin RAM config */
385 vramsz = pci_resource_len(dev->pdev, 0) - 1;
386 switch (dev_priv->chipset) {
388 nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
389 nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
390 nv_wr32(dev, 0x4069A4, nv_rd32(dev, NV04_PFB_CFG0));
391 nv_wr32(dev, 0x4069A8, nv_rd32(dev, NV04_PFB_CFG1));
392 nv_wr32(dev, 0x400820, 0);
393 nv_wr32(dev, 0x400824, 0);
394 nv_wr32(dev, 0x400864, vramsz);
395 nv_wr32(dev, 0x400868, vramsz);
398 switch (dev_priv->chipset) {
403 nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0));
404 nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1));
407 nv_wr32(dev, 0x4009F0, nv_rd32(dev, NV04_PFB_CFG0));
408 nv_wr32(dev, 0x4009F4, nv_rd32(dev, NV04_PFB_CFG1));
411 nv_wr32(dev, 0x4069F0, nv_rd32(dev, NV04_PFB_CFG0));
412 nv_wr32(dev, 0x4069F4, nv_rd32(dev, NV04_PFB_CFG1));
413 nv_wr32(dev, 0x400840, 0);
414 nv_wr32(dev, 0x400844, 0);
415 nv_wr32(dev, 0x4008A0, vramsz);
416 nv_wr32(dev, 0x4008A4, vramsz);
423 void nv40_graph_takedown(struct drm_device *dev)
425 nouveau_irq_unregister(dev, 12);
429 nv40_graph_register(struct drm_device *dev)
431 struct drm_nouveau_private *dev_priv = dev->dev_private;
433 if (dev_priv->engine.graph.registered)
436 NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
437 NVOBJ_CLASS(dev, 0x0030, GR); /* null */
438 NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
439 NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
440 NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
441 NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
442 NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
443 NVOBJ_CLASS(dev, 0x3089, GR); /* sifm (nv40) */
444 NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
445 NVOBJ_CLASS(dev, 0x3062, GR); /* surf2d (nv40) */
446 NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
447 NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
448 NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
449 NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
450 NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
451 NVOBJ_CLASS(dev, 0x309e, GR); /* swzsurf */
454 if (nv44_graph_class(dev))
455 NVOBJ_CLASS(dev, 0x4497, GR);
457 NVOBJ_CLASS(dev, 0x4097, GR);
460 NVOBJ_CLASS(dev, 0x506e, SW);
461 NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
463 dev_priv->engine.graph.registered = true;
468 nv40_graph_isr_chid(struct drm_device *dev, u32 inst)
470 struct drm_nouveau_private *dev_priv = dev->dev_private;
471 struct nouveau_channel *chan;
475 spin_lock_irqsave(&dev_priv->channels.lock, flags);
476 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
477 chan = dev_priv->channels.ptr[i];
478 if (!chan || !chan->ramin_grctx)
481 if (inst == chan->ramin_grctx->pinst)
484 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
489 nv40_graph_isr(struct drm_device *dev)
493 while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
494 u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
495 u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
496 u32 inst = (nv_rd32(dev, 0x40032c) & 0x000fffff) << 4;
497 u32 chid = nv40_graph_isr_chid(dev, inst);
498 u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
499 u32 subc = (addr & 0x00070000) >> 16;
500 u32 mthd = (addr & 0x00001ffc);
501 u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
502 u32 class = nv_rd32(dev, 0x400160 + subc * 4) & 0xffff;
505 if (stat & NV_PGRAPH_INTR_ERROR) {
506 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
507 if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
508 show &= ~NV_PGRAPH_INTR_ERROR;
510 if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
511 nv_mask(dev, 0x402000, 0, 0);
515 nv_wr32(dev, NV03_PGRAPH_INTR, stat);
516 nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
518 if (show && nouveau_ratelimit()) {
519 NV_INFO(dev, "PGRAPH -");
520 nouveau_bitfield_print(nv10_graph_intr, show);
522 nouveau_bitfield_print(nv04_graph_nsource, nsource);
524 nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
526 NV_INFO(dev, "PGRAPH - ch %d (0x%08x) subc %d "
527 "class 0x%04x mthd 0x%04x data 0x%08x\n",
528 chid, inst, subc, class, mthd, data);