2 * Copyright (C) 2007 Ben Skeggs.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "nouveau_drv.h"
30 #include "nouveau_fifo.h"
31 #include "nouveau_ramht.h"
33 struct nv40_graph_engine {
34 struct nouveau_exec_engine base;
39 nv40_graph_context_new(struct nouveau_channel *chan, int engine)
41 struct nv40_graph_engine *pgraph = nv_engine(chan->dev, engine);
42 struct drm_device *dev = chan->dev;
43 struct drm_nouveau_private *dev_priv = dev->dev_private;
44 struct nouveau_gpuobj *grctx = NULL;
48 ret = nouveau_gpuobj_new(dev, NULL, pgraph->grctx_size, 16,
49 NVOBJ_FLAG_ZERO_ALLOC, &grctx);
53 /* Initialise default context values */
54 nv40_grctx_fill(dev, grctx);
55 nv_wo32(grctx, 0, grctx->vinst);
57 /* init grctx pointer in ramfc, and on PFIFO if channel is
58 * already active there
60 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
61 nv_wo32(chan->ramfc, 0x38, grctx->vinst >> 4);
62 nv_mask(dev, 0x002500, 0x00000001, 0x00000000);
63 if ((nv_rd32(dev, 0x003204) & 0x0000001f) == chan->id)
64 nv_wr32(dev, 0x0032e0, grctx->vinst >> 4);
65 nv_mask(dev, 0x002500, 0x00000001, 0x00000001);
66 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
68 chan->engctx[engine] = grctx;
73 nv40_graph_context_del(struct nouveau_channel *chan, int engine)
75 struct nouveau_gpuobj *grctx = chan->engctx[engine];
76 struct drm_device *dev = chan->dev;
77 struct drm_nouveau_private *dev_priv = dev->dev_private;
78 u32 inst = 0x01000000 | (grctx->pinst >> 4);
81 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
82 nv_mask(dev, 0x400720, 0x00000000, 0x00000001);
83 if (nv_rd32(dev, 0x40032c) == inst)
84 nv_mask(dev, 0x40032c, 0x01000000, 0x00000000);
85 if (nv_rd32(dev, 0x400330) == inst)
86 nv_mask(dev, 0x400330, 0x01000000, 0x00000000);
87 nv_mask(dev, 0x400720, 0x00000001, 0x00000001);
88 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
90 /* Free the context resources */
91 nouveau_gpuobj_ref(NULL, &grctx);
92 chan->engctx[engine] = NULL;
96 nv40_graph_object_new(struct nouveau_channel *chan, int engine,
97 u32 handle, u16 class)
99 struct drm_device *dev = chan->dev;
100 struct nouveau_gpuobj *obj = NULL;
103 ret = nouveau_gpuobj_new(dev, chan, 20, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
109 nv_wo32(obj, 0x00, class);
110 nv_wo32(obj, 0x04, 0x00000000);
112 nv_wo32(obj, 0x08, 0x00000000);
114 nv_wo32(obj, 0x08, 0x01000000);
116 nv_wo32(obj, 0x0c, 0x00000000);
117 nv_wo32(obj, 0x10, 0x00000000);
119 ret = nouveau_ramht_insert(chan, handle, obj);
120 nouveau_gpuobj_ref(NULL, &obj);
125 nv40_graph_set_tile_region(struct drm_device *dev, int i)
127 struct drm_nouveau_private *dev_priv = dev->dev_private;
128 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
130 switch (dev_priv->chipset) {
132 case 0x41: /* guess */
135 case 0x45: /* guess */
137 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
138 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
139 nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
140 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
141 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
142 nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
146 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
147 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
148 nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
157 nv_wr32(dev, NV47_PGRAPH_TSIZE(i), tile->pitch);
158 nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), tile->limit);
159 nv_wr32(dev, NV47_PGRAPH_TILE(i), tile->addr);
160 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
161 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
162 nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
177 nv40_graph_init(struct drm_device *dev, int engine)
179 struct nv40_graph_engine *pgraph = nv_engine(dev, engine);
180 struct drm_nouveau_private *dev_priv = dev->dev_private;
181 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
185 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
186 ~NV_PMC_ENABLE_PGRAPH);
187 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
188 NV_PMC_ENABLE_PGRAPH);
190 /* generate and upload context program */
191 nv40_grctx_init(dev, &pgraph->grctx_size);
193 /* No context present currently */
194 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
196 nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
197 nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
199 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
200 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
201 nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0);
202 nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
203 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000);
204 nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
206 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
207 nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF);
209 j = nv_rd32(dev, 0x1540) & 0xff;
211 for (i = 0; !(j & 1); j >>= 1, i++)
213 nv_wr32(dev, 0x405000, i);
216 if (dev_priv->chipset == 0x40) {
217 nv_wr32(dev, 0x4009b0, 0x83280fff);
218 nv_wr32(dev, 0x4009b4, 0x000000a0);
220 nv_wr32(dev, 0x400820, 0x83280eff);
221 nv_wr32(dev, 0x400824, 0x000000a0);
224 switch (dev_priv->chipset) {
227 nv_wr32(dev, 0x4009b8, 0x0078e366);
228 nv_wr32(dev, 0x4009bc, 0x0000014c);
231 case 0x42: /* pciid also 0x00Cx */
232 /* case 0x0120: XXX (pciid) */
233 nv_wr32(dev, 0x400828, 0x007596ff);
234 nv_wr32(dev, 0x40082c, 0x00000108);
237 nv_wr32(dev, 0x400828, 0x0072cb77);
238 nv_wr32(dev, 0x40082c, 0x00000108);
243 case 0x4c: /* G7x-based C51 */
245 nv_wr32(dev, 0x400860, 0);
246 nv_wr32(dev, 0x400864, 0);
251 nv_wr32(dev, 0x400828, 0x07830610);
252 nv_wr32(dev, 0x40082c, 0x0000016A);
258 nv_wr32(dev, 0x400b38, 0x2ffff800);
259 nv_wr32(dev, 0x400b3c, 0x00006000);
261 /* Tiling related stuff. */
262 switch (dev_priv->chipset) {
265 nv_wr32(dev, 0x400bc4, 0x1003d888);
266 nv_wr32(dev, 0x400bbc, 0xb7a7b500);
269 nv_wr32(dev, 0x400bc4, 0x0000e024);
270 nv_wr32(dev, 0x400bbc, 0xb7a7b520);
275 nv_wr32(dev, 0x400bc4, 0x1003d888);
276 nv_wr32(dev, 0x400bbc, 0xb7a7b540);
282 /* Turn all the tiling regions off. */
283 for (i = 0; i < pfb->num_tiles; i++)
284 nv40_graph_set_tile_region(dev, i);
286 /* begin RAM config */
287 vramsz = pci_resource_len(dev->pdev, 0) - 1;
288 switch (dev_priv->chipset) {
290 nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
291 nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
292 nv_wr32(dev, 0x4069A4, nv_rd32(dev, NV04_PFB_CFG0));
293 nv_wr32(dev, 0x4069A8, nv_rd32(dev, NV04_PFB_CFG1));
294 nv_wr32(dev, 0x400820, 0);
295 nv_wr32(dev, 0x400824, 0);
296 nv_wr32(dev, 0x400864, vramsz);
297 nv_wr32(dev, 0x400868, vramsz);
300 switch (dev_priv->chipset) {
308 nv_wr32(dev, 0x4009F0, nv_rd32(dev, NV04_PFB_CFG0));
309 nv_wr32(dev, 0x4009F4, nv_rd32(dev, NV04_PFB_CFG1));
312 nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0));
313 nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1));
316 nv_wr32(dev, 0x4069F0, nv_rd32(dev, NV04_PFB_CFG0));
317 nv_wr32(dev, 0x4069F4, nv_rd32(dev, NV04_PFB_CFG1));
318 nv_wr32(dev, 0x400840, 0);
319 nv_wr32(dev, 0x400844, 0);
320 nv_wr32(dev, 0x4008A0, vramsz);
321 nv_wr32(dev, 0x4008A4, vramsz);
329 nv40_graph_fini(struct drm_device *dev, int engine, bool suspend)
331 u32 inst = nv_rd32(dev, 0x40032c);
332 if (inst & 0x01000000) {
333 nv_wr32(dev, 0x400720, 0x00000000);
334 nv_wr32(dev, 0x400784, inst);
335 nv_mask(dev, 0x400310, 0x00000020, 0x00000020);
336 nv_mask(dev, 0x400304, 0x00000001, 0x00000001);
337 if (!nv_wait(dev, 0x400300, 0x00000001, 0x00000000)) {
338 u32 insn = nv_rd32(dev, 0x400308);
339 NV_ERROR(dev, "PGRAPH: ctxprog timeout 0x%08x\n", insn);
341 nv_mask(dev, 0x40032c, 0x01000000, 0x00000000);
347 nv40_graph_isr_chid(struct drm_device *dev, u32 inst)
349 struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
350 struct drm_nouveau_private *dev_priv = dev->dev_private;
351 struct nouveau_gpuobj *grctx;
355 spin_lock_irqsave(&dev_priv->channels.lock, flags);
356 for (i = 0; i < pfifo->channels; i++) {
357 if (!dev_priv->channels.ptr[i])
359 grctx = dev_priv->channels.ptr[i]->engctx[NVOBJ_ENGINE_GR];
361 if (grctx && grctx->pinst == inst)
364 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
369 nv40_graph_isr(struct drm_device *dev)
373 while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
374 u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
375 u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
376 u32 inst = (nv_rd32(dev, 0x40032c) & 0x000fffff) << 4;
377 u32 chid = nv40_graph_isr_chid(dev, inst);
378 u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
379 u32 subc = (addr & 0x00070000) >> 16;
380 u32 mthd = (addr & 0x00001ffc);
381 u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
382 u32 class = nv_rd32(dev, 0x400160 + subc * 4) & 0xffff;
385 if (stat & NV_PGRAPH_INTR_ERROR) {
386 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
387 if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
388 show &= ~NV_PGRAPH_INTR_ERROR;
390 if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
391 nv_mask(dev, 0x402000, 0, 0);
395 nv_wr32(dev, NV03_PGRAPH_INTR, stat);
396 nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
398 if (show && nouveau_ratelimit()) {
399 NV_INFO(dev, "PGRAPH -");
400 nouveau_bitfield_print(nv10_graph_intr, show);
402 nouveau_bitfield_print(nv04_graph_nsource, nsource);
404 nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
406 NV_INFO(dev, "PGRAPH - ch %d (0x%08x) subc %d "
407 "class 0x%04x mthd 0x%04x data 0x%08x\n",
408 chid, inst, subc, class, mthd, data);
414 nv40_graph_destroy(struct drm_device *dev, int engine)
416 struct nv40_graph_engine *pgraph = nv_engine(dev, engine);
418 nouveau_irq_unregister(dev, 12);
420 NVOBJ_ENGINE_DEL(dev, GR);
425 nv40_graph_create(struct drm_device *dev)
427 struct nv40_graph_engine *pgraph;
429 pgraph = kzalloc(sizeof(*pgraph), GFP_KERNEL);
433 pgraph->base.destroy = nv40_graph_destroy;
434 pgraph->base.init = nv40_graph_init;
435 pgraph->base.fini = nv40_graph_fini;
436 pgraph->base.context_new = nv40_graph_context_new;
437 pgraph->base.context_del = nv40_graph_context_del;
438 pgraph->base.object_new = nv40_graph_object_new;
439 pgraph->base.set_tile_region = nv40_graph_set_tile_region;
441 NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
442 nouveau_irq_register(dev, 12, nv40_graph_isr);
444 NVOBJ_CLASS(dev, 0x0030, GR); /* null */
445 NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
446 NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
447 NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
448 NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
449 NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
450 NVOBJ_CLASS(dev, 0x3089, GR); /* sifm (nv40) */
451 NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
452 NVOBJ_CLASS(dev, 0x3062, GR); /* surf2d (nv40) */
453 NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
454 NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
455 NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
456 NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
457 NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
458 NVOBJ_CLASS(dev, 0x309e, GR); /* swzsurf */
461 if (nv44_graph_class(dev))
462 NVOBJ_CLASS(dev, 0x4497, GR);
464 NVOBJ_CLASS(dev, 0x4097, GR);