2 * Copyright 2011 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "nouveau_drm.h"
27 #include "nouveau_bios.h"
28 #include "nouveau_pm.h"
29 #include "nouveau_hw.h"
31 #include <subdev/bios/pll.h>
32 #include <subdev/clock.h>
33 #include <subdev/timer.h>
35 #include <engine/fifo.h>
37 #define min2(a,b) ((a) < (b) ? (a) : (b))
40 read_pll_1(struct drm_device *dev, u32 reg)
42 struct nouveau_device *device = nouveau_dev(dev);
43 u32 ctrl = nv_rd32(device, reg + 0x00);
44 int P = (ctrl & 0x00070000) >> 16;
45 int N = (ctrl & 0x0000ff00) >> 8;
46 int M = (ctrl & 0x000000ff) >> 0;
47 u32 ref = 27000, clk = 0;
49 if (ctrl & 0x80000000)
56 read_pll_2(struct drm_device *dev, u32 reg)
58 struct nouveau_device *device = nouveau_dev(dev);
59 u32 ctrl = nv_rd32(device, reg + 0x00);
60 u32 coef = nv_rd32(device, reg + 0x04);
61 int N2 = (coef & 0xff000000) >> 24;
62 int M2 = (coef & 0x00ff0000) >> 16;
63 int N1 = (coef & 0x0000ff00) >> 8;
64 int M1 = (coef & 0x000000ff) >> 0;
65 int P = (ctrl & 0x00070000) >> 16;
66 u32 ref = 27000, clk = 0;
68 if ((ctrl & 0x80000000) && M1) {
70 if ((ctrl & 0x40000100) == 0x40000000) {
82 read_clk(struct drm_device *dev, u32 src)
86 return read_pll_2(dev, 0x004000);
88 return read_pll_1(dev, 0x004008);
97 nv40_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
99 struct nouveau_device *device = nouveau_dev(dev);
100 u32 ctrl = nv_rd32(device, 0x00c040);
102 perflvl->core = read_clk(dev, (ctrl & 0x00000003) >> 0);
103 perflvl->shader = read_clk(dev, (ctrl & 0x00000030) >> 4);
104 perflvl->memory = read_pll_2(dev, 0x4020);
108 struct nv40_pm_state {
118 nv40_calc_pll(struct drm_device *dev, u32 reg, struct nvbios_pll *pll,
119 u32 clk, int *N1, int *M1, int *N2, int *M2, int *log2P)
121 struct nouveau_device *device = nouveau_dev(dev);
122 struct nouveau_bios *bios = nouveau_bios(device);
123 struct nouveau_clock *pclk = nouveau_clock(device);
124 struct nouveau_pll_vals coef;
127 ret = nvbios_pll_parse(bios, reg, pll);
131 if (clk < pll->vco1.max_freq)
132 pll->vco2.max_freq = 0;
134 pclk->pll_calc(pclk, pll, clk, &coef);
141 if (pll->vco2.max_freq) {
154 nv40_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
156 struct nv40_pm_state *info;
157 struct nvbios_pll pll;
158 int N1, N2, M1, M2, log2P;
161 info = kmalloc(sizeof(*info), GFP_KERNEL);
163 return ERR_PTR(-ENOMEM);
165 /* core/geometric clock */
166 ret = nv40_calc_pll(dev, 0x004000, &pll, perflvl->core,
167 &N1, &M1, &N2, &M2, &log2P);
172 info->npll_ctrl = 0x80000100 | (log2P << 16);
173 info->npll_coef = (N1 << 8) | M1;
175 info->npll_ctrl = 0xc0000000 | (log2P << 16);
176 info->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
179 /* use the second PLL for shader/rop clock, if it differs from core */
180 if (perflvl->shader && perflvl->shader != perflvl->core) {
181 ret = nv40_calc_pll(dev, 0x004008, &pll, perflvl->shader,
182 &N1, &M1, NULL, NULL, &log2P);
186 info->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1;
187 info->ctrl = 0x00000223;
189 info->spll = 0x00000000;
190 info->ctrl = 0x00000333;
194 if (!perflvl->memory) {
195 info->mpll_ctrl = 0x00000000;
199 ret = nv40_calc_pll(dev, 0x004020, &pll, perflvl->memory,
200 &N1, &M1, &N2, &M2, &log2P);
204 info->mpll_ctrl = 0x80000000 | (log2P << 16);
205 info->mpll_ctrl |= min2(pll.bias_p + log2P, pll.max_p) << 20;
207 info->mpll_ctrl |= 0x00000100;
208 info->mpll_coef = (N1 << 8) | M1;
210 info->mpll_ctrl |= 0x40000000;
211 info->mpll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
223 nv40_pm_gr_idle(void *data)
225 struct drm_device *dev = data;
226 struct nouveau_device *device = nouveau_dev(dev);
228 if ((nv_rd32(device, 0x400760) & 0x000000f0) >> 4 !=
229 (nv_rd32(device, 0x400760) & 0x0000000f))
232 if (nv_rd32(device, 0x400700))
239 nv40_pm_clocks_set(struct drm_device *dev, void *pre_state)
241 struct nouveau_device *device = nouveau_dev(dev);
242 struct nouveau_fifo *pfifo = nouveau_fifo(device);
243 struct nouveau_drm *drm = nouveau_drm(dev);
244 struct nv40_pm_state *info = pre_state;
249 int i, ret = -EAGAIN;
251 /* determine which CRTCs are active, fetch VGA_SR1 for each */
252 for (i = 0; i < 2; i++) {
253 u32 vbl = nv_rd32(device, 0x600808 + (i * 0x2000));
256 if (vbl != nv_rd32(device, 0x600808 + (i * 0x2000))) {
257 nv_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01);
258 sr1[i] = nv_rd08(device, 0x0c03c5 + (i * 0x2000));
259 if (!(sr1[i] & 0x20))
260 crtc_mask |= (1 << i);
264 } while (cnt++ < 32);
267 /* halt and idle engines */
268 pfifo->pause(pfifo, &flags);
270 if (!nv_wait_cb(device, nv40_pm_gr_idle, dev))
275 /* set engine clocks */
276 nv_mask(device, 0x00c040, 0x00000333, 0x00000000);
277 nv_wr32(device, 0x004004, info->npll_coef);
278 nv_mask(device, 0x004000, 0xc0070100, info->npll_ctrl);
279 nv_mask(device, 0x004008, 0xc007ffff, info->spll);
281 nv_mask(device, 0x00c040, 0x00000333, info->ctrl);
283 if (!info->mpll_ctrl)
286 /* wait for vblank start on active crtcs, disable memory access */
287 for (i = 0; i < 2; i++) {
288 if (!(crtc_mask & (1 << i)))
290 nv_wait(device, 0x600808 + (i * 0x2000), 0x00010000, 0x00000000);
291 nv_wait(device, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);
292 nv_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01);
293 nv_wr08(device, 0x0c03c5 + (i * 0x2000), sr1[i] | 0x20);
296 /* prepare ram for reclocking */
297 nv_wr32(device, 0x1002d4, 0x00000001); /* precharge */
298 nv_wr32(device, 0x1002d0, 0x00000001); /* refresh */
299 nv_wr32(device, 0x1002d0, 0x00000001); /* refresh */
300 nv_mask(device, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */
301 nv_wr32(device, 0x1002dc, 0x00000001); /* enable self-refresh */
303 /* change the PLL of each memory partition */
304 nv_mask(device, 0x00c040, 0x0000c000, 0x00000000);
305 switch (nv_device(drm->device)->chipset) {
311 nv_mask(device, 0x004044, 0xc0771100, info->mpll_ctrl);
312 nv_mask(device, 0x00402c, 0xc0771100, info->mpll_ctrl);
313 nv_wr32(device, 0x004048, info->mpll_coef);
314 nv_wr32(device, 0x004030, info->mpll_coef);
318 nv_mask(device, 0x004038, 0xc0771100, info->mpll_ctrl);
319 nv_wr32(device, 0x00403c, info->mpll_coef);
321 nv_mask(device, 0x004020, 0xc0771100, info->mpll_ctrl);
322 nv_wr32(device, 0x004024, info->mpll_coef);
326 nv_mask(device, 0x00c040, 0x0000c000, 0x0000c000);
328 /* re-enable normal operation of memory controller */
329 nv_wr32(device, 0x1002dc, 0x00000000);
330 nv_mask(device, 0x100210, 0x80000000, 0x80000000);
333 /* execute memory reset script from vbios */
334 if (!bit_table(dev, 'M', &M))
335 nouveau_bios_run_init_table(dev, ROM16(M.data[0]), NULL, 0);
337 /* make sure we're in vblank (hopefully the same one as before), and
338 * then re-enable crtc memory access
340 for (i = 0; i < 2; i++) {
341 if (!(crtc_mask & (1 << i)))
343 nv_wait(device, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);
344 nv_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01);
345 nv_wr08(device, 0x0c03c5 + (i * 0x2000), sr1[i]);
350 pfifo->start(pfifo, &flags);