2 * Copyright 2011 Red Hat Inc.
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "nouveau_drv.h"
27 #include "nouveau_bios.h"
28 #include "nouveau_pm.h"
29 #include "nouveau_hw.h"
31 #define min2(a,b) ((a) < (b) ? (a) : (b))
34 read_pll_1(struct drm_device *dev, u32 reg)
36 u32 ctrl = nv_rd32(dev, reg + 0x00);
37 int P = (ctrl & 0x00070000) >> 16;
38 int N = (ctrl & 0x0000ff00) >> 8;
39 int M = (ctrl & 0x000000ff) >> 0;
40 u32 ref = 27000, clk = 0;
42 if (ctrl & 0x80000000)
49 read_pll_2(struct drm_device *dev, u32 reg)
51 u32 ctrl = nv_rd32(dev, reg + 0x00);
52 u32 coef = nv_rd32(dev, reg + 0x04);
53 int N2 = (coef & 0xff000000) >> 24;
54 int M2 = (coef & 0x00ff0000) >> 16;
55 int N1 = (coef & 0x0000ff00) >> 8;
56 int M1 = (coef & 0x000000ff) >> 0;
57 int P = (ctrl & 0x00070000) >> 16;
58 u32 ref = 27000, clk = 0;
60 if ((ctrl & 0x80000000) && M1) {
62 if ((ctrl & 0x40000100) == 0x40000000) {
74 read_clk(struct drm_device *dev, u32 src)
78 return read_pll_2(dev, 0x004000);
80 return read_pll_1(dev, 0x004008);
89 nv40_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
91 u32 ctrl = nv_rd32(dev, 0x00c040);
93 perflvl->core = read_clk(dev, (ctrl & 0x00000003) >> 0);
94 perflvl->shader = read_clk(dev, (ctrl & 0x00000030) >> 4);
95 perflvl->memory = read_pll_2(dev, 0x4020);
99 struct nv40_pm_state {
109 nv40_calc_pll(struct drm_device *dev, u32 reg, struct pll_lims *pll,
110 u32 clk, int *N1, int *M1, int *N2, int *M2, int *log2P)
112 struct nouveau_pll_vals coef;
115 ret = get_pll_limits(dev, reg, pll);
119 if (clk < pll->vco1.maxfreq)
120 pll->vco2.maxfreq = 0;
122 ret = nouveau_calc_pll_mnp(dev, pll, clk, &coef);
129 if (pll->vco2.maxfreq) {
142 nv40_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
144 struct nv40_pm_state *info;
146 int N1, N2, M1, M2, log2P;
149 info = kmalloc(sizeof(*info), GFP_KERNEL);
151 return ERR_PTR(-ENOMEM);
153 /* core/geometric clock */
154 ret = nv40_calc_pll(dev, 0x004000, &pll, perflvl->core,
155 &N1, &M1, &N2, &M2, &log2P);
160 info->npll_ctrl = 0x80000100 | (log2P << 16);
161 info->npll_coef = (N1 << 8) | M1;
163 info->npll_ctrl = 0xc0000000 | (log2P << 16);
164 info->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
167 /* use the second PLL for shader/rop clock, if it differs from core */
168 if (perflvl->shader && perflvl->shader != perflvl->core) {
169 ret = nv40_calc_pll(dev, 0x004008, &pll, perflvl->shader,
170 &N1, &M1, NULL, NULL, &log2P);
174 info->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1;
175 info->ctrl = 0x00000223;
177 info->spll = 0x00000000;
178 info->ctrl = 0x00000333;
182 if (!perflvl->memory) {
183 info->mpll_ctrl = 0x00000000;
187 ret = nv40_calc_pll(dev, 0x004020, &pll, perflvl->memory,
188 &N1, &M1, &N2, &M2, &log2P);
192 info->mpll_ctrl = 0x80000000 | (log2P << 16);
193 info->mpll_ctrl |= min2(pll.log2p_bias + log2P, pll.max_log2p) << 20;
195 info->mpll_ctrl |= 0x00000100;
196 info->mpll_coef = (N1 << 8) | M1;
198 info->mpll_ctrl |= 0x40000000;
199 info->mpll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
211 nv40_pm_gr_idle(void *data)
213 struct drm_device *dev = data;
215 if ((nv_rd32(dev, 0x400760) & 0x000000f0) >> 4 !=
216 (nv_rd32(dev, 0x400760) & 0x0000000f))
219 if (nv_rd32(dev, 0x400700))
226 nv40_pm_clocks_set(struct drm_device *dev, void *pre_state)
228 struct drm_nouveau_private *dev_priv = dev->dev_private;
229 struct nv40_pm_state *info = pre_state;
236 /* determine which CRTCs are active, fetch VGA_SR1 for each */
237 for (i = 0; i < 2; i++) {
238 u32 vbl = nv_rd32(dev, 0x600808 + (i * 0x2000));
241 if (vbl != nv_rd32(dev, 0x600808 + (i * 0x2000))) {
242 nv_wr08(dev, 0x0c03c4 + (i * 0x2000), 0x01);
243 sr1[i] = nv_rd08(dev, 0x0c03c5 + (i * 0x2000));
244 if (!(sr1[i] & 0x20))
245 crtc_mask |= (1 << i);
249 } while (cnt++ < 32);
252 /* halt and idle engines */
253 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
254 nv_mask(dev, 0x002500, 0x00000001, 0x00000000);
255 if (!nv_wait(dev, 0x002500, 0x00000010, 0x00000000))
257 nv_mask(dev, 0x003220, 0x00000001, 0x00000000);
258 if (!nv_wait(dev, 0x003220, 0x00000010, 0x00000000))
260 nv_mask(dev, 0x003200, 0x00000001, 0x00000000);
261 nv04_fifo_cache_pull(dev, false);
263 if (!nv_wait_cb(dev, nv40_pm_gr_idle, dev))
266 /* set engine clocks */
267 nv_mask(dev, 0x00c040, 0x00000333, 0x00000000);
268 nv_wr32(dev, 0x004004, info->npll_coef);
269 nv_mask(dev, 0x004000, 0xc0070100, info->npll_ctrl);
270 nv_mask(dev, 0x004008, 0xc007ffff, info->spll);
272 nv_mask(dev, 0x00c040, 0x00000333, info->ctrl);
274 if (!info->mpll_ctrl)
277 /* wait for vblank start on active crtcs, disable memory access */
278 for (i = 0; i < 2; i++) {
279 if (!(crtc_mask & (1 << i)))
281 nv_wait(dev, 0x600808 + (i * 0x2000), 0x00010000, 0x00000000);
282 nv_wait(dev, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);
283 nv_wr08(dev, 0x0c03c4 + (i * 0x2000), 0x01);
284 nv_wr08(dev, 0x0c03c5 + (i * 0x2000), sr1[i] | 0x20);
287 /* prepare ram for reclocking */
288 nv_wr32(dev, 0x1002d4, 0x00000001); /* precharge */
289 nv_wr32(dev, 0x1002d0, 0x00000001); /* refresh */
290 nv_wr32(dev, 0x1002d0, 0x00000001); /* refresh */
291 nv_mask(dev, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */
292 nv_wr32(dev, 0x1002dc, 0x00000001); /* enable self-refresh */
294 /* change the PLL of each memory partition */
295 nv_mask(dev, 0x00c040, 0x0000c000, 0x00000000);
296 switch (dev_priv->chipset) {
302 nv_mask(dev, 0x004044, 0xc0771100, info->mpll_ctrl);
303 nv_mask(dev, 0x00402c, 0xc0771100, info->mpll_ctrl);
304 nv_wr32(dev, 0x004048, info->mpll_coef);
305 nv_wr32(dev, 0x004030, info->mpll_coef);
309 nv_mask(dev, 0x004038, 0xc0771100, info->mpll_ctrl);
310 nv_wr32(dev, 0x00403c, info->mpll_coef);
312 nv_mask(dev, 0x004020, 0xc0771100, info->mpll_ctrl);
313 nv_wr32(dev, 0x004024, info->mpll_coef);
317 nv_mask(dev, 0x00c040, 0x0000c000, 0x0000c000);
319 /* re-enable normal operation of memory controller */
320 nv_wr32(dev, 0x1002dc, 0x00000000);
321 nv_mask(dev, 0x100210, 0x80000000, 0x80000000);
324 /* execute memory reset script from vbios */
325 if (!bit_table(dev, 'M', &M))
326 nouveau_bios_init_exec(dev, ROM16(M.data[0]));
328 /* make sure we're in vblank (hopefully the same one as before), and
329 * then re-enable crtc memory access
331 for (i = 0; i < 2; i++) {
332 if (!(crtc_mask & (1 << i)))
334 nv_wait(dev, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);
335 nv_wr08(dev, 0x0c03c4 + (i * 0x2000), 0x01);
336 nv_wr08(dev, 0x0c03c5 + (i * 0x2000), sr1[i]);
341 nv_wr32(dev, 0x003250, 0x00000001);
342 nv_mask(dev, 0x003220, 0x00000001, 0x00000001);
343 nv_wr32(dev, 0x003200, 0x00000001);
344 nv_wr32(dev, 0x002500, 0x00000001);
345 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);