drivers/gpu/drm/nouveau/nv50_display.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <linux/dma-mapping.h>
  26
  27 #include <drm/drmP.h>
  28 #include <drm/drm_atomic.h>
  29 #include <drm/drm_atomic_helper.h>
  30 #include <drm/drm_crtc_helper.h>
  31 #include <drm/drm_dp_helper.h>
  32 #include <drm/drm_fb_helper.h>
  33 #include <drm/drm_plane_helper.h>
  34
  35 #include <nvif/class.h>
  36 #include <nvif/cl0002.h>
  37 #include <nvif/cl5070.h>
  38 #include <nvif/cl507a.h>
  39 #include <nvif/cl507b.h>
  40 #include <nvif/cl507c.h>
  41 #include <nvif/cl507d.h>
  42 #include <nvif/cl507e.h>
  43 #include <nvif/event.h>
  44
  45 #include "nouveau_drv.h"
  46 #include "nouveau_dma.h"
  47 #include "nouveau_gem.h"
  48 #include "nouveau_connector.h"
  49 #include "nouveau_encoder.h"
  50 #include "nouveau_crtc.h"
  51 #include "nouveau_fence.h"
  52 #include "nouveau_fbcon.h"
  53 #include "nv50_display.h"
  54
  55 #define EVO_DMA_NR 9
  56
  57 #define EVO_MASTER  (0x00)
  58 #define EVO_FLIP(c) (0x01 + (c))
  59 #define EVO_OVLY(c) (0x05 + (c))
  60 #define EVO_OIMM(c) (0x09 + (c))
  61 #define EVO_CURS(c) (0x0d + (c))
  62
  63 /* offsets in shared sync bo of various structures */
  64 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
  65 #define EVO_MAST_NTFY     EVO_SYNC(      0, 0x00)
  66 #define EVO_FLIP_SEM0(c)  EVO_SYNC((c) + 1, 0x00)
  67 #define EVO_FLIP_SEM1(c)  EVO_SYNC((c) + 1, 0x10)
  68 #define EVO_FLIP_NTFY0(c) EVO_SYNC((c) + 1, 0x20)
  69 #define EVO_FLIP_NTFY1(c) EVO_SYNC((c) + 1, 0x30)
  70
  71 /******************************************************************************
  72  * Atomic state
  73  *****************************************************************************/
  74 #define nv50_atom(p) container_of((p), struct nv50_atom, state)
  75
  76 struct nv50_atom {
  77         struct drm_atomic_state state;
  78
  79         struct list_head outp;
  80         bool lock_core;
  81         bool flush_disable;
  82 };
  83
  84 struct nv50_outp_atom {
  85         struct list_head head;
  86
  87         struct drm_encoder *encoder;
  88         bool flush_disable;
  89
  90         union {
  91                 struct {
  92                         bool ctrl:1;
  93                 };
  94                 u8 mask;
  95         } clr;
  96
  97         union {
  98                 struct {
  99                         bool ctrl:1;
 100                 };
 101                 u8 mask;
 102         } set;
 103 };
 104
 105 #define nv50_head_atom(p) container_of((p), struct nv50_head_atom, state)
 106
 107 struct nv50_head_atom {
 108         struct drm_crtc_state state;
 109
 110         struct {
 111                 u16 iW;
 112                 u16 iH;
 113                 u16 oW;
 114                 u16 oH;
 115         } view;
 116
 117         struct nv50_head_mode {
 118                 bool interlace;
 119                 u32 clock;
 120                 struct {
 121                         u16 active;
 122                         u16 synce;
 123                         u16 blanke;
 124                         u16 blanks;
 125                 } h;
 126                 struct {
 127                         u32 active;
 128                         u16 synce;
 129                         u16 blanke;
 130                         u16 blanks;
 131                         u16 blank2s;
 132                         u16 blank2e;
 133                         u16 blankus;
 134                 } v;
 135         } mode;
 136
 137         struct {
 138                 u32 handle;
 139                 u64 offset:40;
 140         } lut;
 141
 142         struct {
 143                 bool visible;
 144                 u32 handle;
 145                 u64 offset:40;
 146                 u8  format;
 147                 u8  kind:7;
 148                 u8  layout:1;
 149                 u8  block:4;
 150                 u32 pitch:20;
 151                 u16 x;
 152                 u16 y;
 153                 u16 w;
 154                 u16 h;
 155         } core;
 156
 157         struct {
 158                 bool visible;
 159                 u32 handle;
 160                 u64 offset:40;
 161                 u8  layout:1;
 162                 u8  format:1;
 163         } curs;
 164
 165         struct {
 166                 u8  depth;
 167                 u8  cpp;
 168                 u16 x;
 169                 u16 y;
 170                 u16 w;
 171                 u16 h;
 172         } base;
 173
 174         struct {
 175                 u8 cpp;
 176         } ovly;
 177
 178         struct {
 179                 bool enable:1;
 180                 u8 bits:2;
 181                 u8 mode:4;
 182         } dither;
 183
 184         struct {
 185                 struct {
 186                         u16 cos:12;
 187                         u16 sin:12;
 188                 } sat;
 189         } procamp;
 190
 191         union {
 192                 struct {
 193                         bool core:1;
 194                         bool curs:1;
 195                 };
 196                 u8 mask;
 197         } clr;
 198
 199         union {
 200                 struct {
 201                         bool core:1;
 202                         bool curs:1;
 203                         bool view:1;
 204                         bool mode:1;
 205                         bool base:1;
 206                         bool ovly:1;
 207                         bool dither:1;
 208                         bool procamp:1;
 209                 };
 210                 u16 mask;
 211         } set;
 212 };
 213
 214 static inline struct nv50_head_atom *
 215 nv50_head_atom_get(struct drm_atomic_state *state, struct drm_crtc *crtc)
 216 {
 217         struct drm_crtc_state *statec = drm_atomic_get_crtc_state(state, crtc);
 218         if (IS_ERR(statec))
 219                 return (void *)statec;
 220         return nv50_head_atom(statec);
 221 }
 222
 223 #define nv50_wndw_atom(p) container_of((p), struct nv50_wndw_atom, state)
 224
 225 struct nv50_wndw_atom {
 226         struct drm_plane_state state;
 227         u8 interval;
 228
 229         struct drm_rect clip;
 230
 231         struct {
 232                 u32  handle;
 233                 u16  offset:12;
 234                 bool awaken:1;
 235         } ntfy;
 236
 237         struct {
 238                 u32 handle;
 239                 u16 offset:12;
 240                 u32 acquire;
 241                 u32 release;
 242         } sema;
 243
 244         struct {
 245                 u8 enable:2;
 246         } lut;
 247
 248         struct {
 249                 u8  mode:2;
 250                 u8  interval:4;
 251
 252                 u8  format;
 253                 u8  kind:7;
 254                 u8  layout:1;
 255                 u8  block:4;
 256                 u32 pitch:20;
 257                 u16 w;
 258                 u16 h;
 259
 260                 u32 handle;
 261                 u64 offset;
 262         } image;
 263
 264         struct {
 265                 u16 x;
 266                 u16 y;
 267         } point;
 268
 269         union {
 270                 struct {
 271                         bool ntfy:1;
 272                         bool sema:1;
 273                         bool image:1;
 274                 };
 275                 u8 mask;
 276         } clr;
 277
 278         union {
 279                 struct {
 280                         bool ntfy:1;
 281                         bool sema:1;
 282                         bool image:1;
 283                         bool lut:1;
 284                         bool point:1;
 285                 };
 286                 u8 mask;
 287         } set;
 288 };
 289
 290 /******************************************************************************
 291  * EVO channel
 292  *****************************************************************************/
 293
 294 struct nv50_chan {
 295         struct nvif_object user;
 296         struct nvif_device *device;
 297 };
 298
 299 static int
 300 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
 301                  const s32 *oclass, u8 head, void *data, u32 size,
 302                  struct nv50_chan *chan)
 303 {
 304         struct nvif_sclass *sclass;
 305         int ret, i, n;
 306
 307         chan->device = device;
 308
 309         ret = n = nvif_object_sclass_get(disp, &sclass);
 310         if (ret < 0)
 311                 return ret;
 312
 313         while (oclass[0]) {
 314                 for (i = 0; i < n; i++) {
 315                         if (sclass[i].oclass == oclass[0]) {
 316                                 ret = nvif_object_init(disp, 0, oclass[0],
 317                                                        data, size, &chan->user);
 318                                 if (ret == 0)
 319                                         nvif_object_map(&chan->user);
 320                                 nvif_object_sclass_put(&sclass);
 321                                 return ret;
 322                         }
 323                 }
 324                 oclass++;
 325         }
 326
 327         nvif_object_sclass_put(&sclass);
 328         return -ENOSYS;
 329 }
 330
 331 static void
 332 nv50_chan_destroy(struct nv50_chan *chan)
 333 {
 334         nvif_object_fini(&chan->user);
 335 }
 336
 337 /******************************************************************************
 338  * PIO EVO channel
 339  *****************************************************************************/
 340
 341 struct nv50_pioc {
 342         struct nv50_chan base;
 343 };
 344
 345 static void
 346 nv50_pioc_destroy(struct nv50_pioc *pioc)
 347 {
 348         nv50_chan_destroy(&pioc->base);
 349 }
 350
 351 static int
 352 nv50_pioc_create(struct nvif_device *device, struct nvif_object *disp,
 353                  const s32 *oclass, u8 head, void *data, u32 size,
 354                  struct nv50_pioc *pioc)
 355 {
 356         return nv50_chan_create(device, disp, oclass, head, data, size,
 357                                 &pioc->base);
 358 }
 359
 360 /******************************************************************************
 361  * Overlay Immediate
 362  *****************************************************************************/
 363
 364 struct nv50_oimm {
 365         struct nv50_pioc base;
 366 };
 367
 368 static int
 369 nv50_oimm_create(struct nvif_device *device, struct nvif_object *disp,
 370                  int head, struct nv50_oimm *oimm)
 371 {
 372         struct nv50_disp_cursor_v0 args = {
 373                 .head = head,
 374         };
 375         static const s32 oclass[] = {
 376                 GK104_DISP_OVERLAY,
 377                 GF110_DISP_OVERLAY,
 378                 GT214_DISP_OVERLAY,
 379                 G82_DISP_OVERLAY,
 380                 NV50_DISP_OVERLAY,
 381                 0
 382         };
 383
 384         return nv50_pioc_create(device, disp, oclass, head, &args, sizeof(args),
 385                                 &oimm->base);
 386 }
 387
 388 /******************************************************************************
 389  * DMA EVO channel
 390  *****************************************************************************/
 391
 392 struct nv50_dmac_ctxdma {
 393         struct list_head head;
 394         struct nvif_object object;
 395 };
 396
 397 struct nv50_dmac {
 398         struct nv50_chan base;
 399         dma_addr_t handle;
 400         u32 *ptr;
 401
 402         struct nvif_object sync;
 403         struct nvif_object vram;
 404         struct list_head ctxdma;
 405
 406         /* Protects against concurrent pushbuf access to this channel, lock is
 407          * grabbed by evo_wait (if the pushbuf reservation is successful) and
 408          * dropped again by evo_kick. */
 409         struct mutex lock;
 410 };
 411
 412 static void
 413 nv50_dmac_ctxdma_del(struct nv50_dmac_ctxdma *ctxdma)
 414 {
 415         nvif_object_fini(&ctxdma->object);
 416         list_del(&ctxdma->head);
 417         kfree(ctxdma);
 418 }
 419
 420 static struct nv50_dmac_ctxdma *
 421 nv50_dmac_ctxdma_new(struct nv50_dmac *dmac, struct nouveau_framebuffer *fb)
 422 {
 423         struct nouveau_drm *drm = nouveau_drm(fb->base.dev);
 424         struct nv50_dmac_ctxdma *ctxdma;
 425         const u8    kind = (fb->nvbo->tile_flags & 0x0000ff00) >> 8;
 426         const u32 handle = 0xfb000000 | kind;
 427         struct {
 428                 struct nv_dma_v0 base;
 429                 union {
 430                         struct nv50_dma_v0 nv50;
 431                         struct gf100_dma_v0 gf100;
 432                         struct gf119_dma_v0 gf119;
 433                 };
 434         } args = {};
 435         u32 argc = sizeof(args.base);
 436         int ret;
 437
 438         list_for_each_entry(ctxdma, &dmac->ctxdma, head) {
 439                 if (ctxdma->object.handle == handle)
 440                         return ctxdma;
 441         }
 442
 443         if (!(ctxdma = kzalloc(sizeof(*ctxdma), GFP_KERNEL)))
 444                 return ERR_PTR(-ENOMEM);
 445         list_add(&ctxdma->head, &dmac->ctxdma);
 446
 447         args.base.target = NV_DMA_V0_TARGET_VRAM;
 448         args.base.access = NV_DMA_V0_ACCESS_RDWR;
 449         args.base.start  = 0;
 450         args.base.limit  = drm->client.device.info.ram_user - 1;
 451
 452         if (drm->client.device.info.chipset < 0x80) {
 453                 args.nv50.part = NV50_DMA_V0_PART_256;
 454                 argc += sizeof(args.nv50);
 455         } else
 456         if (drm->client.device.info.chipset < 0xc0) {
 457                 args.nv50.part = NV50_DMA_V0_PART_256;
 458                 args.nv50.kind = kind;
 459                 argc += sizeof(args.nv50);
 460         } else
 461         if (drm->client.device.info.chipset < 0xd0) {
 462                 args.gf100.kind = kind;
 463                 argc += sizeof(args.gf100);
 464         } else {
 465                 args.gf119.page = GF119_DMA_V0_PAGE_LP;
 466                 args.gf119.kind = kind;
 467                 argc += sizeof(args.gf119);
 468         }
 469
 470         ret = nvif_object_init(&dmac->base.user, handle, NV_DMA_IN_MEMORY,
 471                                &args, argc, &ctxdma->object);
 472         if (ret) {
 473                 nv50_dmac_ctxdma_del(ctxdma);
 474                 return ERR_PTR(ret);
 475         }
 476
 477         return ctxdma;
 478 }
 479
 480 static void
 481 nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp)
 482 {
 483         struct nvif_device *device = dmac->base.device;
 484         struct nv50_dmac_ctxdma *ctxdma, *ctxtmp;
 485
 486         list_for_each_entry_safe(ctxdma, ctxtmp, &dmac->ctxdma, head) {
 487                 nv50_dmac_ctxdma_del(ctxdma);
 488         }
 489
 490         nvif_object_fini(&dmac->vram);
 491         nvif_object_fini(&dmac->sync);
 492
 493         nv50_chan_destroy(&dmac->base);
 494
 495         if (dmac->ptr) {
 496                 struct device *dev = nvxx_device(device)->dev;
 497                 dma_free_coherent(dev, PAGE_SIZE, dmac->ptr, dmac->handle);
 498         }
 499 }
 500
 501 static int
 502 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 503                  const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
 504                  struct nv50_dmac *dmac)
 505 {
 506         struct nv50_disp_core_channel_dma_v0 *args = data;
 507         struct nvif_object pushbuf;
 508         int ret;
 509
 510         mutex_init(&dmac->lock);
 511
 512         dmac->ptr = dma_alloc_coherent(nvxx_device(device)->dev, PAGE_SIZE,
 513                                        &dmac->handle, GFP_KERNEL);
 514         if (!dmac->ptr)
 515                 return -ENOMEM;
 516
 517         ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY,
 518                                &(struct nv_dma_v0) {
 519                                         .target = NV_DMA_V0_TARGET_PCI_US,
 520                                         .access = NV_DMA_V0_ACCESS_RD,
 521                                         .start = dmac->handle + 0x0000,
 522                                         .limit = dmac->handle + 0x0fff,
 523                                }, sizeof(struct nv_dma_v0), &pushbuf);
 524         if (ret)
 525                 return ret;
 526
 527         args->pushbuf = nvif_handle(&pushbuf);
 528
 529         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 530                                &dmac->base);
 531         nvif_object_fini(&pushbuf);
 532         if (ret)
 533                 return ret;
 534
 535         ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
 536                                &(struct nv_dma_v0) {
 537                                         .target = NV_DMA_V0_TARGET_VRAM,
 538                                         .access = NV_DMA_V0_ACCESS_RDWR,
 539                                         .start = syncbuf + 0x0000,
 540                                         .limit = syncbuf + 0x0fff,
 541                                }, sizeof(struct nv_dma_v0),
 542                                &dmac->sync);
 543         if (ret)
 544                 return ret;
 545
 546         ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
 547                                &(struct nv_dma_v0) {
 548                                         .target = NV_DMA_V0_TARGET_VRAM,
 549                                         .access = NV_DMA_V0_ACCESS_RDWR,
 550                                         .start = 0,
 551                                         .limit = device->info.ram_user - 1,
 552                                }, sizeof(struct nv_dma_v0),
 553                                &dmac->vram);
 554         if (ret)
 555                 return ret;
 556
 557         INIT_LIST_HEAD(&dmac->ctxdma);
 558         return ret;
 559 }
 560
 561 /******************************************************************************
 562  * Core
 563  *****************************************************************************/
 564
 565 struct nv50_mast {
 566         struct nv50_dmac base;
 567 };
 568
 569 static int
 570 nv50_core_create(struct nvif_device *device, struct nvif_object *disp,
 571                  u64 syncbuf, struct nv50_mast *core)
 572 {
 573         struct nv50_disp_core_channel_dma_v0 args = {
 574                 .pushbuf = 0xb0007d00,
 575         };
 576         static const s32 oclass[] = {
 577                 GP102_DISP_CORE_CHANNEL_DMA,
 578                 GP100_DISP_CORE_CHANNEL_DMA,
 579                 GM200_DISP_CORE_CHANNEL_DMA,
 580                 GM107_DISP_CORE_CHANNEL_DMA,
 581                 GK110_DISP_CORE_CHANNEL_DMA,
 582                 GK104_DISP_CORE_CHANNEL_DMA,
 583                 GF110_DISP_CORE_CHANNEL_DMA,
 584                 GT214_DISP_CORE_CHANNEL_DMA,
 585                 GT206_DISP_CORE_CHANNEL_DMA,
 586                 GT200_DISP_CORE_CHANNEL_DMA,
 587                 G82_DISP_CORE_CHANNEL_DMA,
 588                 NV50_DISP_CORE_CHANNEL_DMA,
 589                 0
 590         };
 591
 592         return nv50_dmac_create(device, disp, oclass, 0, &args, sizeof(args),
 593                                 syncbuf, &core->base);
 594 }
 595
 596 /******************************************************************************
 597  * Base
 598  *****************************************************************************/
 599
 600 struct nv50_sync {
 601         struct nv50_dmac base;
 602         u32 addr;
 603         u32 data;
 604 };
 605
 606 static int
 607 nv50_base_create(struct nvif_device *device, struct nvif_object *disp,
 608                  int head, u64 syncbuf, struct nv50_sync *base)
 609 {
 610         struct nv50_disp_base_channel_dma_v0 args = {
 611                 .pushbuf = 0xb0007c00 | head,
 612                 .head = head,
 613         };
 614         static const s32 oclass[] = {
 615                 GK110_DISP_BASE_CHANNEL_DMA,
 616                 GK104_DISP_BASE_CHANNEL_DMA,
 617                 GF110_DISP_BASE_CHANNEL_DMA,
 618                 GT214_DISP_BASE_CHANNEL_DMA,
 619                 GT200_DISP_BASE_CHANNEL_DMA,
 620                 G82_DISP_BASE_CHANNEL_DMA,
 621                 NV50_DISP_BASE_CHANNEL_DMA,
 622                 0
 623         };
 624
 625         return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
 626                                 syncbuf, &base->base);
 627 }
 628
 629 /******************************************************************************
 630  * Overlay
 631  *****************************************************************************/
 632
 633 struct nv50_ovly {
 634         struct nv50_dmac base;
 635 };
 636
 637 static int
 638 nv50_ovly_create(struct nvif_device *device, struct nvif_object *disp,
 639                  int head, u64 syncbuf, struct nv50_ovly *ovly)
 640 {
 641         struct nv50_disp_overlay_channel_dma_v0 args = {
 642                 .pushbuf = 0xb0007e00 | head,
 643                 .head = head,
 644         };
 645         static const s32 oclass[] = {
 646                 GK104_DISP_OVERLAY_CONTROL_DMA,
 647                 GF110_DISP_OVERLAY_CONTROL_DMA,
 648                 GT214_DISP_OVERLAY_CHANNEL_DMA,
 649                 GT200_DISP_OVERLAY_CHANNEL_DMA,
 650                 G82_DISP_OVERLAY_CHANNEL_DMA,
 651                 NV50_DISP_OVERLAY_CHANNEL_DMA,
 652                 0
 653         };
 654
 655         return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
 656                                 syncbuf, &ovly->base);
 657 }
 658
 659 struct nv50_head {
 660         struct nouveau_crtc base;
 661         struct nv50_ovly ovly;
 662         struct nv50_oimm oimm;
 663 };
 664
 665 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
 666 #define nv50_ovly(c) (&nv50_head(c)->ovly)
 667 #define nv50_oimm(c) (&nv50_head(c)->oimm)
 668 #define nv50_chan(c) (&(c)->base.base)
 669 #define nv50_vers(c) nv50_chan(c)->user.oclass
 670
 671 struct nv50_disp {
 672         struct nvif_object *disp;
 673         struct nv50_mast mast;
 674
 675         struct nouveau_bo *sync;
 676
 677         struct mutex mutex;
 678 };
 679
 680 static struct nv50_disp *
 681 nv50_disp(struct drm_device *dev)
 682 {
 683         return nouveau_display(dev)->priv;
 684 }
 685
 686 #define nv50_mast(d) (&nv50_disp(d)->mast)
 687
 688 /******************************************************************************
 689  * EVO channel helpers
 690  *****************************************************************************/
 691 static u32 *
 692 evo_wait(void *evoc, int nr)
 693 {
 694         struct nv50_dmac *dmac = evoc;
 695         struct nvif_device *device = dmac->base.device;
 696         u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
 697
 698         mutex_lock(&dmac->lock);
 699         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 700                 dmac->ptr[put] = 0x20000000;
 701
 702                 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
 703                 if (nvif_msec(device, 2000,
 704                         if (!nvif_rd32(&dmac->base.user, 0x0004))
 705                                 break;
 706                 ) < 0) {
 707                         mutex_unlock(&dmac->lock);
 708                         pr_err("nouveau: evo channel stalled\n");
 709                         return NULL;
 710                 }
 711
 712                 put = 0;
 713         }
 714
 715         return dmac->ptr + put;
 716 }
 717
 718 static void
 719 evo_kick(u32 *push, void *evoc)
 720 {
 721         struct nv50_dmac *dmac = evoc;
 722         nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 723         mutex_unlock(&dmac->lock);
 724 }
 725
 726 #define evo_mthd(p, m, s) do {                                          \
 727         const u32 _m = (m), _s = (s);                                   \
 728         if (drm_debug & DRM_UT_KMS)                                     \
 729                 pr_err("%04x %d %s\n", _m, _s, __func__);               \
 730         *((p)++) = ((_s << 18) | _m);                                   \
 731 } while(0)
 732
 733 #define evo_data(p, d) do {                                             \
 734         const u32 _d = (d);                                             \
 735         if (drm_debug & DRM_UT_KMS)                                     \
 736                 pr_err("\t%08x\n", _d);                                 \
 737         *((p)++) = _d;                                                  \
 738 } while(0)
 739
 740 /******************************************************************************
 741  * Plane
 742  *****************************************************************************/
 743 #define nv50_wndw(p) container_of((p), struct nv50_wndw, plane)
 744
 745 struct nv50_wndw {
 746         const struct nv50_wndw_func *func;
 747         struct nv50_dmac *dmac;
 748
 749         struct drm_plane plane;
 750
 751         struct nvif_notify notify;
 752         u16 ntfy;
 753         u16 sema;
 754         u32 data;
 755 };
 756
 757 struct nv50_wndw_func {
 758         void *(*dtor)(struct nv50_wndw *);
 759         int (*acquire)(struct nv50_wndw *, struct nv50_wndw_atom *asyw,
 760                        struct nv50_head_atom *asyh);
 761         void (*release)(struct nv50_wndw *, struct nv50_wndw_atom *asyw,
 762                         struct nv50_head_atom *asyh);
 763         void (*prepare)(struct nv50_wndw *, struct nv50_head_atom *asyh,
 764                         struct nv50_wndw_atom *asyw);
 765
 766         void (*sema_set)(struct nv50_wndw *, struct nv50_wndw_atom *);
 767         void (*sema_clr)(struct nv50_wndw *);
 768         void (*ntfy_set)(struct nv50_wndw *, struct nv50_wndw_atom *);
 769         void (*ntfy_clr)(struct nv50_wndw *);
 770         int (*ntfy_wait_begun)(struct nv50_wndw *, struct nv50_wndw_atom *);
 771         void (*image_set)(struct nv50_wndw *, struct nv50_wndw_atom *);
 772         void (*image_clr)(struct nv50_wndw *);
 773         void (*lut)(struct nv50_wndw *, struct nv50_wndw_atom *);
 774         void (*point)(struct nv50_wndw *, struct nv50_wndw_atom *);
 775
 776         u32 (*update)(struct nv50_wndw *, u32 interlock);
 777 };
 778
 779 static int
 780 nv50_wndw_wait_armed(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
 781 {
 782         if (asyw->set.ntfy)
 783                 return wndw->func->ntfy_wait_begun(wndw, asyw);
 784         return 0;
 785 }
 786
 787 static u32
 788 nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 interlock, bool flush,
 789                     struct nv50_wndw_atom *asyw)
 790 {
 791         if (asyw->clr.sema && (!asyw->set.sema || flush))
 792                 wndw->func->sema_clr(wndw);
 793         if (asyw->clr.ntfy && (!asyw->set.ntfy || flush))
 794                 wndw->func->ntfy_clr(wndw);
 795         if (asyw->clr.image && (!asyw->set.image || flush))
 796                 wndw->func->image_clr(wndw);
 797
 798         return flush ? wndw->func->update(wndw, interlock) : 0;
 799 }
 800
 801 static u32
 802 nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 interlock,
 803                     struct nv50_wndw_atom *asyw)
 804 {
 805         if (interlock) {
 806                 asyw->image.mode = 0;
 807                 asyw->image.interval = 1;
 808         }
 809
 810         if (asyw->set.sema ) wndw->func->sema_set (wndw, asyw);
 811         if (asyw->set.ntfy ) wndw->func->ntfy_set (wndw, asyw);
 812         if (asyw->set.image) wndw->func->image_set(wndw, asyw);
 813         if (asyw->set.lut  ) wndw->func->lut      (wndw, asyw);
 814         if (asyw->set.point) wndw->func->point    (wndw, asyw);
 815
 816         return wndw->func->update(wndw, interlock);
 817 }
 818
 819 static void
 820 nv50_wndw_atomic_check_release(struct nv50_wndw *wndw,
 821                                struct nv50_wndw_atom *asyw,
 822                                struct nv50_head_atom *asyh)
 823 {
 824         struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
 825         NV_ATOMIC(drm, "%s release\n", wndw->plane.name);
 826         wndw->func->release(wndw, asyw, asyh);
 827         asyw->ntfy.handle = 0;
 828         asyw->sema.handle = 0;
 829 }
 830
 831 static int
 832 nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw,
 833                                struct nv50_wndw_atom *asyw,
 834                                struct nv50_head_atom *asyh)
 835 {
 836         struct nouveau_framebuffer *fb = nouveau_framebuffer(asyw->state.fb);
 837         struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
 838         int ret;
 839
 840         NV_ATOMIC(drm, "%s acquire\n", wndw->plane.name);
 841         asyw->clip.x1 = 0;
 842         asyw->clip.y1 = 0;
 843         asyw->clip.x2 = asyh->state.mode.hdisplay;
 844         asyw->clip.y2 = asyh->state.mode.vdisplay;
 845
 846         asyw->image.w = fb->base.width;
 847         asyw->image.h = fb->base.height;
 848         asyw->image.kind = (fb->nvbo->tile_flags & 0x0000ff00) >> 8;
 849
 850         if (asyh->state.pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC)
 851                 asyw->interval = 0;
 852         else
 853                 asyw->interval = 1;
 854
 855         if (asyw->image.kind) {
 856                 asyw->image.layout = 0;
 857                 if (drm->client.device.info.chipset >= 0xc0)
 858                         asyw->image.block = fb->nvbo->tile_mode >> 4;
 859                 else
 860                         asyw->image.block = fb->nvbo->tile_mode;
 861                 asyw->image.pitch = (fb->base.pitches[0] / 4) << 4;
 862         } else {
 863                 asyw->image.layout = 1;
 864                 asyw->image.block  = 0;
 865                 asyw->image.pitch  = fb->base.pitches[0];
 866         }
 867
 868         ret = wndw->func->acquire(wndw, asyw, asyh);
 869         if (ret)
 870                 return ret;
 871
 872         if (asyw->set.image) {
 873                 if (!(asyw->image.mode = asyw->interval ? 0 : 1))
 874                         asyw->image.interval = asyw->interval;
 875                 else
 876                         asyw->image.interval = 0;
 877         }
 878
 879         return 0;
 880 }
 881
 882 static int
 883 nv50_wndw_atomic_check(struct drm_plane *plane, struct drm_plane_state *state)
 884 {
 885         struct nouveau_drm *drm = nouveau_drm(plane->dev);
 886         struct nv50_wndw *wndw = nv50_wndw(plane);
 887         struct nv50_wndw_atom *armw = nv50_wndw_atom(wndw->plane.state);
 888         struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
 889         struct nv50_head_atom *harm = NULL, *asyh = NULL;
 890         bool varm = false, asyv = false, asym = false;
 891         int ret;
 892
 893         NV_ATOMIC(drm, "%s atomic_check\n", plane->name);
 894         if (asyw->state.crtc) {
 895                 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
 896                 if (IS_ERR(asyh))
 897                         return PTR_ERR(asyh);
 898                 asym = drm_atomic_crtc_needs_modeset(&asyh->state);
 899                 asyv = asyh->state.active;
 900         }
 901
 902         if (armw->state.crtc) {
 903                 harm = nv50_head_atom_get(asyw->state.state, armw->state.crtc);
 904                 if (IS_ERR(harm))
 905                         return PTR_ERR(harm);
 906                 varm = harm->state.crtc->state->active;
 907         }
 908
 909         if (asyv) {
 910                 asyw->point.x = asyw->state.crtc_x;
 911                 asyw->point.y = asyw->state.crtc_y;
 912                 if (memcmp(&armw->point, &asyw->point, sizeof(asyw->point)))
 913                         asyw->set.point = true;
 914
 915                 ret = nv50_wndw_atomic_check_acquire(wndw, asyw, asyh);
 916                 if (ret)
 917                         return ret;
 918         } else
 919         if (varm) {
 920                 nv50_wndw_atomic_check_release(wndw, asyw, harm);
 921         } else {
 922                 return 0;
 923         }
 924
 925         if (!asyv || asym) {
 926                 asyw->clr.ntfy = armw->ntfy.handle != 0;
 927                 asyw->clr.sema = armw->sema.handle != 0;
 928                 if (wndw->func->image_clr)
 929                         asyw->clr.image = armw->image.handle != 0;
 930                 asyw->set.lut = wndw->func->lut && asyv;
 931         }
 932
 933         return 0;
 934 }
 935
 936 static void
 937 nv50_wndw_cleanup_fb(struct drm_plane *plane, struct drm_plane_state *old_state)
 938 {
 939         struct nouveau_framebuffer *fb = nouveau_framebuffer(old_state->fb);
 940         struct nouveau_drm *drm = nouveau_drm(plane->dev);
 941
 942         NV_ATOMIC(drm, "%s cleanup: %p\n", plane->name, old_state->fb);
 943         if (!old_state->fb)
 944                 return;
 945
 946         nouveau_bo_unpin(fb->nvbo);
 947 }
 948
 949 static int
 950 nv50_wndw_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state)
 951 {
 952         struct nouveau_framebuffer *fb = nouveau_framebuffer(state->fb);
 953         struct nouveau_drm *drm = nouveau_drm(plane->dev);
 954         struct nv50_wndw *wndw = nv50_wndw(plane);
 955         struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
 956         struct nv50_head_atom *asyh;
 957         struct nv50_dmac_ctxdma *ctxdma;
 958         int ret;
 959
 960         NV_ATOMIC(drm, "%s prepare: %p\n", plane->name, state->fb);
 961         if (!asyw->state.fb)
 962                 return 0;
 963
 964         ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM, true);
 965         if (ret)
 966                 return ret;
 967
 968         ctxdma = nv50_dmac_ctxdma_new(wndw->dmac, fb);
 969         if (IS_ERR(ctxdma)) {
 970                 nouveau_bo_unpin(fb->nvbo);
 971                 return PTR_ERR(ctxdma);
 972         }
 973
 974         asyw->state.fence = reservation_object_get_excl_rcu(fb->nvbo->bo.resv);
 975         asyw->image.handle = ctxdma->object.handle;
 976         asyw->image.offset = fb->nvbo->bo.offset;
 977
 978         if (wndw->func->prepare) {
 979                 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
 980                 if (IS_ERR(asyh))
 981                         return PTR_ERR(asyh);
 982
 983                 wndw->func->prepare(wndw, asyh, asyw);
 984         }
 985
 986         return 0;
 987 }
 988
 989 static const struct drm_plane_helper_funcs
 990 nv50_wndw_helper = {
 991         .prepare_fb = nv50_wndw_prepare_fb,
 992         .cleanup_fb = nv50_wndw_cleanup_fb,
 993         .atomic_check = nv50_wndw_atomic_check,
 994 };
 995
 996 static void
 997 nv50_wndw_atomic_destroy_state(struct drm_plane *plane,
 998                                struct drm_plane_state *state)
 999 {
1000         struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
1001         __drm_atomic_helper_plane_destroy_state(&asyw->state);
1002         kfree(asyw);
1003 }
1004
1005 static struct drm_plane_state *
1006 nv50_wndw_atomic_duplicate_state(struct drm_plane *plane)
1007 {
1008         struct nv50_wndw_atom *armw = nv50_wndw_atom(plane->state);
1009         struct nv50_wndw_atom *asyw;
1010         if (!(asyw = kmalloc(sizeof(*asyw), GFP_KERNEL)))
1011                 return NULL;
1012         __drm_atomic_helper_plane_duplicate_state(plane, &asyw->state);
1013         asyw->interval = 1;
1014         asyw->sema = armw->sema;
1015         asyw->ntfy = armw->ntfy;
1016         asyw->image = armw->image;
1017         asyw->point = armw->point;
1018         asyw->lut = armw->lut;
1019         asyw->clr.mask = 0;
1020         asyw->set.mask = 0;
1021         return &asyw->state;
1022 }
1023
1024 static void
1025 nv50_wndw_reset(struct drm_plane *plane)
1026 {
1027         struct nv50_wndw_atom *asyw;
1028
1029         if (WARN_ON(!(asyw = kzalloc(sizeof(*asyw), GFP_KERNEL))))
1030                 return;
1031
1032         if (plane->state)
1033                 plane->funcs->atomic_destroy_state(plane, plane->state);
1034         plane->state = &asyw->state;
1035         plane->state->plane = plane;
1036         plane->state->rotation = DRM_ROTATE_0;
1037 }
1038
1039 static void
1040 nv50_wndw_destroy(struct drm_plane *plane)
1041 {
1042         struct nv50_wndw *wndw = nv50_wndw(plane);
1043         void *data;
1044         nvif_notify_fini(&wndw->notify);
1045         data = wndw->func->dtor(wndw);
1046         drm_plane_cleanup(&wndw->plane);
1047         kfree(data);
1048 }
1049
1050 static const struct drm_plane_funcs
1051 nv50_wndw = {
1052         .update_plane = drm_atomic_helper_update_plane,
1053         .disable_plane = drm_atomic_helper_disable_plane,
1054         .destroy = nv50_wndw_destroy,
1055         .reset = nv50_wndw_reset,
1056         .set_property = drm_atomic_helper_plane_set_property,
1057         .atomic_duplicate_state = nv50_wndw_atomic_duplicate_state,
1058         .atomic_destroy_state = nv50_wndw_atomic_destroy_state,
1059 };
1060
1061 static void
1062 nv50_wndw_fini(struct nv50_wndw *wndw)
1063 {
1064         nvif_notify_put(&wndw->notify);
1065 }
1066
1067 static void
1068 nv50_wndw_init(struct nv50_wndw *wndw)
1069 {
1070         nvif_notify_get(&wndw->notify);
1071 }
1072
1073 static int
1074 nv50_wndw_ctor(const struct nv50_wndw_func *func, struct drm_device *dev,
1075                enum drm_plane_type type, const char *name, int index,
1076                struct nv50_dmac *dmac, const u32 *format, int nformat,
1077                struct nv50_wndw *wndw)
1078 {
1079         int ret;
1080
1081         wndw->func = func;
1082         wndw->dmac = dmac;
1083
1084         ret = drm_universal_plane_init(dev, &wndw->plane, 0, &nv50_wndw, format,
1085                                        nformat, type, "%s-%d", name, index);
1086         if (ret)
1087                 return ret;
1088
1089         drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper);
1090         return 0;
1091 }
1092
1093 /******************************************************************************
1094  * Cursor plane
1095  *****************************************************************************/
1096 #define nv50_curs(p) container_of((p), struct nv50_curs, wndw)
1097
1098 struct nv50_curs {
1099         struct nv50_wndw wndw;
1100         struct nvif_object chan;
1101 };
1102
1103 static u32
1104 nv50_curs_update(struct nv50_wndw *wndw, u32 interlock)
1105 {
1106         struct nv50_curs *curs = nv50_curs(wndw);
1107         nvif_wr32(&curs->chan, 0x0080, 0x00000000);
1108         return 0;
1109 }
1110
1111 static void
1112 nv50_curs_point(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1113 {
1114         struct nv50_curs *curs = nv50_curs(wndw);
1115         nvif_wr32(&curs->chan, 0x0084, (asyw->point.y << 16) | asyw->point.x);
1116 }
1117
1118 static void
1119 nv50_curs_prepare(struct nv50_wndw *wndw, struct nv50_head_atom *asyh,
1120                   struct nv50_wndw_atom *asyw)
1121 {
1122         u32 handle = nv50_disp(wndw->plane.dev)->mast.base.vram.handle;
1123         u32 offset = asyw->image.offset;
1124         if (asyh->curs.handle != handle || asyh->curs.offset != offset) {
1125                 asyh->curs.handle = handle;
1126                 asyh->curs.offset = offset;
1127                 asyh->set.curs = asyh->curs.visible;
1128         }
1129 }
1130
1131 static void
1132 nv50_curs_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1133                   struct nv50_head_atom *asyh)
1134 {
1135         asyh->curs.visible = false;
1136 }
1137
1138 static int
1139 nv50_curs_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1140                   struct nv50_head_atom *asyh)
1141 {
1142         int ret;
1143
1144         ret = drm_plane_helper_check_state(&asyw->state, &asyw->clip,
1145                                            DRM_PLANE_HELPER_NO_SCALING,
1146                                            DRM_PLANE_HELPER_NO_SCALING,
1147                                            true, true);
1148         asyh->curs.visible = asyw->state.visible;
1149         if (ret || !asyh->curs.visible)
1150                 return ret;
1151
1152         switch (asyw->state.fb->width) {
1153         case 32: asyh->curs.layout = 0; break;
1154         case 64: asyh->curs.layout = 1; break;
1155         default:
1156                 return -EINVAL;
1157         }
1158
1159         if (asyw->state.fb->width != asyw->state.fb->height)
1160                 return -EINVAL;
1161
1162         switch (asyw->state.fb->format->format) {
1163         case DRM_FORMAT_ARGB8888: asyh->curs.format = 1; break;
1164         default:
1165                 WARN_ON(1);
1166                 return -EINVAL;
1167         }
1168
1169         return 0;
1170 }
1171
1172 static void *
1173 nv50_curs_dtor(struct nv50_wndw *wndw)
1174 {
1175         struct nv50_curs *curs = nv50_curs(wndw);
1176         nvif_object_fini(&curs->chan);
1177         return curs;
1178 }
1179
1180 static const u32
1181 nv50_curs_format[] = {
1182         DRM_FORMAT_ARGB8888,
1183 };
1184
1185 static const struct nv50_wndw_func
1186 nv50_curs = {
1187         .dtor = nv50_curs_dtor,
1188         .acquire = nv50_curs_acquire,
1189         .release = nv50_curs_release,
1190         .prepare = nv50_curs_prepare,
1191         .point = nv50_curs_point,
1192         .update = nv50_curs_update,
1193 };
1194
1195 static int
1196 nv50_curs_new(struct nouveau_drm *drm, struct nv50_head *head,
1197               struct nv50_curs **pcurs)
1198 {
1199         static const struct nvif_mclass curses[] = {
1200                 { GK104_DISP_CURSOR, 0 },
1201                 { GF110_DISP_CURSOR, 0 },
1202                 { GT214_DISP_CURSOR, 0 },
1203                 {   G82_DISP_CURSOR, 0 },
1204                 {  NV50_DISP_CURSOR, 0 },
1205                 {}
1206         };
1207         struct nv50_disp_cursor_v0 args = {
1208                 .head = head->base.index,
1209         };
1210         struct nv50_disp *disp = nv50_disp(drm->dev);
1211         struct nv50_curs *curs;
1212         int cid, ret;
1213
1214         cid = nvif_mclass(disp->disp, curses);
1215         if (cid < 0) {
1216                 NV_ERROR(drm, "No supported cursor immediate class\n");
1217                 return cid;
1218         }
1219
1220         if (!(curs = *pcurs = kzalloc(sizeof(*curs), GFP_KERNEL)))
1221                 return -ENOMEM;
1222
1223         ret = nv50_wndw_ctor(&nv50_curs, drm->dev, DRM_PLANE_TYPE_CURSOR,
1224                              "curs", head->base.index, &disp->mast.base,
1225                              nv50_curs_format, ARRAY_SIZE(nv50_curs_format),
1226                              &curs->wndw);
1227         if (ret) {
1228                 kfree(curs);
1229                 return ret;
1230         }
1231
1232         ret = nvif_object_init(disp->disp, 0, curses[cid].oclass, &args,
1233                                sizeof(args), &curs->chan);
1234         if (ret) {
1235                 NV_ERROR(drm, "curs%04x allocation failed: %d\n",
1236                          curses[cid].oclass, ret);
1237                 return ret;
1238         }
1239
1240         return 0;
1241 }
1242
1243 /******************************************************************************
1244  * Primary plane
1245  *****************************************************************************/
1246 #define nv50_base(p) container_of((p), struct nv50_base, wndw)
1247
1248 struct nv50_base {
1249         struct nv50_wndw wndw;
1250         struct nv50_sync chan;
1251         int id;
1252 };
1253
1254 static int
1255 nv50_base_notify(struct nvif_notify *notify)
1256 {
1257         return NVIF_NOTIFY_KEEP;
1258 }
1259
1260 static void
1261 nv50_base_lut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1262 {
1263         struct nv50_base *base = nv50_base(wndw);
1264         u32 *push;
1265         if ((push = evo_wait(&base->chan, 2))) {
1266                 evo_mthd(push, 0x00e0, 1);
1267                 evo_data(push, asyw->lut.enable << 30);
1268                 evo_kick(push, &base->chan);
1269         }
1270 }
1271
1272 static void
1273 nv50_base_image_clr(struct nv50_wndw *wndw)
1274 {
1275         struct nv50_base *base = nv50_base(wndw);
1276         u32 *push;
1277         if ((push = evo_wait(&base->chan, 4))) {
1278                 evo_mthd(push, 0x0084, 1);
1279                 evo_data(push, 0x00000000);
1280                 evo_mthd(push, 0x00c0, 1);
1281                 evo_data(push, 0x00000000);
1282                 evo_kick(push, &base->chan);
1283         }
1284 }
1285
1286 static void
1287 nv50_base_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1288 {
1289         struct nv50_base *base = nv50_base(wndw);
1290         const s32 oclass = base->chan.base.base.user.oclass;
1291         u32 *push;
1292         if ((push = evo_wait(&base->chan, 10))) {
1293                 evo_mthd(push, 0x0084, 1);
1294                 evo_data(push, (asyw->image.mode << 8) |
1295                                (asyw->image.interval << 4));
1296                 evo_mthd(push, 0x00c0, 1);
1297                 evo_data(push, asyw->image.handle);
1298                 if (oclass < G82_DISP_BASE_CHANNEL_DMA) {
1299                         evo_mthd(push, 0x0800, 5);
1300                         evo_data(push, asyw->image.offset >> 8);
1301                         evo_data(push, 0x00000000);
1302                         evo_data(push, (asyw->image.h << 16) | asyw->image.w);
1303                         evo_data(push, (asyw->image.layout << 20) |
1304                                         asyw->image.pitch |
1305                                         asyw->image.block);
1306                         evo_data(push, (asyw->image.kind << 16) |
1307                                        (asyw->image.format << 8));
1308                 } else
1309                 if (oclass < GF110_DISP_BASE_CHANNEL_DMA) {
1310                         evo_mthd(push, 0x0800, 5);
1311                         evo_data(push, asyw->image.offset >> 8);
1312                         evo_data(push, 0x00000000);
1313                         evo_data(push, (asyw->image.h << 16) | asyw->image.w);
1314                         evo_data(push, (asyw->image.layout << 20) |
1315                                         asyw->image.pitch |
1316                                         asyw->image.block);
1317                         evo_data(push, asyw->image.format << 8);
1318                 } else {
1319                         evo_mthd(push, 0x0400, 5);
1320                         evo_data(push, asyw->image.offset >> 8);
1321                         evo_data(push, 0x00000000);
1322                         evo_data(push, (asyw->image.h << 16) | asyw->image.w);
1323                         evo_data(push, (asyw->image.layout << 24) |
1324                                         asyw->image.pitch |
1325                                         asyw->image.block);
1326                         evo_data(push, asyw->image.format << 8);
1327                 }
1328                 evo_kick(push, &base->chan);
1329         }
1330 }
1331
1332 static void
1333 nv50_base_ntfy_clr(struct nv50_wndw *wndw)
1334 {
1335         struct nv50_base *base = nv50_base(wndw);
1336         u32 *push;
1337         if ((push = evo_wait(&base->chan, 2))) {
1338                 evo_mthd(push, 0x00a4, 1);
1339                 evo_data(push, 0x00000000);
1340                 evo_kick(push, &base->chan);
1341         }
1342 }
1343
1344 static void
1345 nv50_base_ntfy_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1346 {
1347         struct nv50_base *base = nv50_base(wndw);
1348         u32 *push;
1349         if ((push = evo_wait(&base->chan, 3))) {
1350                 evo_mthd(push, 0x00a0, 2);
1351                 evo_data(push, (asyw->ntfy.awaken << 30) | asyw->ntfy.offset);
1352                 evo_data(push, asyw->ntfy.handle);
1353                 evo_kick(push, &base->chan);
1354         }
1355 }
1356
1357 static void
1358 nv50_base_sema_clr(struct nv50_wndw *wndw)
1359 {
1360         struct nv50_base *base = nv50_base(wndw);
1361         u32 *push;
1362         if ((push = evo_wait(&base->chan, 2))) {
1363                 evo_mthd(push, 0x0094, 1);
1364                 evo_data(push, 0x00000000);
1365                 evo_kick(push, &base->chan);
1366         }
1367 }
1368
1369 static void
1370 nv50_base_sema_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1371 {
1372         struct nv50_base *base = nv50_base(wndw);
1373         u32 *push;
1374         if ((push = evo_wait(&base->chan, 5))) {
1375                 evo_mthd(push, 0x0088, 4);
1376                 evo_data(push, asyw->sema.offset);
1377                 evo_data(push, asyw->sema.acquire);
1378                 evo_data(push, asyw->sema.release);
1379                 evo_data(push, asyw->sema.handle);
1380                 evo_kick(push, &base->chan);
1381         }
1382 }
1383
1384 static u32
1385 nv50_base_update(struct nv50_wndw *wndw, u32 interlock)
1386 {
1387         struct nv50_base *base = nv50_base(wndw);
1388         u32 *push;
1389
1390         if (!(push = evo_wait(&base->chan, 2)))
1391                 return 0;
1392         evo_mthd(push, 0x0080, 1);
1393         evo_data(push, interlock);
1394         evo_kick(push, &base->chan);
1395
1396         if (base->chan.base.base.user.oclass < GF110_DISP_BASE_CHANNEL_DMA)
1397                 return interlock ? 2 << (base->id * 8) : 0;
1398         return interlock ? 2 << (base->id * 4) : 0;
1399 }
1400
1401 static int
1402 nv50_base_ntfy_wait_begun(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1403 {
1404         struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
1405         struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
1406         if (nvif_msec(&drm->client.device, 2000ULL,
1407                 u32 data = nouveau_bo_rd32(disp->sync, asyw->ntfy.offset / 4);
1408                 if ((data & 0xc0000000) == 0x40000000)
1409                         break;
1410                 usleep_range(1, 2);
1411         ) < 0)
1412                 return -ETIMEDOUT;
1413         return 0;
1414 }
1415
1416 static void
1417 nv50_base_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1418                   struct nv50_head_atom *asyh)
1419 {
1420         asyh->base.cpp = 0;
1421 }
1422
1423 static int
1424 nv50_base_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1425                   struct nv50_head_atom *asyh)
1426 {
1427         const struct drm_framebuffer *fb = asyw->state.fb;
1428         int ret;
1429
1430         if (!fb->format->depth)
1431                 return -EINVAL;
1432
1433         ret = drm_plane_helper_check_state(&asyw->state, &asyw->clip,
1434                                            DRM_PLANE_HELPER_NO_SCALING,
1435                                            DRM_PLANE_HELPER_NO_SCALING,
1436                                            false, true);
1437         if (ret)
1438                 return ret;
1439
1440         asyh->base.depth = fb->format->depth;
1441         asyh->base.cpp = fb->format->cpp[0];
1442         asyh->base.x = asyw->state.src.x1 >> 16;
1443         asyh->base.y = asyw->state.src.y1 >> 16;
1444         asyh->base.w = asyw->state.fb->width;
1445         asyh->base.h = asyw->state.fb->height;
1446
1447         switch (fb->format->format) {
1448         case DRM_FORMAT_C8         : asyw->image.format = 0x1e; break;
1449         case DRM_FORMAT_RGB565     : asyw->image.format = 0xe8; break;
1450         case DRM_FORMAT_XRGB1555   :
1451         case DRM_FORMAT_ARGB1555   : asyw->image.format = 0xe9; break;
1452         case DRM_FORMAT_XRGB8888   :
1453         case DRM_FORMAT_ARGB8888   : asyw->image.format = 0xcf; break;
1454         case DRM_FORMAT_XBGR2101010:
1455         case DRM_FORMAT_ABGR2101010: asyw->image.format = 0xd1; break;
1456         case DRM_FORMAT_XBGR8888   :
1457         case DRM_FORMAT_ABGR8888   : asyw->image.format = 0xd5; break;
1458         default:
1459                 WARN_ON(1);
1460                 return -EINVAL;
1461         }
1462
1463         asyw->lut.enable = 1;
1464         asyw->set.image = true;
1465         return 0;
1466 }
1467
1468 static void *
1469 nv50_base_dtor(struct nv50_wndw *wndw)
1470 {
1471         struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
1472         struct nv50_base *base = nv50_base(wndw);
1473         nv50_dmac_destroy(&base->chan.base, disp->disp);
1474         return base;
1475 }
1476
1477 static const u32
1478 nv50_base_format[] = {
1479         DRM_FORMAT_C8,
1480         DRM_FORMAT_RGB565,
1481         DRM_FORMAT_XRGB1555,
1482         DRM_FORMAT_ARGB1555,
1483         DRM_FORMAT_XRGB8888,
1484         DRM_FORMAT_ARGB8888,
1485         DRM_FORMAT_XBGR2101010,
1486         DRM_FORMAT_ABGR2101010,
1487         DRM_FORMAT_XBGR8888,
1488         DRM_FORMAT_ABGR8888,
1489 };
1490
1491 static const struct nv50_wndw_func
1492 nv50_base = {
1493         .dtor = nv50_base_dtor,
1494         .acquire = nv50_base_acquire,
1495         .release = nv50_base_release,
1496         .sema_set = nv50_base_sema_set,
1497         .sema_clr = nv50_base_sema_clr,
1498         .ntfy_set = nv50_base_ntfy_set,
1499         .ntfy_clr = nv50_base_ntfy_clr,
1500         .ntfy_wait_begun = nv50_base_ntfy_wait_begun,
1501         .image_set = nv50_base_image_set,
1502         .image_clr = nv50_base_image_clr,
1503         .lut = nv50_base_lut,
1504         .update = nv50_base_update,
1505 };
1506
1507 static int
1508 nv50_base_new(struct nouveau_drm *drm, struct nv50_head *head,
1509               struct nv50_base **pbase)
1510 {
1511         struct nv50_disp *disp = nv50_disp(drm->dev);
1512         struct nv50_base *base;
1513         int ret;
1514
1515         if (!(base = *pbase = kzalloc(sizeof(*base), GFP_KERNEL)))
1516                 return -ENOMEM;
1517         base->id = head->base.index;
1518         base->wndw.ntfy = EVO_FLIP_NTFY0(base->id);
1519         base->wndw.sema = EVO_FLIP_SEM0(base->id);
1520         base->wndw.data = 0x00000000;
1521
1522         ret = nv50_wndw_ctor(&nv50_base, drm->dev, DRM_PLANE_TYPE_PRIMARY,
1523                              "base", base->id, &base->chan.base,
1524                              nv50_base_format, ARRAY_SIZE(nv50_base_format),
1525                              &base->wndw);
1526         if (ret) {
1527                 kfree(base);
1528                 return ret;
1529         }
1530
1531         ret = nv50_base_create(&drm->client.device, disp->disp, base->id,
1532                                disp->sync->bo.offset, &base->chan);
1533         if (ret)
1534                 return ret;
1535
1536         return nvif_notify_init(&base->chan.base.base.user, nv50_base_notify,
1537                                 false,
1538                                 NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT,
1539                                 &(struct nvif_notify_uevent_req) {},
1540                                 sizeof(struct nvif_notify_uevent_req),
1541                                 sizeof(struct nvif_notify_uevent_rep),
1542                                 &base->wndw.notify);
1543 }
1544
1545 /******************************************************************************
1546  * Head
1547  *****************************************************************************/
1548 static void
1549 nv50_head_procamp(struct nv50_head *head, struct nv50_head_atom *asyh)
1550 {
1551         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1552         u32 *push;
1553         if ((push = evo_wait(core, 2))) {
1554                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1555                         evo_mthd(push, 0x08a8 + (head->base.index * 0x400), 1);
1556                 else
1557                         evo_mthd(push, 0x0498 + (head->base.index * 0x300), 1);
1558                 evo_data(push, (asyh->procamp.sat.sin << 20) |
1559                                (asyh->procamp.sat.cos << 8));
1560                 evo_kick(push, core);
1561         }
1562 }
1563
1564 static void
1565 nv50_head_dither(struct nv50_head *head, struct nv50_head_atom *asyh)
1566 {
1567         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1568         u32 *push;
1569         if ((push = evo_wait(core, 2))) {
1570                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1571                         evo_mthd(push, 0x08a0 + (head->base.index * 0x0400), 1);
1572                 else
1573                 if (core->base.user.oclass < GK104_DISP_CORE_CHANNEL_DMA)
1574                         evo_mthd(push, 0x0490 + (head->base.index * 0x0300), 1);
1575                 else
1576                         evo_mthd(push, 0x04a0 + (head->base.index * 0x0300), 1);
1577                 evo_data(push, (asyh->dither.mode << 3) |
1578                                (asyh->dither.bits << 1) |
1579                                 asyh->dither.enable);
1580                 evo_kick(push, core);
1581         }
1582 }
1583
1584 static void
1585 nv50_head_ovly(struct nv50_head *head, struct nv50_head_atom *asyh)
1586 {
1587         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1588         u32 bounds = 0;
1589         u32 *push;
1590
1591         if (asyh->base.cpp) {
1592                 switch (asyh->base.cpp) {
1593                 case 8: bounds |= 0x00000500; break;
1594                 case 4: bounds |= 0x00000300; break;
1595                 case 2: bounds |= 0x00000100; break;
1596                 default:
1597                         WARN_ON(1);
1598                         break;
1599                 }
1600                 bounds |= 0x00000001;
1601         }
1602
1603         if ((push = evo_wait(core, 2))) {
1604                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1605                         evo_mthd(push, 0x0904 + head->base.index * 0x400, 1);
1606                 else
1607                         evo_mthd(push, 0x04d4 + head->base.index * 0x300, 1);
1608                 evo_data(push, bounds);
1609                 evo_kick(push, core);
1610         }
1611 }
1612
1613 static void
1614 nv50_head_base(struct nv50_head *head, struct nv50_head_atom *asyh)
1615 {
1616         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1617         u32 bounds = 0;
1618         u32 *push;
1619
1620         if (asyh->base.cpp) {
1621                 switch (asyh->base.cpp) {
1622                 case 8: bounds |= 0x00000500; break;
1623                 case 4: bounds |= 0x00000300; break;
1624                 case 2: bounds |= 0x00000100; break;
1625                 case 1: bounds |= 0x00000000; break;
1626                 default:
1627                         WARN_ON(1);
1628                         break;
1629                 }
1630                 bounds |= 0x00000001;
1631         }
1632
1633         if ((push = evo_wait(core, 2))) {
1634                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1635                         evo_mthd(push, 0x0900 + head->base.index * 0x400, 1);
1636                 else
1637                         evo_mthd(push, 0x04d0 + head->base.index * 0x300, 1);
1638                 evo_data(push, bounds);
1639                 evo_kick(push, core);
1640         }
1641 }
1642
1643 static void
1644 nv50_head_curs_clr(struct nv50_head *head)
1645 {
1646         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1647         u32 *push;
1648         if ((push = evo_wait(core, 4))) {
1649                 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1650                         evo_mthd(push, 0x0880 + head->base.index * 0x400, 1);
1651                         evo_data(push, 0x05000000);
1652                 } else
1653                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1654                         evo_mthd(push, 0x0880 + head->base.index * 0x400, 1);
1655                         evo_data(push, 0x05000000);
1656                         evo_mthd(push, 0x089c + head->base.index * 0x400, 1);
1657                         evo_data(push, 0x00000000);
1658                 } else {
1659                         evo_mthd(push, 0x0480 + head->base.index * 0x300, 1);
1660                         evo_data(push, 0x05000000);
1661                         evo_mthd(push, 0x048c + head->base.index * 0x300, 1);
1662                         evo_data(push, 0x00000000);
1663                 }
1664                 evo_kick(push, core);
1665         }
1666 }
1667
1668 static void
1669 nv50_head_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1670 {
1671         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1672         u32 *push;
1673         if ((push = evo_wait(core, 5))) {
1674                 if (core->base.user.oclass < G82_DISP_BASE_CHANNEL_DMA) {
1675                         evo_mthd(push, 0x0880 + head->base.index * 0x400, 2);
1676                         evo_data(push, 0x80000000 | (asyh->curs.layout << 26) |
1677                                                     (asyh->curs.format << 24));
1678                         evo_data(push, asyh->curs.offset >> 8);
1679                 } else
1680                 if (core->base.user.oclass < GF110_DISP_BASE_CHANNEL_DMA) {
1681                         evo_mthd(push, 0x0880 + head->base.index * 0x400, 2);
1682                         evo_data(push, 0x80000000 | (asyh->curs.layout << 26) |
1683                                                     (asyh->curs.format << 24));
1684                         evo_data(push, asyh->curs.offset >> 8);
1685                         evo_mthd(push, 0x089c + head->base.index * 0x400, 1);
1686                         evo_data(push, asyh->curs.handle);
1687                 } else {
1688                         evo_mthd(push, 0x0480 + head->base.index * 0x300, 2);
1689                         evo_data(push, 0x80000000 | (asyh->curs.layout << 26) |
1690                                                     (asyh->curs.format << 24));
1691                         evo_data(push, asyh->curs.offset >> 8);
1692                         evo_mthd(push, 0x048c + head->base.index * 0x300, 1);
1693                         evo_data(push, asyh->curs.handle);
1694                 }
1695                 evo_kick(push, core);
1696         }
1697 }
1698
1699 static void
1700 nv50_head_core_clr(struct nv50_head *head)
1701 {
1702         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1703         u32 *push;
1704         if ((push = evo_wait(core, 2))) {
1705                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1706                         evo_mthd(push, 0x0874 + head->base.index * 0x400, 1);
1707                 else
1708                         evo_mthd(push, 0x0474 + head->base.index * 0x300, 1);
1709                 evo_data(push, 0x00000000);
1710                 evo_kick(push, core);
1711         }
1712 }
1713
1714 static void
1715 nv50_head_core_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1716 {
1717         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1718         u32 *push;
1719         if ((push = evo_wait(core, 9))) {
1720                 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1721                         evo_mthd(push, 0x0860 + head->base.index * 0x400, 1);
1722                         evo_data(push, asyh->core.offset >> 8);
1723                         evo_mthd(push, 0x0868 + head->base.index * 0x400, 4);
1724                         evo_data(push, (asyh->core.h << 16) | asyh->core.w);
1725                         evo_data(push, asyh->core.layout << 20 |
1726                                        (asyh->core.pitch >> 8) << 8 |
1727                                        asyh->core.block);
1728                         evo_data(push, asyh->core.kind << 16 |
1729                                        asyh->core.format << 8);
1730                         evo_data(push, asyh->core.handle);
1731                         evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1);
1732                         evo_data(push, (asyh->core.y << 16) | asyh->core.x);
1733                         /* EVO will complain with INVALID_STATE if we have an
1734                          * active cursor and (re)specify HeadSetContextDmaIso
1735                          * without also updating HeadSetOffsetCursor.
1736                          */
1737                         asyh->set.curs = asyh->curs.visible;
1738                 } else
1739                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1740                         evo_mthd(push, 0x0860 + head->base.index * 0x400, 1);
1741                         evo_data(push, asyh->core.offset >> 8);
1742                         evo_mthd(push, 0x0868 + head->base.index * 0x400, 4);
1743                         evo_data(push, (asyh->core.h << 16) | asyh->core.w);
1744                         evo_data(push, asyh->core.layout << 20 |
1745                                        (asyh->core.pitch >> 8) << 8 |
1746                                        asyh->core.block);
1747                         evo_data(push, asyh->core.format << 8);
1748                         evo_data(push, asyh->core.handle);
1749                         evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1);
1750                         evo_data(push, (asyh->core.y << 16) | asyh->core.x);
1751                 } else {
1752                         evo_mthd(push, 0x0460 + head->base.index * 0x300, 1);
1753                         evo_data(push, asyh->core.offset >> 8);
1754                         evo_mthd(push, 0x0468 + head->base.index * 0x300, 4);
1755                         evo_data(push, (asyh->core.h << 16) | asyh->core.w);
1756                         evo_data(push, asyh->core.layout << 24 |
1757                                        (asyh->core.pitch >> 8) << 8 |
1758                                        asyh->core.block);
1759                         evo_data(push, asyh->core.format << 8);
1760                         evo_data(push, asyh->core.handle);
1761                         evo_mthd(push, 0x04b0 + head->base.index * 0x300, 1);
1762                         evo_data(push, (asyh->core.y << 16) | asyh->core.x);
1763                 }
1764                 evo_kick(push, core);
1765         }
1766 }
1767
1768 static void
1769 nv50_head_lut_clr(struct nv50_head *head)
1770 {
1771         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1772         u32 *push;
1773         if ((push = evo_wait(core, 4))) {
1774                 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1775                         evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1);
1776                         evo_data(push, 0x40000000);
1777                 } else
1778                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1779                         evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1);
1780                         evo_data(push, 0x40000000);
1781                         evo_mthd(push, 0x085c + (head->base.index * 0x400), 1);
1782                         evo_data(push, 0x00000000);
1783                 } else {
1784                         evo_mthd(push, 0x0440 + (head->base.index * 0x300), 1);
1785                         evo_data(push, 0x03000000);
1786                         evo_mthd(push, 0x045c + (head->base.index * 0x300), 1);
1787                         evo_data(push, 0x00000000);
1788                 }
1789                 evo_kick(push, core);
1790         }
1791 }
1792
1793 static void
1794 nv50_head_lut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1795 {
1796         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1797         u32 *push;
1798         if ((push = evo_wait(core, 7))) {
1799                 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1800                         evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2);
1801                         evo_data(push, 0xc0000000);
1802                         evo_data(push, asyh->lut.offset >> 8);
1803                 } else
1804                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1805                         evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2);
1806                         evo_data(push, 0xc0000000);
1807                         evo_data(push, asyh->lut.offset >> 8);
1808                         evo_mthd(push, 0x085c + (head->base.index * 0x400), 1);
1809                         evo_data(push, asyh->lut.handle);
1810                 } else {
1811                         evo_mthd(push, 0x0440 + (head->base.index * 0x300), 4);
1812                         evo_data(push, 0x83000000);
1813                         evo_data(push, asyh->lut.offset >> 8);
1814                         evo_data(push, 0x00000000);
1815                         evo_data(push, 0x00000000);
1816                         evo_mthd(push, 0x045c + (head->base.index * 0x300), 1);
1817                         evo_data(push, asyh->lut.handle);
1818                 }
1819                 evo_kick(push, core);
1820         }
1821 }
1822
1823 static void
1824 nv50_head_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
1825 {
1826         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1827         struct nv50_head_mode *m = &asyh->mode;
1828         u32 *push;
1829         if ((push = evo_wait(core, 14))) {
1830                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1831                         evo_mthd(push, 0x0804 + (head->base.index * 0x400), 2);
1832                         evo_data(push, 0x00800000 | m->clock);
1833                         evo_data(push, m->interlace ? 0x00000002 : 0x00000000);
1834                         evo_mthd(push, 0x0810 + (head->base.index * 0x400), 7);
1835                         evo_data(push, 0x00000000);
1836                         evo_data(push, (m->v.active  << 16) | m->h.active );
1837                         evo_data(push, (m->v.synce   << 16) | m->h.synce  );
1838                         evo_data(push, (m->v.blanke  << 16) | m->h.blanke );
1839                         evo_data(push, (m->v.blanks  << 16) | m->h.blanks );
1840                         evo_data(push, (m->v.blank2e << 16) | m->v.blank2s);
1841                         evo_data(push, asyh->mode.v.blankus);
1842                         evo_mthd(push, 0x082c + (head->base.index * 0x400), 1);
1843                         evo_data(push, 0x00000000);
1844                 } else {
1845                         evo_mthd(push, 0x0410 + (head->base.index * 0x300), 6);
1846                         evo_data(push, 0x00000000);
1847                         evo_data(push, (m->v.active  << 16) | m->h.active );
1848                         evo_data(push, (m->v.synce   << 16) | m->h.synce  );
1849                         evo_data(push, (m->v.blanke  << 16) | m->h.blanke );
1850                         evo_data(push, (m->v.blanks  << 16) | m->h.blanks );
1851                         evo_data(push, (m->v.blank2e << 16) | m->v.blank2s);
1852                         evo_mthd(push, 0x042c + (head->base.index * 0x300), 2);
1853                         evo_data(push, 0x00000000); /* ??? */
1854                         evo_data(push, 0xffffff00);
1855                         evo_mthd(push, 0x0450 + (head->base.index * 0x300), 3);
1856                         evo_data(push, m->clock * 1000);
1857                         evo_data(push, 0x00200000); /* ??? */
1858                         evo_data(push, m->clock * 1000);
1859                 }
1860                 evo_kick(push, core);
1861         }
1862 }
1863
1864 static void
1865 nv50_head_view(struct nv50_head *head, struct nv50_head_atom *asyh)
1866 {
1867         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1868         u32 *push;
1869         if ((push = evo_wait(core, 10))) {
1870                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1871                         evo_mthd(push, 0x08a4 + (head->base.index * 0x400), 1);
1872                         evo_data(push, 0x00000000);
1873                         evo_mthd(push, 0x08c8 + (head->base.index * 0x400), 1);
1874                         evo_data(push, (asyh->view.iH << 16) | asyh->view.iW);
1875                         evo_mthd(push, 0x08d8 + (head->base.index * 0x400), 2);
1876                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1877                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1878                 } else {
1879                         evo_mthd(push, 0x0494 + (head->base.index * 0x300), 1);
1880                         evo_data(push, 0x00000000);
1881                         evo_mthd(push, 0x04b8 + (head->base.index * 0x300), 1);
1882                         evo_data(push, (asyh->view.iH << 16) | asyh->view.iW);
1883                         evo_mthd(push, 0x04c0 + (head->base.index * 0x300), 3);
1884                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1885                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1886                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1887                 }
1888                 evo_kick(push, core);
1889         }
1890 }
1891
1892 static void
1893 nv50_head_flush_clr(struct nv50_head *head, struct nv50_head_atom *asyh, bool y)
1894 {
1895         if (asyh->clr.core && (!asyh->set.core || y))
1896                 nv50_head_lut_clr(head);
1897         if (asyh->clr.core && (!asyh->set.core || y))
1898                 nv50_head_core_clr(head);
1899         if (asyh->clr.curs && (!asyh->set.curs || y))
1900                 nv50_head_curs_clr(head);
1901 }
1902
1903 static void
1904 nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1905 {
1906         if (asyh->set.view   ) nv50_head_view    (head, asyh);
1907         if (asyh->set.mode   ) nv50_head_mode    (head, asyh);
1908         if (asyh->set.core   ) nv50_head_lut_set (head, asyh);
1909         if (asyh->set.core   ) nv50_head_core_set(head, asyh);
1910         if (asyh->set.curs   ) nv50_head_curs_set(head, asyh);
1911         if (asyh->set.base   ) nv50_head_base    (head, asyh);
1912         if (asyh->set.ovly   ) nv50_head_ovly    (head, asyh);
1913         if (asyh->set.dither ) nv50_head_dither  (head, asyh);
1914         if (asyh->set.procamp) nv50_head_procamp (head, asyh);
1915 }
1916
1917 static void
1918 nv50_head_atomic_check_procamp(struct nv50_head_atom *armh,
1919                                struct nv50_head_atom *asyh,
1920                                struct nouveau_conn_atom *asyc)
1921 {
1922         const int vib = asyc->procamp.color_vibrance - 100;
1923         const int hue = asyc->procamp.vibrant_hue - 90;
1924         const int adj = (vib > 0) ? 50 : 0;
1925         asyh->procamp.sat.cos = ((vib * 2047 + adj) / 100) & 0xfff;
1926         asyh->procamp.sat.sin = ((hue * 2047) / 100) & 0xfff;
1927         asyh->set.procamp = true;
1928 }
1929
1930 static void
1931 nv50_head_atomic_check_dither(struct nv50_head_atom *armh,
1932                               struct nv50_head_atom *asyh,
1933                               struct nouveau_conn_atom *asyc)
1934 {
1935         struct drm_connector *connector = asyc->state.connector;
1936         u32 mode = 0x00;
1937
1938         if (asyc->dither.mode == DITHERING_MODE_AUTO) {
1939                 if (asyh->base.depth > connector->display_info.bpc * 3)
1940                         mode = DITHERING_MODE_DYNAMIC2X2;
1941         } else {
1942                 mode = asyc->dither.mode;
1943         }
1944
1945         if (asyc->dither.depth == DITHERING_DEPTH_AUTO) {
1946                 if (connector->display_info.bpc >= 8)
1947                         mode |= DITHERING_DEPTH_8BPC;
1948         } else {
1949                 mode |= asyc->dither.depth;
1950         }
1951
1952         asyh->dither.enable = mode;
1953         asyh->dither.bits = mode >> 1;
1954         asyh->dither.mode = mode >> 3;
1955         asyh->set.dither = true;
1956 }
1957
1958 static void
1959 nv50_head_atomic_check_view(struct nv50_head_atom *armh,
1960                             struct nv50_head_atom *asyh,
1961                             struct nouveau_conn_atom *asyc)
1962 {
1963         struct drm_connector *connector = asyc->state.connector;
1964         struct drm_display_mode *omode = &asyh->state.adjusted_mode;
1965         struct drm_display_mode *umode = &asyh->state.mode;
1966         int mode = asyc->scaler.mode;
1967         struct edid *edid;
1968
1969         if (connector->edid_blob_ptr)
1970                 edid = (struct edid *)connector->edid_blob_ptr->data;
1971         else
1972                 edid = NULL;
1973
1974         if (!asyc->scaler.full) {
1975                 if (mode == DRM_MODE_SCALE_NONE)
1976                         omode = umode;
1977         } else {
1978                 /* Non-EDID LVDS/eDP mode. */
1979                 mode = DRM_MODE_SCALE_FULLSCREEN;
1980         }
1981
1982         asyh->view.iW = umode->hdisplay;
1983         asyh->view.iH = umode->vdisplay;
1984         asyh->view.oW = omode->hdisplay;
1985         asyh->view.oH = omode->vdisplay;
1986         if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
1987                 asyh->view.oH *= 2;
1988
1989         /* Add overscan compensation if necessary, will keep the aspect
1990          * ratio the same as the backend mode unless overridden by the
1991          * user setting both hborder and vborder properties.
1992          */
1993         if ((asyc->scaler.underscan.mode == UNDERSCAN_ON ||
1994             (asyc->scaler.underscan.mode == UNDERSCAN_AUTO &&
1995              drm_detect_hdmi_monitor(edid)))) {
1996                 u32 bX = asyc->scaler.underscan.hborder;
1997                 u32 bY = asyc->scaler.underscan.vborder;
1998                 u32 r = (asyh->view.oH << 19) / asyh->view.oW;
1999
2000                 if (bX) {
2001                         asyh->view.oW -= (bX * 2);
2002                         if (bY) asyh->view.oH -= (bY * 2);
2003                         else    asyh->view.oH  = ((asyh->view.oW * r) + (r / 2)) >> 19;
2004                 } else {
2005                         asyh->view.oW -= (asyh->view.oW >> 4) + 32;
2006                         if (bY) asyh->view.oH -= (bY * 2);
2007                         else    asyh->view.oH  = ((asyh->view.oW * r) + (r / 2)) >> 19;
2008                 }
2009         }
2010
2011         /* Handle CENTER/ASPECT scaling, taking into account the areas
2012          * removed already for overscan compensation.
2013          */
2014         switch (mode) {
2015         case DRM_MODE_SCALE_CENTER:
2016                 asyh->view.oW = min((u16)umode->hdisplay, asyh->view.oW);
2017                 asyh->view.oH = min((u16)umode->vdisplay, asyh->view.oH);
2018                 /* fall-through */
2019         case DRM_MODE_SCALE_ASPECT:
2020                 if (asyh->view.oH < asyh->view.oW) {
2021                         u32 r = (asyh->view.iW << 19) / asyh->view.iH;
2022                         asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19;
2023                 } else {
2024                         u32 r = (asyh->view.iH << 19) / asyh->view.iW;
2025                         asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
2026                 }
2027                 break;
2028         default:
2029                 break;
2030         }
2031
2032         asyh->set.view = true;
2033 }
2034
2035 static void
2036 nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
2037 {
2038         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
2039         u32 ilace   = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
2040         u32 vscan   = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
2041         u32 hbackp  =  mode->htotal - mode->hsync_end;
2042         u32 vbackp  = (mode->vtotal - mode->vsync_end) * vscan / ilace;
2043         u32 hfrontp =  mode->hsync_start - mode->hdisplay;
2044         u32 vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
2045         u32 blankus;
2046         struct nv50_head_mode *m = &asyh->mode;
2047
2048         m->h.active = mode->htotal;
2049         m->h.synce  = mode->hsync_end - mode->hsync_start - 1;
2050         m->h.blanke = m->h.synce + hbackp;
2051         m->h.blanks = mode->htotal - hfrontp - 1;
2052
2053         m->v.active = mode->vtotal * vscan / ilace;
2054         m->v.synce  = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
2055         m->v.blanke = m->v.synce + vbackp;
2056         m->v.blanks = m->v.active - vfrontp - 1;
2057
2058         /*XXX: Safe underestimate, even "0" works */
2059         blankus = (m->v.active - mode->vdisplay - 2) * m->h.active;
2060         blankus *= 1000;
2061         blankus /= mode->clock;
2062         m->v.blankus = blankus;
2063
2064         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
2065                 m->v.blank2e =  m->v.active + m->v.synce + vbackp;
2066                 m->v.blank2s =  m->v.blank2e + (mode->vdisplay * vscan / ilace);
2067                 m->v.active  = (m->v.active * 2) + 1;
2068                 m->interlace = true;
2069         } else {
2070                 m->v.blank2e = 0;
2071                 m->v.blank2s = 1;
2072                 m->interlace = false;
2073         }
2074         m->clock = mode->clock;
2075
2076         drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
2077         asyh->set.mode = true;
2078 }
2079
2080 static int
2081 nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state)
2082 {
2083         struct nouveau_drm *drm = nouveau_drm(crtc->dev);
2084         struct nv50_disp *disp = nv50_disp(crtc->dev);
2085         struct nv50_head *head = nv50_head(crtc);
2086         struct nv50_head_atom *armh = nv50_head_atom(crtc->state);
2087         struct nv50_head_atom *asyh = nv50_head_atom(state);
2088         struct nouveau_conn_atom *asyc = NULL;
2089         struct drm_connector_state *conns;
2090         struct drm_connector *conn;
2091         int i;
2092
2093         NV_ATOMIC(drm, "%s atomic_check %d\n", crtc->name, asyh->state.active);
2094         if (asyh->state.active) {
2095                 for_each_connector_in_state(asyh->state.state, conn, conns, i) {
2096                         if (conns->crtc == crtc) {
2097                                 asyc = nouveau_conn_atom(conns);
2098                                 break;
2099                         }
2100                 }
2101
2102                 if (armh->state.active) {
2103                         if (asyc) {
2104                                 if (asyh->state.mode_changed)
2105                                         asyc->set.scaler = true;
2106                                 if (armh->base.depth != asyh->base.depth)
2107                                         asyc->set.dither = true;
2108                         }
2109                 } else {
2110                         if (asyc)
2111                                 asyc->set.mask = ~0;
2112                         asyh->set.mask = ~0;
2113                 }
2114
2115                 if (asyh->state.mode_changed)
2116                         nv50_head_atomic_check_mode(head, asyh);
2117
2118                 if (asyc) {
2119                         if (asyc->set.scaler)
2120                                 nv50_head_atomic_check_view(armh, asyh, asyc);
2121                         if (asyc->set.dither)
2122                                 nv50_head_atomic_check_dither(armh, asyh, asyc);
2123                         if (asyc->set.procamp)
2124                                 nv50_head_atomic_check_procamp(armh, asyh, asyc);
2125                 }
2126
2127                 if ((asyh->core.visible = (asyh->base.cpp != 0))) {
2128                         asyh->core.x = asyh->base.x;
2129                         asyh->core.y = asyh->base.y;
2130                         asyh->core.w = asyh->base.w;
2131                         asyh->core.h = asyh->base.h;
2132                 } else
2133                 if ((asyh->core.visible = asyh->curs.visible)) {
2134                         /*XXX: We need to either find some way of having the
2135                          *     primary base layer appear black, while still
2136                          *     being able to display the other layers, or we
2137                          *     need to allocate a dummy black surface here.
2138                          */
2139                         asyh->core.x = 0;
2140                         asyh->core.y = 0;
2141                         asyh->core.w = asyh->state.mode.hdisplay;
2142                         asyh->core.h = asyh->state.mode.vdisplay;
2143                 }
2144                 asyh->core.handle = disp->mast.base.vram.handle;
2145                 asyh->core.offset = 0;
2146                 asyh->core.format = 0xcf;
2147                 asyh->core.kind = 0;
2148                 asyh->core.layout = 1;
2149                 asyh->core.block = 0;
2150                 asyh->core.pitch = ALIGN(asyh->core.w, 64) * 4;
2151                 asyh->lut.handle = disp->mast.base.vram.handle;
2152                 asyh->lut.offset = head->base.lut.nvbo->bo.offset;
2153                 asyh->set.base = armh->base.cpp != asyh->base.cpp;
2154                 asyh->set.ovly = armh->ovly.cpp != asyh->ovly.cpp;
2155         } else {
2156                 asyh->core.visible = false;
2157                 asyh->curs.visible = false;
2158                 asyh->base.cpp = 0;
2159                 asyh->ovly.cpp = 0;
2160         }
2161
2162         if (!drm_atomic_crtc_needs_modeset(&asyh->state)) {
2163                 if (asyh->core.visible) {
2164                         if (memcmp(&armh->core, &asyh->core, sizeof(asyh->core)))
2165                                 asyh->set.core = true;
2166                 } else
2167                 if (armh->core.visible) {
2168                         asyh->clr.core = true;
2169                 }
2170
2171                 if (asyh->curs.visible) {
2172                         if (memcmp(&armh->curs, &asyh->curs, sizeof(asyh->curs)))
2173                                 asyh->set.curs = true;
2174                 } else
2175                 if (armh->curs.visible) {
2176                         asyh->clr.curs = true;
2177                 }
2178         } else {
2179                 asyh->clr.core = armh->core.visible;
2180                 asyh->clr.curs = armh->curs.visible;
2181                 asyh->set.core = asyh->core.visible;
2182                 asyh->set.curs = asyh->curs.visible;
2183         }
2184
2185         if (asyh->clr.mask || asyh->set.mask)
2186                 nv50_atom(asyh->state.state)->lock_core = true;
2187         return 0;
2188 }
2189
2190 static void
2191 nv50_head_lut_load(struct drm_crtc *crtc)
2192 {
2193         struct nv50_disp *disp = nv50_disp(crtc->dev);
2194         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
2195         void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
2196         int i;
2197
2198         for (i = 0; i < 256; i++) {
2199                 u16 r = nv_crtc->lut.r[i] >> 2;
2200                 u16 g = nv_crtc->lut.g[i] >> 2;
2201                 u16 b = nv_crtc->lut.b[i] >> 2;
2202
2203                 if (disp->disp->oclass < GF110_DISP) {
2204                         writew(r + 0x0000, lut + (i * 0x08) + 0);
2205                         writew(g + 0x0000, lut + (i * 0x08) + 2);
2206                         writew(b + 0x0000, lut + (i * 0x08) + 4);
2207                 } else {
2208                         writew(r + 0x6000, lut + (i * 0x20) + 0);
2209                         writew(g + 0x6000, lut + (i * 0x20) + 2);
2210                         writew(b + 0x6000, lut + (i * 0x20) + 4);
2211                 }
2212         }
2213 }
2214
2215 static const struct drm_crtc_helper_funcs
2216 nv50_head_help = {
2217         .load_lut = nv50_head_lut_load,
2218         .atomic_check = nv50_head_atomic_check,
2219 };
2220
2221 static int
2222 nv50_head_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
2223                     uint32_t size,
2224                     struct drm_modeset_acquire_ctx *ctx)
2225 {
2226         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
2227         u32 i;
2228
2229         for (i = 0; i < size; i++) {
2230                 nv_crtc->lut.r[i] = r[i];
2231                 nv_crtc->lut.g[i] = g[i];
2232                 nv_crtc->lut.b[i] = b[i];
2233         }
2234
2235         nv50_head_lut_load(crtc);
2236         return 0;
2237 }
2238
2239 static void
2240 nv50_head_atomic_destroy_state(struct drm_crtc *crtc,
2241                                struct drm_crtc_state *state)
2242 {
2243         struct nv50_head_atom *asyh = nv50_head_atom(state);
2244         __drm_atomic_helper_crtc_destroy_state(&asyh->state);
2245         kfree(asyh);
2246 }
2247
2248 static struct drm_crtc_state *
2249 nv50_head_atomic_duplicate_state(struct drm_crtc *crtc)
2250 {
2251         struct nv50_head_atom *armh = nv50_head_atom(crtc->state);
2252         struct nv50_head_atom *asyh;
2253         if (!(asyh = kmalloc(sizeof(*asyh), GFP_KERNEL)))
2254                 return NULL;
2255         __drm_atomic_helper_crtc_duplicate_state(crtc, &asyh->state);
2256         asyh->view = armh->view;
2257         asyh->mode = armh->mode;
2258         asyh->lut  = armh->lut;
2259         asyh->core = armh->core;
2260         asyh->curs = armh->curs;
2261         asyh->base = armh->base;
2262         asyh->ovly = armh->ovly;
2263         asyh->dither = armh->dither;
2264         asyh->procamp = armh->procamp;
2265         asyh->clr.mask = 0;
2266         asyh->set.mask = 0;
2267         return &asyh->state;
2268 }
2269
2270 static void
2271 __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc,
2272                                struct drm_crtc_state *state)
2273 {
2274         if (crtc->state)
2275                 crtc->funcs->atomic_destroy_state(crtc, crtc->state);
2276         crtc->state = state;
2277         crtc->state->crtc = crtc;
2278 }
2279
2280 static void
2281 nv50_head_reset(struct drm_crtc *crtc)
2282 {
2283         struct nv50_head_atom *asyh;
2284
2285         if (WARN_ON(!(asyh = kzalloc(sizeof(*asyh), GFP_KERNEL))))
2286                 return;
2287
2288         __drm_atomic_helper_crtc_reset(crtc, &asyh->state);
2289 }
2290
2291 static void
2292 nv50_head_destroy(struct drm_crtc *crtc)
2293 {
2294         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
2295         struct nv50_disp *disp = nv50_disp(crtc->dev);
2296         struct nv50_head *head = nv50_head(crtc);
2297
2298         nv50_dmac_destroy(&head->ovly.base, disp->disp);
2299         nv50_pioc_destroy(&head->oimm.base);
2300
2301         nouveau_bo_unmap(nv_crtc->lut.nvbo);
2302         if (nv_crtc->lut.nvbo)
2303                 nouveau_bo_unpin(nv_crtc->lut.nvbo);
2304         nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
2305
2306         drm_crtc_cleanup(crtc);
2307         kfree(crtc);
2308 }
2309
2310 static const struct drm_crtc_funcs
2311 nv50_head_func = {
2312         .reset = nv50_head_reset,
2313         .gamma_set = nv50_head_gamma_set,
2314         .destroy = nv50_head_destroy,
2315         .set_config = drm_atomic_helper_set_config,
2316         .page_flip = drm_atomic_helper_page_flip,
2317         .set_property = drm_atomic_helper_crtc_set_property,
2318         .atomic_duplicate_state = nv50_head_atomic_duplicate_state,
2319         .atomic_destroy_state = nv50_head_atomic_destroy_state,
2320 };
2321
2322 static int
2323 nv50_head_create(struct drm_device *dev, int index)
2324 {
2325         struct nouveau_drm *drm = nouveau_drm(dev);
2326         struct nvif_device *device = &drm->client.device;
2327         struct nv50_disp *disp = nv50_disp(dev);
2328         struct nv50_head *head;
2329         struct nv50_base *base;
2330         struct nv50_curs *curs;
2331         struct drm_crtc *crtc;
2332         int ret, i;
2333
2334         head = kzalloc(sizeof(*head), GFP_KERNEL);
2335         if (!head)
2336                 return -ENOMEM;
2337
2338         head->base.index = index;
2339         for (i = 0; i < 256; i++) {
2340                 head->base.lut.r[i] = i << 8;
2341                 head->base.lut.g[i] = i << 8;
2342                 head->base.lut.b[i] = i << 8;
2343         }
2344
2345         ret = nv50_base_new(drm, head, &base);
2346         if (ret == 0)
2347                 ret = nv50_curs_new(drm, head, &curs);
2348         if (ret) {
2349                 kfree(head);
2350                 return ret;
2351         }
2352
2353         crtc = &head->base.base;
2354         drm_crtc_init_with_planes(dev, crtc, &base->wndw.plane,
2355                                   &curs->wndw.plane, &nv50_head_func,
2356                                   "head-%d", head->base.index);
2357         drm_crtc_helper_add(crtc, &nv50_head_help);
2358         drm_mode_crtc_set_gamma_size(crtc, 256);
2359
2360         ret = nouveau_bo_new(&drm->client, 8192, 0x100, TTM_PL_FLAG_VRAM,
2361                              0, 0x0000, NULL, NULL, &head->base.lut.nvbo);
2362         if (!ret) {
2363                 ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM, true);
2364                 if (!ret) {
2365                         ret = nouveau_bo_map(head->base.lut.nvbo);
2366                         if (ret)
2367                                 nouveau_bo_unpin(head->base.lut.nvbo);
2368                 }
2369                 if (ret)
2370                         nouveau_bo_ref(NULL, &head->base.lut.nvbo);
2371         }
2372
2373         if (ret)
2374                 goto out;
2375
2376         /* allocate overlay resources */
2377         ret = nv50_oimm_create(device, disp->disp, index, &head->oimm);
2378         if (ret)
2379                 goto out;
2380
2381         ret = nv50_ovly_create(device, disp->disp, index, disp->sync->bo.offset,
2382                                &head->ovly);
2383         if (ret)
2384                 goto out;
2385
2386 out:
2387         if (ret)
2388                 nv50_head_destroy(crtc);
2389         return ret;
2390 }
2391
2392 /******************************************************************************
2393  * Output path helpers
2394  *****************************************************************************/
2395 static int
2396 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
2397                             struct drm_crtc_state *crtc_state,
2398                             struct drm_connector_state *conn_state,
2399                             struct drm_display_mode *native_mode)
2400 {
2401         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
2402         struct drm_display_mode *mode = &crtc_state->mode;
2403         struct drm_connector *connector = conn_state->connector;
2404         struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
2405         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
2406
2407         NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
2408         asyc->scaler.full = false;
2409         if (!native_mode)
2410                 return 0;
2411
2412         if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
2413                 switch (connector->connector_type) {
2414                 case DRM_MODE_CONNECTOR_LVDS:
2415                 case DRM_MODE_CONNECTOR_eDP:
2416                         /* Force use of scaler for non-EDID modes. */
2417                         if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
2418                                 break;
2419                         mode = native_mode;
2420                         asyc->scaler.full = true;
2421                         break;
2422                 default:
2423                         break;
2424                 }
2425         } else {
2426                 mode = native_mode;
2427         }
2428
2429         if (!drm_mode_equal(adjusted_mode, mode)) {
2430                 drm_mode_copy(adjusted_mode, mode);
2431                 crtc_state->mode_changed = true;
2432         }
2433
2434         return 0;
2435 }
2436
2437 static int
2438 nv50_outp_atomic_check(struct drm_encoder *encoder,
2439                        struct drm_crtc_state *crtc_state,
2440                        struct drm_connector_state *conn_state)
2441 {
2442         struct nouveau_connector *nv_connector =
2443                 nouveau_connector(conn_state->connector);
2444         return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
2445                                            nv_connector->native_mode);
2446 }
2447
2448 /******************************************************************************
2449  * DAC
2450  *****************************************************************************/
2451 static void
2452 nv50_dac_dpms(struct drm_encoder *encoder, int mode)
2453 {
2454         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2455         struct nv50_disp *disp = nv50_disp(encoder->dev);
2456         struct {
2457                 struct nv50_disp_mthd_v1 base;
2458                 struct nv50_disp_dac_pwr_v0 pwr;
2459         } args = {
2460                 .base.version = 1,
2461                 .base.method = NV50_DISP_MTHD_V1_DAC_PWR,
2462                 .base.hasht  = nv_encoder->dcb->hasht,
2463                 .base.hashm  = nv_encoder->dcb->hashm,
2464                 .pwr.state = 1,
2465                 .pwr.data  = 1,
2466                 .pwr.vsync = (mode != DRM_MODE_DPMS_SUSPEND &&
2467                               mode != DRM_MODE_DPMS_OFF),
2468                 .pwr.hsync = (mode != DRM_MODE_DPMS_STANDBY &&
2469                               mode != DRM_MODE_DPMS_OFF),
2470         };
2471
2472         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2473 }
2474
2475 static void
2476 nv50_dac_disable(struct drm_encoder *encoder)
2477 {
2478         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2479         struct nv50_mast *mast = nv50_mast(encoder->dev);
2480         const int or = nv_encoder->or;
2481         u32 *push;
2482
2483         if (nv_encoder->crtc) {
2484                 push = evo_wait(mast, 4);
2485                 if (push) {
2486                         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2487                                 evo_mthd(push, 0x0400 + (or * 0x080), 1);
2488                                 evo_data(push, 0x00000000);
2489                         } else {
2490                                 evo_mthd(push, 0x0180 + (or * 0x020), 1);
2491                                 evo_data(push, 0x00000000);
2492                         }
2493                         evo_kick(push, mast);
2494                 }
2495         }
2496
2497         nv_encoder->crtc = NULL;
2498 }
2499
2500 static void
2501 nv50_dac_enable(struct drm_encoder *encoder)
2502 {
2503         struct nv50_mast *mast = nv50_mast(encoder->dev);
2504         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2505         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2506         struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode;
2507         u32 *push;
2508
2509         push = evo_wait(mast, 8);
2510         if (push) {
2511                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2512                         u32 syncs = 0x00000000;
2513
2514                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2515                                 syncs |= 0x00000001;
2516                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2517                                 syncs |= 0x00000002;
2518
2519                         evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
2520                         evo_data(push, 1 << nv_crtc->index);
2521                         evo_data(push, syncs);
2522                 } else {
2523                         u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
2524                         u32 syncs = 0x00000001;
2525
2526                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2527                                 syncs |= 0x00000008;
2528                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2529                                 syncs |= 0x00000010;
2530
2531                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2532                                 magic |= 0x00000001;
2533
2534                         evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
2535                         evo_data(push, syncs);
2536                         evo_data(push, magic);
2537                         evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
2538                         evo_data(push, 1 << nv_crtc->index);
2539                 }
2540
2541                 evo_kick(push, mast);
2542         }
2543
2544         nv_encoder->crtc = encoder->crtc;
2545 }
2546
2547 static enum drm_connector_status
2548 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2549 {
2550         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2551         struct nv50_disp *disp = nv50_disp(encoder->dev);
2552         struct {
2553                 struct nv50_disp_mthd_v1 base;
2554                 struct nv50_disp_dac_load_v0 load;
2555         } args = {
2556                 .base.version = 1,
2557                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
2558                 .base.hasht  = nv_encoder->dcb->hasht,
2559                 .base.hashm  = nv_encoder->dcb->hashm,
2560         };
2561         int ret;
2562
2563         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
2564         if (args.load.data == 0)
2565                 args.load.data = 340;
2566
2567         ret = nvif_mthd(disp->disp, 0, &args, sizeof(args));
2568         if (ret || !args.load.load)
2569                 return connector_status_disconnected;
2570
2571         return connector_status_connected;
2572 }
2573
2574 static const struct drm_encoder_helper_funcs
2575 nv50_dac_help = {
2576         .dpms = nv50_dac_dpms,
2577         .atomic_check = nv50_outp_atomic_check,
2578         .enable = nv50_dac_enable,
2579         .disable = nv50_dac_disable,
2580         .detect = nv50_dac_detect
2581 };
2582
2583 static void
2584 nv50_dac_destroy(struct drm_encoder *encoder)
2585 {
2586         drm_encoder_cleanup(encoder);
2587         kfree(encoder);
2588 }
2589
2590 static const struct drm_encoder_funcs
2591 nv50_dac_func = {
2592         .destroy = nv50_dac_destroy,
2593 };
2594
2595 static int
2596 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
2597 {
2598         struct nouveau_drm *drm = nouveau_drm(connector->dev);
2599         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
2600         struct nvkm_i2c_bus *bus;
2601         struct nouveau_encoder *nv_encoder;
2602         struct drm_encoder *encoder;
2603         int type = DRM_MODE_ENCODER_DAC;
2604
2605         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2606         if (!nv_encoder)
2607                 return -ENOMEM;
2608         nv_encoder->dcb = dcbe;
2609         nv_encoder->or = ffs(dcbe->or) - 1;
2610
2611         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
2612         if (bus)
2613                 nv_encoder->i2c = &bus->i2c;
2614
2615         encoder = to_drm_encoder(nv_encoder);
2616         encoder->possible_crtcs = dcbe->heads;
2617         encoder->possible_clones = 0;
2618         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
2619                          "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
2620         drm_encoder_helper_add(encoder, &nv50_dac_help);
2621
2622         drm_mode_connector_attach_encoder(connector, encoder);
2623         return 0;
2624 }
2625
2626 /******************************************************************************
2627  * Audio
2628  *****************************************************************************/
2629 static void
2630 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
2631 {
2632         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2633         struct nv50_disp *disp = nv50_disp(encoder->dev);
2634         struct {
2635                 struct nv50_disp_mthd_v1 base;
2636                 struct nv50_disp_sor_hda_eld_v0 eld;
2637         } args = {
2638                 .base.version = 1,
2639                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
2640                 .base.hasht   = nv_encoder->dcb->hasht,
2641                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
2642                                 (0x0100 << nv_crtc->index),
2643         };
2644
2645         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2646 }
2647
2648 static void
2649 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
2650 {
2651         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2652         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2653         struct nouveau_connector *nv_connector;
2654         struct nv50_disp *disp = nv50_disp(encoder->dev);
2655         struct __packed {
2656                 struct {
2657                         struct nv50_disp_mthd_v1 mthd;
2658                         struct nv50_disp_sor_hda_eld_v0 eld;
2659                 } base;
2660                 u8 data[sizeof(nv_connector->base.eld)];
2661         } args = {
2662                 .base.mthd.version = 1,
2663                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
2664                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
2665                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
2666                                      (0x0100 << nv_crtc->index),
2667         };
2668
2669         nv_connector = nouveau_encoder_connector_get(nv_encoder);
2670         if (!drm_detect_monitor_audio(nv_connector->edid))
2671                 return;
2672
2673         drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
2674         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
2675
2676         nvif_mthd(disp->disp, 0, &args,
2677                   sizeof(args.base) + drm_eld_size(args.data));
2678 }
2679
2680 /******************************************************************************
2681  * HDMI
2682  *****************************************************************************/
2683 static void
2684 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
2685 {
2686         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2687         struct nv50_disp *disp = nv50_disp(encoder->dev);
2688         struct {
2689                 struct nv50_disp_mthd_v1 base;
2690                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
2691         } args = {
2692                 .base.version = 1,
2693                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
2694                 .base.hasht  = nv_encoder->dcb->hasht,
2695                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
2696                                (0x0100 << nv_crtc->index),
2697         };
2698
2699         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2700 }
2701
2702 static void
2703 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
2704 {
2705         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2706         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2707         struct nv50_disp *disp = nv50_disp(encoder->dev);
2708         struct {
2709                 struct nv50_disp_mthd_v1 base;
2710                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
2711         } args = {
2712                 .base.version = 1,
2713                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
2714                 .base.hasht  = nv_encoder->dcb->hasht,
2715                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
2716                                (0x0100 << nv_crtc->index),
2717                 .pwr.state = 1,
2718                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
2719         };
2720         struct nouveau_connector *nv_connector;
2721         u32 max_ac_packet;
2722
2723         nv_connector = nouveau_encoder_connector_get(nv_encoder);
2724         if (!drm_detect_hdmi_monitor(nv_connector->edid))
2725                 return;
2726
2727         max_ac_packet  = mode->htotal - mode->hdisplay;
2728         max_ac_packet -= args.pwr.rekey;
2729         max_ac_packet -= 18; /* constant from tegra */
2730         args.pwr.max_ac_packet = max_ac_packet / 32;
2731
2732         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2733         nv50_audio_enable(encoder, mode);
2734 }
2735
2736 /******************************************************************************
2737  * MST
2738  *****************************************************************************/
2739 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
2740 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
2741 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
2742
2743 struct nv50_mstm {
2744         struct nouveau_encoder *outp;
2745
2746         struct drm_dp_mst_topology_mgr mgr;
2747         struct nv50_msto *msto[4];
2748
2749         bool modified;
2750 };
2751
2752 struct nv50_mstc {
2753         struct nv50_mstm *mstm;
2754         struct drm_dp_mst_port *port;
2755         struct drm_connector connector;
2756
2757         struct drm_display_mode *native;
2758         struct edid *edid;
2759
2760         int pbn;
2761 };
2762
2763 struct nv50_msto {
2764         struct drm_encoder encoder;
2765
2766         struct nv50_head *head;
2767         struct nv50_mstc *mstc;
2768         bool disabled;
2769 };
2770
2771 static struct drm_dp_payload *
2772 nv50_msto_payload(struct nv50_msto *msto)
2773 {
2774         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
2775         struct nv50_mstc *mstc = msto->mstc;
2776         struct nv50_mstm *mstm = mstc->mstm;
2777         int vcpi = mstc->port->vcpi.vcpi, i;
2778
2779         NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
2780         for (i = 0; i < mstm->mgr.max_payloads; i++) {
2781                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
2782                 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
2783                           mstm->outp->base.base.name, i, payload->vcpi,
2784                           payload->start_slot, payload->num_slots);
2785         }
2786
2787         for (i = 0; i < mstm->mgr.max_payloads; i++) {
2788                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
2789                 if (payload->vcpi == vcpi)
2790                         return payload;
2791         }
2792
2793         return NULL;
2794 }
2795
2796 static void
2797 nv50_msto_cleanup(struct nv50_msto *msto)
2798 {
2799         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
2800         struct nv50_mstc *mstc = msto->mstc;
2801         struct nv50_mstm *mstm = mstc->mstm;
2802
2803         NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
2804         if (mstc->port && mstc->port->vcpi.vcpi > 0 && !nv50_msto_payload(msto))
2805                 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
2806         if (msto->disabled) {
2807                 msto->mstc = NULL;
2808                 msto->head = NULL;
2809                 msto->disabled = false;
2810         }
2811 }
2812
2813 static void
2814 nv50_msto_prepare(struct nv50_msto *msto)
2815 {
2816         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
2817         struct nv50_mstc *mstc = msto->mstc;
2818         struct nv50_mstm *mstm = mstc->mstm;
2819         struct {
2820                 struct nv50_disp_mthd_v1 base;
2821                 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
2822         } args = {
2823                 .base.version = 1,
2824                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
2825                 .base.hasht  = mstm->outp->dcb->hasht,
2826                 .base.hashm  = (0xf0ff & mstm->outp->dcb->hashm) |
2827                                (0x0100 << msto->head->base.index),
2828         };
2829
2830         NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
2831         if (mstc->port && mstc->port->vcpi.vcpi > 0) {
2832                 struct drm_dp_payload *payload = nv50_msto_payload(msto);
2833                 if (payload) {
2834                         args.vcpi.start_slot = payload->start_slot;
2835                         args.vcpi.num_slots = payload->num_slots;
2836                         args.vcpi.pbn = mstc->port->vcpi.pbn;
2837                         args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
2838                 }
2839         }
2840
2841         NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
2842                   msto->encoder.name, msto->head->base.base.name,
2843                   args.vcpi.start_slot, args.vcpi.num_slots,
2844                   args.vcpi.pbn, args.vcpi.aligned_pbn);
2845         nvif_mthd(&drm->display->disp, 0, &args, sizeof(args));
2846 }
2847
2848 static int
2849 nv50_msto_atomic_check(struct drm_encoder *encoder,
2850                        struct drm_crtc_state *crtc_state,
2851                        struct drm_connector_state *conn_state)
2852 {
2853         struct nv50_mstc *mstc = nv50_mstc(conn_state->connector);
2854         struct nv50_mstm *mstm = mstc->mstm;
2855         int bpp = conn_state->connector->display_info.bpc * 3;
2856         int slots;
2857
2858         mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, bpp);
2859
2860         slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
2861         if (slots < 0)
2862                 return slots;
2863
2864         return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
2865                                            mstc->native);
2866 }
2867
2868 static void
2869 nv50_msto_enable(struct drm_encoder *encoder)
2870 {
2871         struct nv50_head *head = nv50_head(encoder->crtc);
2872         struct nv50_msto *msto = nv50_msto(encoder);
2873         struct nv50_mstc *mstc = NULL;
2874         struct nv50_mstm *mstm = NULL;
2875         struct drm_connector *connector;
2876         u8 proto, depth;
2877         int slots;
2878         bool r;
2879
2880         drm_for_each_connector(connector, encoder->dev) {
2881                 if (connector->state->best_encoder == &msto->encoder) {
2882                         mstc = nv50_mstc(connector);
2883                         mstm = mstc->mstm;
2884                         break;
2885                 }
2886         }
2887
2888         if (WARN_ON(!mstc))
2889                 return;
2890
2891         slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
2892         r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, mstc->pbn, slots);
2893         WARN_ON(!r);
2894
2895         if (mstm->outp->dcb->sorconf.link & 1)
2896                 proto = 0x8;
2897         else
2898                 proto = 0x9;
2899
2900         switch (mstc->connector.display_info.bpc) {
2901         case  6: depth = 0x2; break;
2902         case  8: depth = 0x5; break;
2903         case 10:
2904         default: depth = 0x6; break;
2905         }
2906
2907         mstm->outp->update(mstm->outp, head->base.index,
2908                            &head->base.base.state->adjusted_mode, proto, depth);
2909
2910         msto->head = head;
2911         msto->mstc = mstc;
2912         mstm->modified = true;
2913 }
2914
2915 static void
2916 nv50_msto_disable(struct drm_encoder *encoder)
2917 {
2918         struct nv50_msto *msto = nv50_msto(encoder);
2919         struct nv50_mstc *mstc = msto->mstc;
2920         struct nv50_mstm *mstm = mstc->mstm;
2921
2922         if (mstc->port)
2923                 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
2924
2925         mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
2926         mstm->modified = true;
2927         msto->disabled = true;
2928 }
2929
2930 static const struct drm_encoder_helper_funcs
2931 nv50_msto_help = {
2932         .disable = nv50_msto_disable,
2933         .enable = nv50_msto_enable,
2934         .atomic_check = nv50_msto_atomic_check,
2935 };
2936
2937 static void
2938 nv50_msto_destroy(struct drm_encoder *encoder)
2939 {
2940         struct nv50_msto *msto = nv50_msto(encoder);
2941         drm_encoder_cleanup(&msto->encoder);
2942         kfree(msto);
2943 }
2944
2945 static const struct drm_encoder_funcs
2946 nv50_msto = {
2947         .destroy = nv50_msto_destroy,
2948 };
2949
2950 static int
2951 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id,
2952               struct nv50_msto **pmsto)
2953 {
2954         struct nv50_msto *msto;
2955         int ret;
2956
2957         if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL)))
2958                 return -ENOMEM;
2959
2960         ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
2961                                DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id);
2962         if (ret) {
2963                 kfree(*pmsto);
2964                 *pmsto = NULL;
2965                 return ret;
2966         }
2967
2968         drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
2969         msto->encoder.possible_crtcs = heads;
2970         return 0;
2971 }
2972
2973 static struct drm_encoder *
2974 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
2975                               struct drm_connector_state *connector_state)
2976 {
2977         struct nv50_head *head = nv50_head(connector_state->crtc);
2978         struct nv50_mstc *mstc = nv50_mstc(connector);
2979         if (mstc->port) {
2980                 struct nv50_mstm *mstm = mstc->mstm;
2981                 return &mstm->msto[head->base.index]->encoder;
2982         }
2983         return NULL;
2984 }
2985
2986 static struct drm_encoder *
2987 nv50_mstc_best_encoder(struct drm_connector *connector)
2988 {
2989         struct nv50_mstc *mstc = nv50_mstc(connector);
2990         if (mstc->port) {
2991                 struct nv50_mstm *mstm = mstc->mstm;
2992                 return &mstm->msto[0]->encoder;
2993         }
2994         return NULL;
2995 }
2996
2997 static enum drm_mode_status
2998 nv50_mstc_mode_valid(struct drm_connector *connector,
2999                      struct drm_display_mode *mode)
3000 {
3001         return MODE_OK;
3002 }
3003
3004 static int
3005 nv50_mstc_get_modes(struct drm_connector *connector)
3006 {
3007         struct nv50_mstc *mstc = nv50_mstc(connector);
3008         int ret = 0;
3009
3010         mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
3011         drm_mode_connector_update_edid_property(&mstc->connector, mstc->edid);
3012         if (mstc->edid) {
3013                 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
3014                 drm_edid_to_eld(&mstc->connector, mstc->edid);
3015         }
3016
3017         if (!mstc->connector.display_info.bpc)
3018                 mstc->connector.display_info.bpc = 8;
3019
3020         if (mstc->native)
3021                 drm_mode_destroy(mstc->connector.dev, mstc->native);
3022         mstc->native = nouveau_conn_native_mode(&mstc->connector);
3023         return ret;
3024 }
3025
3026 static const struct drm_connector_helper_funcs
3027 nv50_mstc_help = {
3028         .get_modes = nv50_mstc_get_modes,
3029         .mode_valid = nv50_mstc_mode_valid,
3030         .best_encoder = nv50_mstc_best_encoder,
3031         .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
3032 };
3033
3034 static enum drm_connector_status
3035 nv50_mstc_detect(struct drm_connector *connector, bool force)
3036 {
3037         struct nv50_mstc *mstc = nv50_mstc(connector);
3038         if (!mstc->port)
3039                 return connector_status_disconnected;
3040         return drm_dp_mst_detect_port(connector, mstc->port->mgr, mstc->port);
3041 }
3042
3043 static void
3044 nv50_mstc_destroy(struct drm_connector *connector)
3045 {
3046         struct nv50_mstc *mstc = nv50_mstc(connector);
3047         drm_connector_cleanup(&mstc->connector);
3048         kfree(mstc);
3049 }
3050
3051 static const struct drm_connector_funcs
3052 nv50_mstc = {
3053         .dpms = drm_atomic_helper_connector_dpms,
3054         .reset = nouveau_conn_reset,
3055         .detect = nv50_mstc_detect,
3056         .fill_modes = drm_helper_probe_single_connector_modes,
3057         .set_property = drm_atomic_helper_connector_set_property,
3058         .destroy = nv50_mstc_destroy,
3059         .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
3060         .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
3061         .atomic_set_property = nouveau_conn_atomic_set_property,
3062         .atomic_get_property = nouveau_conn_atomic_get_property,
3063 };
3064
3065 static int
3066 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
3067               const char *path, struct nv50_mstc **pmstc)
3068 {
3069         struct drm_device *dev = mstm->outp->base.base.dev;
3070         struct nv50_mstc *mstc;
3071         int ret, i;
3072
3073         if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
3074                 return -ENOMEM;
3075         mstc->mstm = mstm;
3076         mstc->port = port;
3077
3078         ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
3079                                  DRM_MODE_CONNECTOR_DisplayPort);
3080         if (ret) {
3081                 kfree(*pmstc);
3082                 *pmstc = NULL;
3083                 return ret;
3084         }
3085
3086         drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
3087
3088         mstc->connector.funcs->reset(&mstc->connector);
3089         nouveau_conn_attach_properties(&mstc->connector);
3090
3091         for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto; i++)
3092                 drm_mode_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder);
3093
3094         drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
3095         drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
3096         drm_mode_connector_set_path_property(&mstc->connector, path);
3097         return 0;
3098 }
3099
3100 static void
3101 nv50_mstm_cleanup(struct nv50_mstm *mstm)
3102 {
3103         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
3104         struct drm_encoder *encoder;
3105         int ret;
3106
3107         NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
3108         ret = drm_dp_check_act_status(&mstm->mgr);
3109
3110         ret = drm_dp_update_payload_part2(&mstm->mgr);
3111
3112         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
3113                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
3114                         struct nv50_msto *msto = nv50_msto(encoder);
3115                         struct nv50_mstc *mstc = msto->mstc;
3116                         if (mstc && mstc->mstm == mstm)
3117                                 nv50_msto_cleanup(msto);
3118                 }
3119         }
3120
3121         mstm->modified = false;
3122 }
3123
3124 static void
3125 nv50_mstm_prepare(struct nv50_mstm *mstm)
3126 {
3127         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
3128         struct drm_encoder *encoder;
3129         int ret;
3130
3131         NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
3132         ret = drm_dp_update_payload_part1(&mstm->mgr);
3133
3134         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
3135                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
3136                         struct nv50_msto *msto = nv50_msto(encoder);
3137                         struct nv50_mstc *mstc = msto->mstc;
3138                         if (mstc && mstc->mstm == mstm)
3139                                 nv50_msto_prepare(msto);
3140                 }
3141         }
3142 }
3143
3144 static void
3145 nv50_mstm_hotplug(struct drm_dp_mst_topology_mgr *mgr)
3146 {
3147         struct nv50_mstm *mstm = nv50_mstm(mgr);
3148         drm_kms_helper_hotplug_event(mstm->outp->base.base.dev);
3149 }
3150
3151 static void
3152 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
3153                             struct drm_connector *connector)
3154 {
3155         struct nouveau_drm *drm = nouveau_drm(connector->dev);
3156         struct nv50_mstc *mstc = nv50_mstc(connector);
3157
3158         drm_connector_unregister(&mstc->connector);
3159
3160         drm_modeset_lock_all(drm->dev);
3161         drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
3162         mstc->port = NULL;
3163         drm_modeset_unlock_all(drm->dev);
3164
3165         drm_connector_unreference(&mstc->connector);
3166 }
3167
3168 static void
3169 nv50_mstm_register_connector(struct drm_connector *connector)
3170 {
3171         struct nouveau_drm *drm = nouveau_drm(connector->dev);
3172
3173         drm_modeset_lock_all(drm->dev);
3174         drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
3175         drm_modeset_unlock_all(drm->dev);
3176
3177         drm_connector_register(connector);
3178 }
3179
3180 static struct drm_connector *
3181 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
3182                         struct drm_dp_mst_port *port, const char *path)
3183 {
3184         struct nv50_mstm *mstm = nv50_mstm(mgr);
3185         struct nv50_mstc *mstc;
3186         int ret;
3187
3188         ret = nv50_mstc_new(mstm, port, path, &mstc);
3189         if (ret) {
3190                 if (mstc)
3191                         mstc->connector.funcs->destroy(&mstc->connector);
3192                 return NULL;
3193         }
3194
3195         return &mstc->connector;
3196 }
3197
3198 static const struct drm_dp_mst_topology_cbs
3199 nv50_mstm = {
3200         .add_connector = nv50_mstm_add_connector,
3201         .register_connector = nv50_mstm_register_connector,
3202         .destroy_connector = nv50_mstm_destroy_connector,
3203         .hotplug = nv50_mstm_hotplug,
3204 };
3205
3206 void
3207 nv50_mstm_service(struct nv50_mstm *mstm)
3208 {
3209         struct drm_dp_aux *aux = mstm->mgr.aux;
3210         bool handled = true;
3211         int ret;
3212         u8 esi[8] = {};
3213
3214         while (handled) {
3215                 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
3216                 if (ret != 8) {
3217                         drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
3218                         return;
3219                 }
3220
3221                 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
3222                 if (!handled)
3223                         break;
3224
3225                 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
3226         }
3227 }
3228
3229 void
3230 nv50_mstm_remove(struct nv50_mstm *mstm)
3231 {
3232         if (mstm)
3233                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
3234 }
3235
3236 static int
3237 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
3238 {
3239         struct nouveau_encoder *outp = mstm->outp;
3240         struct {
3241                 struct nv50_disp_mthd_v1 base;
3242                 struct nv50_disp_sor_dp_mst_link_v0 mst;
3243         } args = {
3244                 .base.version = 1,
3245                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
3246                 .base.hasht = outp->dcb->hasht,
3247                 .base.hashm = outp->dcb->hashm,
3248                 .mst.state = state,
3249         };
3250         struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
3251         struct nvif_object *disp = &drm->display->disp;
3252         int ret;
3253
3254         if (dpcd >= 0x12) {
3255                 ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CTRL, &dpcd);
3256                 if (ret < 0)
3257                         return ret;
3258
3259                 dpcd &= ~DP_MST_EN;
3260                 if (state)
3261                         dpcd |= DP_MST_EN;
3262
3263                 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, dpcd);
3264                 if (ret < 0)
3265                         return ret;
3266         }
3267
3268         return nvif_mthd(disp, 0, &args, sizeof(args));
3269 }
3270
3271 int
3272 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
3273 {
3274         int ret, state = 0;
3275
3276         if (!mstm)
3277                 return 0;
3278
3279         if (dpcd[0] >= 0x12) {
3280                 ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CAP, &dpcd[1]);
3281                 if (ret < 0)
3282                         return ret;
3283
3284                 if (!(dpcd[1] & DP_MST_CAP))
3285                         dpcd[0] = 0x11;
3286                 else
3287                         state = allow;
3288         }
3289
3290         ret = nv50_mstm_enable(mstm, dpcd[0], state);
3291         if (ret)
3292                 return ret;
3293
3294         ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, state);
3295         if (ret)
3296                 return nv50_mstm_enable(mstm, dpcd[0], 0);
3297
3298         return mstm->mgr.mst_state;
3299 }
3300
3301 static void
3302 nv50_mstm_fini(struct nv50_mstm *mstm)
3303 {
3304         if (mstm && mstm->mgr.mst_state)
3305                 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
3306 }
3307
3308 static void
3309 nv50_mstm_init(struct nv50_mstm *mstm)
3310 {
3311         if (mstm && mstm->mgr.mst_state)
3312                 drm_dp_mst_topology_mgr_resume(&mstm->mgr);
3313 }
3314
3315 static void
3316 nv50_mstm_del(struct nv50_mstm **pmstm)
3317 {
3318         struct nv50_mstm *mstm = *pmstm;
3319         if (mstm) {
3320                 kfree(*pmstm);
3321                 *pmstm = NULL;
3322         }
3323 }
3324
3325 static int
3326 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
3327               int conn_base_id, struct nv50_mstm **pmstm)
3328 {
3329         const int max_payloads = hweight8(outp->dcb->heads);
3330         struct drm_device *dev = outp->base.base.dev;
3331         struct nv50_mstm *mstm;
3332         int ret, i;
3333         u8 dpcd;
3334
3335         /* This is a workaround for some monitors not functioning
3336          * correctly in MST mode on initial module load.  I think
3337          * some bad interaction with the VBIOS may be responsible.
3338          *
3339          * A good ol' off and on again seems to work here ;)
3340          */
3341         ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
3342         if (ret >= 0 && dpcd >= 0x12)
3343                 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
3344
3345         if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
3346                 return -ENOMEM;
3347         mstm->outp = outp;
3348         mstm->mgr.cbs = &nv50_mstm;
3349
3350         ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
3351                                            max_payloads, conn_base_id);
3352         if (ret)
3353                 return ret;
3354
3355         for (i = 0; i < max_payloads; i++) {
3356                 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name,
3357                                     i, &mstm->msto[i]);
3358                 if (ret)
3359                         return ret;
3360         }
3361
3362         return 0;
3363 }
3364
3365 /******************************************************************************
3366  * SOR
3367  *****************************************************************************/
3368 static void
3369 nv50_sor_dpms(struct drm_encoder *encoder, int mode)
3370 {
3371         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3372         struct nv50_disp *disp = nv50_disp(encoder->dev);
3373         struct {
3374                 struct nv50_disp_mthd_v1 base;
3375                 struct nv50_disp_sor_pwr_v0 pwr;
3376         } args = {
3377                 .base.version = 1,
3378                 .base.method = NV50_DISP_MTHD_V1_SOR_PWR,
3379                 .base.hasht  = nv_encoder->dcb->hasht,
3380                 .base.hashm  = nv_encoder->dcb->hashm,
3381                 .pwr.state = mode == DRM_MODE_DPMS_ON,
3382         };
3383
3384         nvif_mthd(disp->disp, 0, &args, sizeof(args));
3385 }
3386
3387 static void
3388 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
3389                 struct drm_display_mode *mode, u8 proto, u8 depth)
3390 {
3391         struct nv50_dmac *core = &nv50_mast(nv_encoder->base.base.dev)->base;
3392         u32 *push;
3393
3394         if (!mode) {
3395                 nv_encoder->ctrl &= ~BIT(head);
3396                 if (!(nv_encoder->ctrl & 0x0000000f))
3397                         nv_encoder->ctrl = 0;
3398         } else {
3399                 nv_encoder->ctrl |= proto << 8;
3400                 nv_encoder->ctrl |= BIT(head);
3401         }
3402
3403         if ((push = evo_wait(core, 6))) {
3404                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
3405                         if (mode) {
3406                                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
3407                                         nv_encoder->ctrl |= 0x00001000;
3408                                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
3409                                         nv_encoder->ctrl |= 0x00002000;
3410                                 nv_encoder->ctrl |= depth << 16;
3411                         }
3412                         evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1);
3413                 } else {
3414                         if (mode) {
3415                                 u32 magic = 0x31ec6000 | (head << 25);
3416                                 u32 syncs = 0x00000001;
3417                                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
3418                                         syncs |= 0x00000008;
3419                                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
3420                                         syncs |= 0x00000010;
3421                                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
3422                                         magic |= 0x00000001;
3423
3424                                 evo_mthd(push, 0x0404 + (head * 0x300), 2);
3425                                 evo_data(push, syncs | (depth << 6));
3426                                 evo_data(push, magic);
3427                         }
3428                         evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
3429                 }
3430                 evo_data(push, nv_encoder->ctrl);
3431                 evo_kick(push, core);
3432         }
3433 }
3434
3435 static void
3436 nv50_sor_disable(struct drm_encoder *encoder)
3437 {
3438         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3439         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
3440
3441         nv_encoder->crtc = NULL;
3442
3443         if (nv_crtc) {
3444                 struct nvkm_i2c_aux *aux = nv_encoder->aux;
3445                 u8 pwr;
3446
3447                 if (aux) {
3448                         int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
3449                         if (ret == 0) {
3450                                 pwr &= ~DP_SET_POWER_MASK;
3451                                 pwr |=  DP_SET_POWER_D3;
3452                                 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
3453                         }
3454                 }
3455
3456                 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
3457                 nv50_audio_disable(encoder, nv_crtc);
3458                 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
3459         }
3460 }
3461
3462 static void
3463 nv50_sor_enable(struct drm_encoder *encoder)
3464 {
3465         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3466         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
3467         struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode;
3468         struct {
3469                 struct nv50_disp_mthd_v1 base;
3470                 struct nv50_disp_sor_lvds_script_v0 lvds;
3471         } lvds = {
3472                 .base.version = 1,
3473                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
3474                 .base.hasht   = nv_encoder->dcb->hasht,
3475                 .base.hashm   = nv_encoder->dcb->hashm,
3476         };
3477         struct nv50_disp *disp = nv50_disp(encoder->dev);
3478         struct drm_device *dev = encoder->dev;
3479         struct nouveau_drm *drm = nouveau_drm(dev);
3480         struct nouveau_connector *nv_connector;
3481         struct nvbios *bios = &drm->vbios;
3482         u8 proto = 0xf;
3483         u8 depth = 0x0;
3484
3485         nv_connector = nouveau_encoder_connector_get(nv_encoder);
3486         nv_encoder->crtc = encoder->crtc;
3487
3488         switch (nv_encoder->dcb->type) {
3489         case DCB_OUTPUT_TMDS:
3490                 if (nv_encoder->dcb->sorconf.link & 1) {
3491                         proto = 0x1;
3492                         /* Only enable dual-link if:
3493                          *  - Need to (i.e. rate > 165MHz)
3494                          *  - DCB says we can
3495                          *  - Not an HDMI monitor, since there's no dual-link
3496                          *    on HDMI.
3497                          */
3498                         if (mode->clock >= 165000 &&
3499                             nv_encoder->dcb->duallink_possible &&
3500                             !drm_detect_hdmi_monitor(nv_connector->edid))
3501                                 proto |= 0x4;
3502                 } else {
3503                         proto = 0x2;
3504                 }
3505
3506                 nv50_hdmi_enable(&nv_encoder->base.base, mode);
3507                 break;
3508         case DCB_OUTPUT_LVDS:
3509                 proto = 0x0;
3510
3511                 if (bios->fp_no_ddc) {
3512                         if (bios->fp.dual_link)
3513                                 lvds.lvds.script |= 0x0100;
3514                         if (bios->fp.if_is_24bit)
3515                                 lvds.lvds.script |= 0x0200;
3516                 } else {
3517                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
3518                                 if (((u8 *)nv_connector->edid)[121] == 2)
3519                                         lvds.lvds.script |= 0x0100;
3520                         } else
3521                         if (mode->clock >= bios->fp.duallink_transition_clk) {
3522                                 lvds.lvds.script |= 0x0100;
3523                         }
3524
3525                         if (lvds.lvds.script & 0x0100) {
3526                                 if (bios->fp.strapless_is_24bit & 2)
3527                                         lvds.lvds.script |= 0x0200;
3528                         } else {
3529                                 if (bios->fp.strapless_is_24bit & 1)
3530                                         lvds.lvds.script |= 0x0200;
3531                         }
3532
3533                         if (nv_connector->base.display_info.bpc == 8)
3534                                 lvds.lvds.script |= 0x0200;
3535                 }
3536
3537                 nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds));
3538                 break;
3539         case DCB_OUTPUT_DP:
3540                 if (nv_connector->base.display_info.bpc == 6)
3541                         depth = 0x2;
3542                 else
3543                 if (nv_connector->base.display_info.bpc == 8)
3544                         depth = 0x5;
3545                 else
3546                         depth = 0x6;
3547
3548                 if (nv_encoder->dcb->sorconf.link & 1)
3549                         proto = 0x8;
3550                 else
3551                         proto = 0x9;
3552
3553                 nv50_audio_enable(encoder, mode);
3554                 break;
3555         default:
3556                 BUG();
3557                 break;
3558         }
3559
3560         nv_encoder->update(nv_encoder, nv_crtc->index, mode, proto, depth);
3561 }
3562
3563 static const struct drm_encoder_helper_funcs
3564 nv50_sor_help = {
3565         .dpms = nv50_sor_dpms,
3566         .atomic_check = nv50_outp_atomic_check,
3567         .enable = nv50_sor_enable,
3568         .disable = nv50_sor_disable,
3569 };
3570
3571 static void
3572 nv50_sor_destroy(struct drm_encoder *encoder)
3573 {
3574         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3575         nv50_mstm_del(&nv_encoder->dp.mstm);
3576         drm_encoder_cleanup(encoder);
3577         kfree(encoder);
3578 }
3579
3580 static const struct drm_encoder_funcs
3581 nv50_sor_func = {
3582         .destroy = nv50_sor_destroy,
3583 };
3584
3585 static int
3586 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
3587 {
3588         struct nouveau_connector *nv_connector = nouveau_connector(connector);
3589         struct nouveau_drm *drm = nouveau_drm(connector->dev);
3590         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
3591         struct nouveau_encoder *nv_encoder;
3592         struct drm_encoder *encoder;
3593         int type, ret;
3594
3595         switch (dcbe->type) {
3596         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
3597         case DCB_OUTPUT_TMDS:
3598         case DCB_OUTPUT_DP:
3599         default:
3600                 type = DRM_MODE_ENCODER_TMDS;
3601                 break;
3602         }
3603
3604         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
3605         if (!nv_encoder)
3606                 return -ENOMEM;
3607         nv_encoder->dcb = dcbe;
3608         nv_encoder->or = ffs(dcbe->or) - 1;
3609         nv_encoder->update = nv50_sor_update;
3610
3611         encoder = to_drm_encoder(nv_encoder);
3612         encoder->possible_crtcs = dcbe->heads;
3613         encoder->possible_clones = 0;
3614         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
3615                          "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
3616         drm_encoder_helper_add(encoder, &nv50_sor_help);
3617
3618         drm_mode_connector_attach_encoder(connector, encoder);
3619
3620         if (dcbe->type == DCB_OUTPUT_DP) {
3621                 struct nvkm_i2c_aux *aux =
3622                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
3623                 if (aux) {
3624                         nv_encoder->i2c = &nv_connector->aux.ddc;
3625                         nv_encoder->aux = aux;
3626                 }
3627
3628                 /*TODO: Use DP Info Table to check for support. */
3629                 if (nv50_disp(encoder->dev)->disp->oclass >= GF110_DISP) {
3630                         ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
3631                                             nv_connector->base.base.id,
3632                                             &nv_encoder->dp.mstm);
3633                         if (ret)
3634                                 return ret;
3635                 }
3636         } else {
3637                 struct nvkm_i2c_bus *bus =
3638                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
3639                 if (bus)
3640                         nv_encoder->i2c = &bus->i2c;
3641         }
3642
3643         return 0;
3644 }
3645
3646 /******************************************************************************
3647  * PIOR
3648  *****************************************************************************/
3649 static void
3650 nv50_pior_dpms(struct drm_encoder *encoder, int mode)
3651 {
3652         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3653         struct nv50_disp *disp = nv50_disp(encoder->dev);
3654         struct {
3655                 struct nv50_disp_mthd_v1 base;
3656                 struct nv50_disp_pior_pwr_v0 pwr;
3657         } args = {
3658                 .base.version = 1,
3659                 .base.method = NV50_DISP_MTHD_V1_PIOR_PWR,
3660                 .base.hasht  = nv_encoder->dcb->hasht,
3661                 .base.hashm  = nv_encoder->dcb->hashm,
3662                 .pwr.state = mode == DRM_MODE_DPMS_ON,
3663                 .pwr.type = nv_encoder->dcb->type,
3664         };
3665
3666         nvif_mthd(disp->disp, 0, &args, sizeof(args));
3667 }
3668
3669 static int
3670 nv50_pior_atomic_check(struct drm_encoder *encoder,
3671                        struct drm_crtc_state *crtc_state,
3672                        struct drm_connector_state *conn_state)
3673 {
3674         int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
3675         if (ret)
3676                 return ret;
3677         crtc_state->adjusted_mode.clock *= 2;
3678         return 0;
3679 }
3680
3681 static void
3682 nv50_pior_disable(struct drm_encoder *encoder)
3683 {
3684         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3685         struct nv50_mast *mast = nv50_mast(encoder->dev);
3686         const int or = nv_encoder->or;
3687         u32 *push;
3688
3689         if (nv_encoder->crtc) {
3690                 push = evo_wait(mast, 4);
3691                 if (push) {
3692                         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
3693                                 evo_mthd(push, 0x0700 + (or * 0x040), 1);
3694                                 evo_data(push, 0x00000000);
3695                         }
3696                         evo_kick(push, mast);
3697                 }
3698         }
3699
3700         nv_encoder->crtc = NULL;
3701 }
3702
3703 static void
3704 nv50_pior_enable(struct drm_encoder *encoder)
3705 {
3706         struct nv50_mast *mast = nv50_mast(encoder->dev);
3707         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3708         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
3709         struct nouveau_connector *nv_connector;
3710         struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode;
3711         u8 owner = 1 << nv_crtc->index;
3712         u8 proto, depth;
3713         u32 *push;
3714
3715         nv_connector = nouveau_encoder_connector_get(nv_encoder);
3716         switch (nv_connector->base.display_info.bpc) {
3717         case 10: depth = 0x6; break;
3718         case  8: depth = 0x5; break;
3719         case  6: depth = 0x2; break;
3720         default: depth = 0x0; break;
3721         }
3722
3723         switch (nv_encoder->dcb->type) {
3724         case DCB_OUTPUT_TMDS:
3725         case DCB_OUTPUT_DP:
3726                 proto = 0x0;
3727                 break;
3728         default:
3729                 BUG();
3730                 break;
3731         }
3732
3733         push = evo_wait(mast, 8);
3734         if (push) {
3735                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
3736                         u32 ctrl = (depth << 16) | (proto << 8) | owner;
3737                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
3738                                 ctrl |= 0x00001000;
3739                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
3740                                 ctrl |= 0x00002000;
3741                         evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
3742                         evo_data(push, ctrl);
3743                 }
3744
3745                 evo_kick(push, mast);
3746         }
3747
3748         nv_encoder->crtc = encoder->crtc;
3749 }
3750
3751 static const struct drm_encoder_helper_funcs
3752 nv50_pior_help = {
3753         .dpms = nv50_pior_dpms,
3754         .atomic_check = nv50_pior_atomic_check,
3755         .enable = nv50_pior_enable,
3756         .disable = nv50_pior_disable,
3757 };
3758
3759 static void
3760 nv50_pior_destroy(struct drm_encoder *encoder)
3761 {
3762         drm_encoder_cleanup(encoder);
3763         kfree(encoder);
3764 }
3765
3766 static const struct drm_encoder_funcs
3767 nv50_pior_func = {
3768         .destroy = nv50_pior_destroy,
3769 };
3770
3771 static int
3772 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
3773 {
3774         struct nouveau_connector *nv_connector = nouveau_connector(connector);
3775         struct nouveau_drm *drm = nouveau_drm(connector->dev);
3776         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
3777         struct nvkm_i2c_bus *bus = NULL;
3778         struct nvkm_i2c_aux *aux = NULL;
3779         struct i2c_adapter *ddc;
3780         struct nouveau_encoder *nv_encoder;
3781         struct drm_encoder *encoder;
3782         int type;
3783
3784         switch (dcbe->type) {
3785         case DCB_OUTPUT_TMDS:
3786                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
3787                 ddc  = bus ? &bus->i2c : NULL;
3788                 type = DRM_MODE_ENCODER_TMDS;
3789                 break;
3790         case DCB_OUTPUT_DP:
3791                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
3792                 ddc  = aux ? &nv_connector->aux.ddc : NULL;
3793                 type = DRM_MODE_ENCODER_TMDS;
3794                 break;
3795         default:
3796                 return -ENODEV;
3797         }
3798
3799         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
3800         if (!nv_encoder)
3801                 return -ENOMEM;
3802         nv_encoder->dcb = dcbe;
3803         nv_encoder->or = ffs(dcbe->or) - 1;
3804         nv_encoder->i2c = ddc;
3805         nv_encoder->aux = aux;
3806
3807         encoder = to_drm_encoder(nv_encoder);
3808         encoder->possible_crtcs = dcbe->heads;
3809         encoder->possible_clones = 0;
3810         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
3811                          "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
3812         drm_encoder_helper_add(encoder, &nv50_pior_help);
3813
3814         drm_mode_connector_attach_encoder(connector, encoder);
3815         return 0;
3816 }
3817
3818 /******************************************************************************
3819  * Atomic
3820  *****************************************************************************/
3821
3822 static void
3823 nv50_disp_atomic_commit_core(struct nouveau_drm *drm, u32 interlock)
3824 {
3825         struct nv50_disp *disp = nv50_disp(drm->dev);
3826         struct nv50_dmac *core = &disp->mast.base;
3827         struct nv50_mstm *mstm;
3828         struct drm_encoder *encoder;
3829         u32 *push;
3830
3831         NV_ATOMIC(drm, "commit core %08x\n", interlock);
3832
3833         drm_for_each_encoder(encoder, drm->dev) {
3834                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
3835                         mstm = nouveau_encoder(encoder)->dp.mstm;
3836                         if (mstm && mstm->modified)
3837                                 nv50_mstm_prepare(mstm);
3838                 }
3839         }
3840
3841         if ((push = evo_wait(core, 5))) {
3842                 evo_mthd(push, 0x0084, 1);
3843                 evo_data(push, 0x80000000);
3844                 evo_mthd(push, 0x0080, 2);
3845                 evo_data(push, interlock);
3846                 evo_data(push, 0x00000000);
3847                 nouveau_bo_wr32(disp->sync, 0, 0x00000000);
3848                 evo_kick(push, core);
3849                 if (nvif_msec(&drm->client.device, 2000ULL,
3850                         if (nouveau_bo_rd32(disp->sync, 0))
3851                                 break;
3852                         usleep_range(1, 2);
3853                 ) < 0)
3854                         NV_ERROR(drm, "EVO timeout\n");
3855         }
3856
3857         drm_for_each_encoder(encoder, drm->dev) {
3858                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
3859                         mstm = nouveau_encoder(encoder)->dp.mstm;
3860                         if (mstm && mstm->modified)
3861                                 nv50_mstm_cleanup(mstm);
3862                 }
3863         }
3864 }
3865
3866 static void
3867 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
3868 {
3869         struct drm_device *dev = state->dev;
3870         struct drm_crtc_state *crtc_state;
3871         struct drm_crtc *crtc;
3872         struct drm_plane_state *plane_state;
3873         struct drm_plane *plane;
3874         struct nouveau_drm *drm = nouveau_drm(dev);
3875         struct nv50_disp *disp = nv50_disp(dev);
3876         struct nv50_atom *atom = nv50_atom(state);
3877         struct nv50_outp_atom *outp, *outt;
3878         u32 interlock_core = 0;
3879         u32 interlock_chan = 0;
3880         int i;
3881
3882         NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
3883         drm_atomic_helper_wait_for_fences(dev, state, false);
3884         drm_atomic_helper_wait_for_dependencies(state);
3885         drm_atomic_helper_update_legacy_modeset_state(dev, state);
3886
3887         if (atom->lock_core)
3888                 mutex_lock(&disp->mutex);
3889
3890         /* Disable head(s). */
3891         for_each_crtc_in_state(state, crtc, crtc_state, i) {
3892                 struct nv50_head_atom *asyh = nv50_head_atom(crtc->state);
3893                 struct nv50_head *head = nv50_head(crtc);
3894
3895                 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
3896                           asyh->clr.mask, asyh->set.mask);
3897
3898                 if (asyh->clr.mask) {
3899                         nv50_head_flush_clr(head, asyh, atom->flush_disable);
3900                         interlock_core |= 1;
3901                 }
3902         }
3903
3904         /* Disable plane(s). */
3905         for_each_plane_in_state(state, plane, plane_state, i) {
3906                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane->state);
3907                 struct nv50_wndw *wndw = nv50_wndw(plane);
3908
3909                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
3910                           asyw->clr.mask, asyw->set.mask);
3911                 if (!asyw->clr.mask)
3912                         continue;
3913
3914                 interlock_chan |= nv50_wndw_flush_clr(wndw, interlock_core,
3915                                                       atom->flush_disable,
3916                                                       asyw);
3917         }
3918
3919         /* Disable output path(s). */
3920         list_for_each_entry(outp, &atom->outp, head) {
3921                 const struct drm_encoder_helper_funcs *help;
3922                 struct drm_encoder *encoder;
3923
3924                 encoder = outp->encoder;
3925                 help = encoder->helper_private;
3926
3927                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
3928                           outp->clr.mask, outp->set.mask);
3929
3930                 if (outp->clr.mask) {
3931                         help->disable(encoder);
3932                         interlock_core |= 1;
3933                         if (outp->flush_disable) {
3934                                 nv50_disp_atomic_commit_core(drm, interlock_chan);
3935                                 interlock_core = 0;
3936                                 interlock_chan = 0;
3937                         }
3938                 }
3939         }
3940
3941         /* Flush disable. */
3942         if (interlock_core) {
3943                 if (atom->flush_disable) {
3944                         nv50_disp_atomic_commit_core(drm, interlock_chan);
3945                         interlock_core = 0;
3946                         interlock_chan = 0;
3947                 }
3948         }
3949
3950         /* Update output path(s). */
3951         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
3952                 const struct drm_encoder_helper_funcs *help;
3953                 struct drm_encoder *encoder;
3954
3955                 encoder = outp->encoder;
3956                 help = encoder->helper_private;
3957
3958                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
3959                           outp->set.mask, outp->clr.mask);
3960
3961                 if (outp->set.mask) {
3962                         help->enable(encoder);
3963                         interlock_core = 1;
3964                 }
3965
3966                 list_del(&outp->head);
3967                 kfree(outp);
3968         }
3969
3970         /* Update head(s). */
3971         for_each_crtc_in_state(state, crtc, crtc_state, i) {
3972                 struct nv50_head_atom *asyh = nv50_head_atom(crtc->state);
3973                 struct nv50_head *head = nv50_head(crtc);
3974
3975                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
3976                           asyh->set.mask, asyh->clr.mask);
3977
3978                 if (asyh->set.mask) {
3979                         nv50_head_flush_set(head, asyh);
3980                         interlock_core = 1;
3981                 }
3982         }
3983
3984         for_each_crtc_in_state(state, crtc, crtc_state, i) {
3985                 if (crtc->state->event)
3986                         drm_crtc_vblank_get(crtc);
3987         }
3988
3989         /* Update plane(s). */
3990         for_each_plane_in_state(state, plane, plane_state, i) {
3991                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane->state);
3992                 struct nv50_wndw *wndw = nv50_wndw(plane);
3993
3994                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
3995                           asyw->set.mask, asyw->clr.mask);
3996                 if ( !asyw->set.mask &&
3997                     (!asyw->clr.mask || atom->flush_disable))
3998                         continue;
3999
4000                 interlock_chan |= nv50_wndw_flush_set(wndw, interlock_core, asyw);
4001         }
4002
4003         /* Flush update. */
4004         if (interlock_core) {
4005                 if (!interlock_chan && atom->state.legacy_cursor_update) {
4006                         u32 *push = evo_wait(&disp->mast, 2);
4007                         if (push) {
4008                                 evo_mthd(push, 0x0080, 1);
4009                                 evo_data(push, 0x00000000);
4010                                 evo_kick(push, &disp->mast);
4011                         }
4012                 } else {
4013                         nv50_disp_atomic_commit_core(drm, interlock_chan);
4014                 }
4015         }
4016
4017         if (atom->lock_core)
4018                 mutex_unlock(&disp->mutex);
4019
4020         /* Wait for HW to signal completion. */
4021         for_each_plane_in_state(state, plane, plane_state, i) {
4022                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane->state);
4023                 struct nv50_wndw *wndw = nv50_wndw(plane);
4024                 int ret = nv50_wndw_wait_armed(wndw, asyw);
4025                 if (ret)
4026                         NV_ERROR(drm, "%s: timeout\n", plane->name);
4027         }
4028
4029         for_each_crtc_in_state(state, crtc, crtc_state, i) {
4030                 if (crtc->state->event) {
4031                         unsigned long flags;
4032                         /* Get correct count/ts if racing with vblank irq */
4033                         drm_accurate_vblank_count(crtc);
4034                         spin_lock_irqsave(&crtc->dev->event_lock, flags);
4035                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
4036                         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4037                         crtc->state->event = NULL;
4038                         drm_crtc_vblank_put(crtc);
4039                 }
4040         }
4041
4042         drm_atomic_helper_commit_hw_done(state);
4043         drm_atomic_helper_cleanup_planes(dev, state);
4044         drm_atomic_helper_commit_cleanup_done(state);
4045         drm_atomic_state_put(state);
4046 }
4047
4048 static void
4049 nv50_disp_atomic_commit_work(struct work_struct *work)
4050 {
4051         struct drm_atomic_state *state =
4052                 container_of(work, typeof(*state), commit_work);
4053         nv50_disp_atomic_commit_tail(state);
4054 }
4055
4056 static int
4057 nv50_disp_atomic_commit(struct drm_device *dev,
4058                         struct drm_atomic_state *state, bool nonblock)
4059 {
4060         struct nouveau_drm *drm = nouveau_drm(dev);
4061         struct nv50_disp *disp = nv50_disp(dev);
4062         struct drm_plane_state *plane_state;
4063         struct drm_plane *plane;
4064         struct drm_crtc *crtc;
4065         bool active = false;
4066         int ret, i;
4067
4068         ret = pm_runtime_get_sync(dev->dev);
4069         if (ret < 0 && ret != -EACCES)
4070                 return ret;
4071
4072         ret = drm_atomic_helper_setup_commit(state, nonblock);
4073         if (ret)
4074                 goto done;
4075
4076         INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
4077
4078         ret = drm_atomic_helper_prepare_planes(dev, state);
4079         if (ret)
4080                 goto done;
4081
4082         if (!nonblock) {
4083                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
4084                 if (ret)
4085                         goto done;
4086         }
4087
4088         for_each_plane_in_state(state, plane, plane_state, i) {
4089                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane_state);
4090                 struct nv50_wndw *wndw = nv50_wndw(plane);
4091                 if (asyw->set.image) {
4092                         asyw->ntfy.handle = wndw->dmac->sync.handle;
4093                         asyw->ntfy.offset = wndw->ntfy;
4094                         asyw->ntfy.awaken = false;
4095                         asyw->set.ntfy = true;
4096                         nouveau_bo_wr32(disp->sync, wndw->ntfy / 4, 0x00000000);
4097                         wndw->ntfy ^= 0x10;
4098                 }
4099         }
4100
4101         drm_atomic_helper_swap_state(state, true);
4102         drm_atomic_state_get(state);
4103
4104         if (nonblock)
4105                 queue_work(system_unbound_wq, &state->commit_work);
4106         else
4107                 nv50_disp_atomic_commit_tail(state);
4108
4109         drm_for_each_crtc(crtc, dev) {
4110                 if (crtc->state->enable) {
4111                         if (!drm->have_disp_power_ref) {
4112                                 drm->have_disp_power_ref = true;
4113                                 return ret;
4114                         }
4115                         active = true;
4116                         break;
4117                 }
4118         }
4119
4120         if (!active && drm->have_disp_power_ref) {
4121                 pm_runtime_put_autosuspend(dev->dev);
4122                 drm->have_disp_power_ref = false;
4123         }
4124
4125 done:
4126         pm_runtime_put_autosuspend(dev->dev);
4127         return ret;
4128 }
4129
4130 static struct nv50_outp_atom *
4131 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
4132 {
4133         struct nv50_outp_atom *outp;
4134
4135         list_for_each_entry(outp, &atom->outp, head) {
4136                 if (outp->encoder == encoder)
4137                         return outp;
4138         }
4139
4140         outp = kzalloc(sizeof(*outp), GFP_KERNEL);
4141         if (!outp)
4142                 return ERR_PTR(-ENOMEM);
4143
4144         list_add(&outp->head, &atom->outp);
4145         outp->encoder = encoder;
4146         return outp;
4147 }
4148
4149 static int
4150 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
4151                                 struct drm_connector *connector)
4152 {
4153         struct drm_encoder *encoder = connector->state->best_encoder;
4154         struct drm_crtc_state *crtc_state;
4155         struct drm_crtc *crtc;
4156         struct nv50_outp_atom *outp;
4157
4158         if (!(crtc = connector->state->crtc))
4159                 return 0;
4160
4161         crtc_state = drm_atomic_get_existing_crtc_state(&atom->state, crtc);
4162         if (crtc->state->active && drm_atomic_crtc_needs_modeset(crtc_state)) {
4163                 outp = nv50_disp_outp_atomic_add(atom, encoder);
4164                 if (IS_ERR(outp))
4165                         return PTR_ERR(outp);
4166
4167                 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
4168                         outp->flush_disable = true;
4169                         atom->flush_disable = true;
4170                 }
4171                 outp->clr.ctrl = true;
4172                 atom->lock_core = true;
4173         }
4174
4175         return 0;
4176 }
4177
4178 static int
4179 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
4180                                 struct drm_connector_state *connector_state)
4181 {
4182         struct drm_encoder *encoder = connector_state->best_encoder;
4183         struct drm_crtc_state *crtc_state;
4184         struct drm_crtc *crtc;
4185         struct nv50_outp_atom *outp;
4186
4187         if (!(crtc = connector_state->crtc))
4188                 return 0;
4189
4190         crtc_state = drm_atomic_get_existing_crtc_state(&atom->state, crtc);
4191         if (crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state)) {
4192                 outp = nv50_disp_outp_atomic_add(atom, encoder);
4193                 if (IS_ERR(outp))
4194                         return PTR_ERR(outp);
4195
4196                 outp->set.ctrl = true;
4197                 atom->lock_core = true;
4198         }
4199
4200         return 0;
4201 }
4202
4203 static int
4204 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
4205 {
4206         struct nv50_atom *atom = nv50_atom(state);
4207         struct drm_connector_state *connector_state;
4208         struct drm_connector *connector;
4209         int ret, i;
4210
4211         ret = drm_atomic_helper_check(dev, state);
4212         if (ret)
4213                 return ret;
4214
4215         for_each_connector_in_state(state, connector, connector_state, i) {
4216                 ret = nv50_disp_outp_atomic_check_clr(atom, connector);
4217                 if (ret)
4218                         return ret;
4219
4220                 ret = nv50_disp_outp_atomic_check_set(atom, connector_state);
4221                 if (ret)
4222                         return ret;
4223         }
4224
4225         return 0;
4226 }
4227
4228 static void
4229 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
4230 {
4231         struct nv50_atom *atom = nv50_atom(state);
4232         struct nv50_outp_atom *outp, *outt;
4233
4234         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
4235                 list_del(&outp->head);
4236                 kfree(outp);
4237         }
4238
4239         drm_atomic_state_default_clear(state);
4240 }
4241
4242 static void
4243 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
4244 {
4245         struct nv50_atom *atom = nv50_atom(state);
4246         drm_atomic_state_default_release(&atom->state);
4247         kfree(atom);
4248 }
4249
4250 static struct drm_atomic_state *
4251 nv50_disp_atomic_state_alloc(struct drm_device *dev)
4252 {
4253         struct nv50_atom *atom;
4254         if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
4255             drm_atomic_state_init(dev, &atom->state) < 0) {
4256                 kfree(atom);
4257                 return NULL;
4258         }
4259         INIT_LIST_HEAD(&atom->outp);
4260         return &atom->state;
4261 }
4262
4263 static const struct drm_mode_config_funcs
4264 nv50_disp_func = {
4265         .fb_create = nouveau_user_framebuffer_create,
4266         .output_poll_changed = nouveau_fbcon_output_poll_changed,
4267         .atomic_check = nv50_disp_atomic_check,
4268         .atomic_commit = nv50_disp_atomic_commit,
4269         .atomic_state_alloc = nv50_disp_atomic_state_alloc,
4270         .atomic_state_clear = nv50_disp_atomic_state_clear,
4271         .atomic_state_free = nv50_disp_atomic_state_free,
4272 };
4273
4274 /******************************************************************************
4275  * Init
4276  *****************************************************************************/
4277
4278 void
4279 nv50_display_fini(struct drm_device *dev)
4280 {
4281         struct nouveau_encoder *nv_encoder;
4282         struct drm_encoder *encoder;
4283         struct drm_plane *plane;
4284
4285         drm_for_each_plane(plane, dev) {
4286                 struct nv50_wndw *wndw = nv50_wndw(plane);
4287                 if (plane->funcs != &nv50_wndw)
4288                         continue;
4289                 nv50_wndw_fini(wndw);
4290         }
4291
4292         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4293                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
4294                         nv_encoder = nouveau_encoder(encoder);
4295                         nv50_mstm_fini(nv_encoder->dp.mstm);
4296                 }
4297         }
4298 }
4299
4300 int
4301 nv50_display_init(struct drm_device *dev)
4302 {
4303         struct drm_encoder *encoder;
4304         struct drm_plane *plane;
4305         struct drm_crtc *crtc;
4306         u32 *push;
4307
4308         push = evo_wait(nv50_mast(dev), 32);
4309         if (!push)
4310                 return -EBUSY;
4311
4312         evo_mthd(push, 0x0088, 1);
4313         evo_data(push, nv50_mast(dev)->base.sync.handle);
4314         evo_kick(push, nv50_mast(dev));
4315
4316         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4317                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
4318                         const struct drm_encoder_helper_funcs *help;
4319                         struct nouveau_encoder *nv_encoder;
4320
4321                         nv_encoder = nouveau_encoder(encoder);
4322                         help = encoder->helper_private;
4323                         if (help && help->dpms)
4324                                 help->dpms(encoder, DRM_MODE_DPMS_ON);
4325
4326                         nv50_mstm_init(nv_encoder->dp.mstm);
4327                 }
4328         }
4329
4330         drm_for_each_crtc(crtc, dev) {
4331                 nv50_head_lut_load(crtc);
4332         }
4333
4334         drm_for_each_plane(plane, dev) {
4335                 struct nv50_wndw *wndw = nv50_wndw(plane);
4336                 if (plane->funcs != &nv50_wndw)
4337                         continue;
4338                 nv50_wndw_init(wndw);
4339         }
4340
4341         return 0;
4342 }
4343
4344 void
4345 nv50_display_destroy(struct drm_device *dev)
4346 {
4347         struct nv50_disp *disp = nv50_disp(dev);
4348
4349         nv50_dmac_destroy(&disp->mast.base, disp->disp);
4350
4351         nouveau_bo_unmap(disp->sync);
4352         if (disp->sync)
4353                 nouveau_bo_unpin(disp->sync);
4354         nouveau_bo_ref(NULL, &disp->sync);
4355
4356         nouveau_display(dev)->priv = NULL;
4357         kfree(disp);
4358 }
4359
4360 MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)");
4361 static int nouveau_atomic = 0;
4362 module_param_named(atomic, nouveau_atomic, int, 0400);
4363
4364 int
4365 nv50_display_create(struct drm_device *dev)
4366 {
4367         struct nvif_device *device = &nouveau_drm(dev)->client.device;
4368         struct nouveau_drm *drm = nouveau_drm(dev);
4369         struct dcb_table *dcb = &drm->vbios.dcb;
4370         struct drm_connector *connector, *tmp;
4371         struct nv50_disp *disp;
4372         struct dcb_output *dcbe;
4373         int crtcs, ret, i;
4374
4375         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
4376         if (!disp)
4377                 return -ENOMEM;
4378
4379         mutex_init(&disp->mutex);
4380
4381         nouveau_display(dev)->priv = disp;
4382         nouveau_display(dev)->dtor = nv50_display_destroy;
4383         nouveau_display(dev)->init = nv50_display_init;
4384         nouveau_display(dev)->fini = nv50_display_fini;
4385         disp->disp = &nouveau_display(dev)->disp;
4386         dev->mode_config.funcs = &nv50_disp_func;
4387         if (nouveau_atomic)
4388                 dev->driver->driver_features |= DRIVER_ATOMIC;
4389
4390         /* small shared memory area we use for notifiers and semaphores */
4391         ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
4392                              0, 0x0000, NULL, NULL, &disp->sync);
4393         if (!ret) {
4394                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
4395                 if (!ret) {
4396                         ret = nouveau_bo_map(disp->sync);
4397                         if (ret)
4398                                 nouveau_bo_unpin(disp->sync);
4399                 }
4400                 if (ret)
4401                         nouveau_bo_ref(NULL, &disp->sync);
4402         }
4403
4404         if (ret)
4405                 goto out;
4406
4407         /* allocate master evo channel */
4408         ret = nv50_core_create(device, disp->disp, disp->sync->bo.offset,
4409                               &disp->mast);
4410         if (ret)
4411                 goto out;
4412
4413         /* create crtc objects to represent the hw heads */
4414         if (disp->disp->oclass >= GF110_DISP)
4415                 crtcs = nvif_rd32(&device->object, 0x022448);
4416         else
4417                 crtcs = 2;
4418
4419         for (i = 0; i < crtcs; i++) {
4420                 ret = nv50_head_create(dev, i);
4421                 if (ret)
4422                         goto out;
4423         }
4424
4425         /* create encoder/connector objects based on VBIOS DCB table */
4426         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
4427                 connector = nouveau_connector_create(dev, dcbe->connector);
4428                 if (IS_ERR(connector))
4429                         continue;
4430
4431                 if (dcbe->location == DCB_LOC_ON_CHIP) {
4432                         switch (dcbe->type) {
4433                         case DCB_OUTPUT_TMDS:
4434                         case DCB_OUTPUT_LVDS:
4435                         case DCB_OUTPUT_DP:
4436                                 ret = nv50_sor_create(connector, dcbe);
4437                                 break;
4438                         case DCB_OUTPUT_ANALOG:
4439                                 ret = nv50_dac_create(connector, dcbe);
4440                                 break;
4441                         default:
4442                                 ret = -ENODEV;
4443                                 break;
4444                         }
4445                 } else {
4446                         ret = nv50_pior_create(connector, dcbe);
4447                 }
4448
4449                 if (ret) {
4450                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
4451                                      dcbe->location, dcbe->type,
4452                                      ffs(dcbe->or) - 1, ret);
4453                         ret = 0;
4454                 }
4455         }
4456
4457         /* cull any connectors we created that don't have an encoder */
4458         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
4459                 if (connector->encoder_ids[0])
4460                         continue;
4461
4462                 NV_WARN(drm, "%s has no encoders, removing\n",
4463                         connector->name);
4464                 connector->funcs->destroy(connector);
4465         }
4466
4467 out:
4468         if (ret)
4469                 nv50_display_destroy(dev);
4470         return ret;
4471 }