2 * Copyright 2011 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/dma-mapping.h>
28 #include <drm/drm_crtc_helper.h>
30 #include "nouveau_drm.h"
31 #include "nouveau_dma.h"
32 #include "nouveau_gem.h"
33 #include "nouveau_connector.h"
34 #include "nouveau_encoder.h"
35 #include "nouveau_crtc.h"
36 #include "nouveau_fence.h"
37 #include "nv50_display.h"
39 #include <core/client.h>
40 #include <core/gpuobj.h>
41 #include <core/class.h>
43 #include <subdev/timer.h>
44 #include <subdev/bar.h>
45 #include <subdev/fb.h>
49 #define EVO_MASTER (0x00)
50 #define EVO_FLIP(c) (0x01 + (c))
51 #define EVO_OVLY(c) (0x05 + (c))
52 #define EVO_OIMM(c) (0x09 + (c))
53 #define EVO_CURS(c) (0x0d + (c))
55 /* offsets in shared sync bo of various structures */
56 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
57 #define EVO_MAST_NTFY EVO_SYNC( 0, 0x00)
58 #define EVO_FLIP_SEM0(c) EVO_SYNC((c), 0x00)
59 #define EVO_FLIP_SEM1(c) EVO_SYNC((c), 0x10)
61 #define EVO_CORE_HANDLE (0xd1500000)
62 #define EVO_CHAN_HANDLE(t,i) (0xd15c0000 | (((t) & 0x00ff) << 8) | (i))
63 #define EVO_CHAN_OCLASS(t,c) ((nv_hclass(c) & 0xff00) | ((t) & 0x00ff))
64 #define EVO_PUSH_HANDLE(t,i) (0xd15b0000 | (i) | \
65 (((NV50_DISP_##t##_CLASS) & 0x00ff) << 8))
67 /******************************************************************************
69 *****************************************************************************/
72 struct nouveau_object *user;
77 nv50_chan_create(struct nouveau_object *core, u32 bclass, u8 head,
78 void *data, u32 size, struct nv50_chan *chan)
80 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
81 const u32 oclass = EVO_CHAN_OCLASS(bclass, core);
82 const u32 handle = EVO_CHAN_HANDLE(bclass, head);
85 ret = nouveau_object_new(client, EVO_CORE_HANDLE, handle,
86 oclass, data, size, &chan->user);
90 chan->handle = handle;
95 nv50_chan_destroy(struct nouveau_object *core, struct nv50_chan *chan)
97 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
99 nouveau_object_del(client, EVO_CORE_HANDLE, chan->handle);
102 /******************************************************************************
104 *****************************************************************************/
107 struct nv50_chan base;
111 nv50_pioc_destroy(struct nouveau_object *core, struct nv50_pioc *pioc)
113 nv50_chan_destroy(core, &pioc->base);
117 nv50_pioc_create(struct nouveau_object *core, u32 bclass, u8 head,
118 void *data, u32 size, struct nv50_pioc *pioc)
120 return nv50_chan_create(core, bclass, head, data, size, &pioc->base);
123 /******************************************************************************
125 *****************************************************************************/
128 struct nv50_chan base;
134 nv50_dmac_destroy(struct nouveau_object *core, struct nv50_dmac *dmac)
137 struct pci_dev *pdev = nv_device(core)->pdev;
138 pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle);
141 nv50_chan_destroy(core, &dmac->base);
145 nv50_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
147 struct nouveau_fb *pfb = nouveau_fb(core);
148 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
149 struct nouveau_object *object;
150 int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
151 NV_DMA_IN_MEMORY_CLASS,
152 &(struct nv_dma_class) {
153 .flags = NV_DMA_TARGET_VRAM |
156 .limit = pfb->ram.size - 1,
157 .conf0 = NV50_DMA_CONF0_ENABLE |
158 NV50_DMA_CONF0_PART_256,
159 }, sizeof(struct nv_dma_class), &object);
163 ret = nouveau_object_new(client, parent, NvEvoFB16,
164 NV_DMA_IN_MEMORY_CLASS,
165 &(struct nv_dma_class) {
166 .flags = NV_DMA_TARGET_VRAM |
169 .limit = pfb->ram.size - 1,
170 .conf0 = NV50_DMA_CONF0_ENABLE | 0x70 |
171 NV50_DMA_CONF0_PART_256,
172 }, sizeof(struct nv_dma_class), &object);
176 ret = nouveau_object_new(client, parent, NvEvoFB32,
177 NV_DMA_IN_MEMORY_CLASS,
178 &(struct nv_dma_class) {
179 .flags = NV_DMA_TARGET_VRAM |
182 .limit = pfb->ram.size - 1,
183 .conf0 = NV50_DMA_CONF0_ENABLE | 0x7a |
184 NV50_DMA_CONF0_PART_256,
185 }, sizeof(struct nv_dma_class), &object);
190 nvc0_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
192 struct nouveau_fb *pfb = nouveau_fb(core);
193 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
194 struct nouveau_object *object;
195 int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
196 NV_DMA_IN_MEMORY_CLASS,
197 &(struct nv_dma_class) {
198 .flags = NV_DMA_TARGET_VRAM |
201 .limit = pfb->ram.size - 1,
202 .conf0 = NVC0_DMA_CONF0_ENABLE,
203 }, sizeof(struct nv_dma_class), &object);
207 ret = nouveau_object_new(client, parent, NvEvoFB16,
208 NV_DMA_IN_MEMORY_CLASS,
209 &(struct nv_dma_class) {
210 .flags = NV_DMA_TARGET_VRAM |
213 .limit = pfb->ram.size - 1,
214 .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe,
215 }, sizeof(struct nv_dma_class), &object);
219 ret = nouveau_object_new(client, parent, NvEvoFB32,
220 NV_DMA_IN_MEMORY_CLASS,
221 &(struct nv_dma_class) {
222 .flags = NV_DMA_TARGET_VRAM |
225 .limit = pfb->ram.size - 1,
226 .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe,
227 }, sizeof(struct nv_dma_class), &object);
232 nvd0_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
234 struct nouveau_fb *pfb = nouveau_fb(core);
235 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
236 struct nouveau_object *object;
237 int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
238 NV_DMA_IN_MEMORY_CLASS,
239 &(struct nv_dma_class) {
240 .flags = NV_DMA_TARGET_VRAM |
243 .limit = pfb->ram.size - 1,
244 .conf0 = NVD0_DMA_CONF0_ENABLE |
245 NVD0_DMA_CONF0_PAGE_LP,
246 }, sizeof(struct nv_dma_class), &object);
250 ret = nouveau_object_new(client, parent, NvEvoFB32,
251 NV_DMA_IN_MEMORY_CLASS,
252 &(struct nv_dma_class) {
253 .flags = NV_DMA_TARGET_VRAM |
256 .limit = pfb->ram.size - 1,
257 .conf0 = NVD0_DMA_CONF0_ENABLE | 0xfe |
258 NVD0_DMA_CONF0_PAGE_LP,
259 }, sizeof(struct nv_dma_class), &object);
264 nv50_dmac_create(struct nouveau_object *core, u32 bclass, u8 head,
265 void *data, u32 size, u64 syncbuf,
266 struct nv50_dmac *dmac)
268 struct nouveau_fb *pfb = nouveau_fb(core);
269 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
270 struct nouveau_object *object;
271 u32 pushbuf = *(u32 *)data;
274 dmac->ptr = pci_alloc_consistent(nv_device(core)->pdev, PAGE_SIZE,
279 ret = nouveau_object_new(client, NVDRM_DEVICE, pushbuf,
280 NV_DMA_FROM_MEMORY_CLASS,
281 &(struct nv_dma_class) {
282 .flags = NV_DMA_TARGET_PCI_US |
284 .start = dmac->handle + 0x0000,
285 .limit = dmac->handle + 0x0fff,
286 }, sizeof(struct nv_dma_class), &object);
290 ret = nv50_chan_create(core, bclass, head, data, size, &dmac->base);
294 ret = nouveau_object_new(client, dmac->base.handle, NvEvoSync,
295 NV_DMA_IN_MEMORY_CLASS,
296 &(struct nv_dma_class) {
297 .flags = NV_DMA_TARGET_VRAM |
299 .start = syncbuf + 0x0000,
300 .limit = syncbuf + 0x0fff,
301 }, sizeof(struct nv_dma_class), &object);
305 ret = nouveau_object_new(client, dmac->base.handle, NvEvoVRAM,
306 NV_DMA_IN_MEMORY_CLASS,
307 &(struct nv_dma_class) {
308 .flags = NV_DMA_TARGET_VRAM |
311 .limit = pfb->ram.size - 1,
312 }, sizeof(struct nv_dma_class), &object);
316 if (nv_device(core)->card_type < NV_C0)
317 ret = nv50_dmac_create_fbdma(core, dmac->base.handle);
319 if (nv_device(core)->card_type < NV_D0)
320 ret = nvc0_dmac_create_fbdma(core, dmac->base.handle);
322 ret = nvd0_dmac_create_fbdma(core, dmac->base.handle);
327 struct nv50_dmac base;
331 struct nv50_pioc base;
335 struct nv50_dmac base;
343 struct nv50_dmac base;
347 struct nv50_pioc base;
351 struct nouveau_crtc base;
352 struct nv50_curs curs;
353 struct nv50_sync sync;
354 struct nv50_ovly ovly;
355 struct nv50_oimm oimm;
358 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
359 #define nv50_curs(c) (&nv50_head(c)->curs)
360 #define nv50_sync(c) (&nv50_head(c)->sync)
361 #define nv50_ovly(c) (&nv50_head(c)->ovly)
362 #define nv50_oimm(c) (&nv50_head(c)->oimm)
363 #define nv50_chan(c) (&(c)->base.base)
364 #define nv50_vers(c) nv_mclass(nv50_chan(c)->user)
367 struct nouveau_object *core;
368 struct nv50_mast mast;
372 struct nouveau_bo *sync;
375 static struct nv50_disp *
376 nv50_disp(struct drm_device *dev)
378 return nouveau_display(dev)->priv;
381 #define nv50_mast(d) (&nv50_disp(d)->mast)
383 static struct drm_crtc *
384 nv50_display_crtc_get(struct drm_encoder *encoder)
386 return nouveau_encoder(encoder)->crtc;
389 /******************************************************************************
390 * EVO channel helpers
391 *****************************************************************************/
393 evo_wait(void *evoc, int nr)
395 struct nv50_dmac *dmac = evoc;
396 u32 put = nv_ro32(dmac->base.user, 0x0000) / 4;
398 if (put + nr >= (PAGE_SIZE / 4) - 8) {
399 dmac->ptr[put] = 0x20000000;
401 nv_wo32(dmac->base.user, 0x0000, 0x00000000);
402 if (!nv_wait(dmac->base.user, 0x0004, ~0, 0x00000000)) {
403 NV_ERROR(dmac->base.user, "channel stalled\n");
410 return dmac->ptr + put;
414 evo_kick(u32 *push, void *evoc)
416 struct nv50_dmac *dmac = evoc;
417 nv_wo32(dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
420 #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
421 #define evo_data(p,d) *((p)++) = (d)
424 evo_sync_wait(void *data)
426 return nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000;
430 evo_sync(struct drm_device *dev)
432 struct nouveau_device *device = nouveau_dev(dev);
433 struct nv50_disp *disp = nv50_disp(dev);
434 struct nv50_mast *mast = nv50_mast(dev);
435 u32 *push = evo_wait(mast, 8);
437 nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
438 evo_mthd(push, 0x0084, 1);
439 evo_data(push, 0x80000000 | EVO_MAST_NTFY);
440 evo_mthd(push, 0x0080, 2);
441 evo_data(push, 0x00000000);
442 evo_data(push, 0x00000000);
443 evo_kick(push, mast);
444 if (nv_wait_cb(device, evo_sync_wait, disp->sync))
451 /******************************************************************************
452 * Page flipping channel
453 *****************************************************************************/
455 nv50_display_crtc_sema(struct drm_device *dev, int crtc)
457 return nv50_disp(dev)->sync;
461 nv50_display_flip_stop(struct drm_crtc *crtc)
463 struct nv50_sync *sync = nv50_sync(crtc);
466 push = evo_wait(sync, 8);
468 evo_mthd(push, 0x0084, 1);
469 evo_data(push, 0x00000000);
470 evo_mthd(push, 0x0094, 1);
471 evo_data(push, 0x00000000);
472 evo_mthd(push, 0x00c0, 1);
473 evo_data(push, 0x00000000);
474 evo_mthd(push, 0x0080, 1);
475 evo_data(push, 0x00000000);
476 evo_kick(push, sync);
481 nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
482 struct nouveau_channel *chan, u32 swap_interval)
484 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
485 struct nv50_disp *disp = nv50_disp(crtc->dev);
486 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
487 struct nv50_sync *sync = nv50_sync(crtc);
492 if (swap_interval == 0)
493 swap_interval |= 0x100;
495 push = evo_wait(sync, 128);
496 if (unlikely(push == NULL))
499 /* synchronise with the rendering channel, if necessary */
501 ret = RING_SPACE(chan, 10);
505 if (nv_mclass(chan->object) < NVC0_CHANNEL_IND_CLASS) {
506 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
507 OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
508 OUT_RING (chan, sync->sem.offset);
509 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
510 OUT_RING (chan, 0xf00d0000 | sync->sem.value);
511 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
512 OUT_RING (chan, sync->sem.offset ^ 0x10);
513 OUT_RING (chan, 0x74b1e000);
514 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
515 if (nv_mclass(chan->object) < NV84_CHANNEL_DMA_CLASS)
516 OUT_RING (chan, NvSema);
518 OUT_RING (chan, chan->vram);
520 u64 offset = nvc0_fence_crtc(chan, nv_crtc->index);
521 offset += sync->sem.offset;
523 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
524 OUT_RING (chan, upper_32_bits(offset));
525 OUT_RING (chan, lower_32_bits(offset));
526 OUT_RING (chan, 0xf00d0000 | sync->sem.value);
527 OUT_RING (chan, 0x1002);
528 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
529 OUT_RING (chan, upper_32_bits(offset));
530 OUT_RING (chan, lower_32_bits(offset ^ 0x10));
531 OUT_RING (chan, 0x74b1e000);
532 OUT_RING (chan, 0x1001);
537 nouveau_bo_wr32(disp->sync, sync->sem.offset / 4,
538 0xf00d0000 | sync->sem.value);
543 evo_mthd(push, 0x0100, 1);
544 evo_data(push, 0xfffe0000);
545 evo_mthd(push, 0x0084, 1);
546 evo_data(push, swap_interval);
547 if (!(swap_interval & 0x00000100)) {
548 evo_mthd(push, 0x00e0, 1);
549 evo_data(push, 0x40000000);
551 evo_mthd(push, 0x0088, 4);
552 evo_data(push, sync->sem.offset);
553 evo_data(push, 0xf00d0000 | sync->sem.value);
554 evo_data(push, 0x74b1e000);
555 evo_data(push, NvEvoSync);
556 evo_mthd(push, 0x00a0, 2);
557 evo_data(push, 0x00000000);
558 evo_data(push, 0x00000000);
559 evo_mthd(push, 0x00c0, 1);
560 evo_data(push, nv_fb->r_dma);
561 evo_mthd(push, 0x0110, 2);
562 evo_data(push, 0x00000000);
563 evo_data(push, 0x00000000);
564 if (nv50_vers(sync) < NVD0_DISP_SYNC_CLASS) {
565 evo_mthd(push, 0x0800, 5);
566 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
568 evo_data(push, (fb->height << 16) | fb->width);
569 evo_data(push, nv_fb->r_pitch);
570 evo_data(push, nv_fb->r_format);
572 evo_mthd(push, 0x0400, 5);
573 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
575 evo_data(push, (fb->height << 16) | fb->width);
576 evo_data(push, nv_fb->r_pitch);
577 evo_data(push, nv_fb->r_format);
579 evo_mthd(push, 0x0080, 1);
580 evo_data(push, 0x00000000);
581 evo_kick(push, sync);
583 sync->sem.offset ^= 0x10;
588 /******************************************************************************
590 *****************************************************************************/
592 nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
594 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
595 struct nouveau_connector *nv_connector;
596 struct drm_connector *connector;
597 u32 *push, mode = 0x00;
599 nv_connector = nouveau_crtc_connector_get(nv_crtc);
600 connector = &nv_connector->base;
601 if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
602 if (nv_crtc->base.fb->depth > connector->display_info.bpc * 3)
603 mode = DITHERING_MODE_DYNAMIC2X2;
605 mode = nv_connector->dithering_mode;
608 if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
609 if (connector->display_info.bpc >= 8)
610 mode |= DITHERING_DEPTH_8BPC;
612 mode |= nv_connector->dithering_depth;
615 push = evo_wait(mast, 4);
617 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
618 evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1);
619 evo_data(push, mode);
621 if (nv50_vers(mast) < NVE0_DISP_MAST_CLASS) {
622 evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1);
623 evo_data(push, mode);
625 evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1);
626 evo_data(push, mode);
630 evo_mthd(push, 0x0080, 1);
631 evo_data(push, 0x00000000);
633 evo_kick(push, mast);
640 nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
642 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
643 struct drm_display_mode *omode, *umode = &nv_crtc->base.mode;
644 struct drm_crtc *crtc = &nv_crtc->base;
645 struct nouveau_connector *nv_connector;
646 int mode = DRM_MODE_SCALE_NONE;
649 /* start off at the resolution we programmed the crtc for, this
650 * effectively handles NONE/FULL scaling
652 nv_connector = nouveau_crtc_connector_get(nv_crtc);
653 if (nv_connector && nv_connector->native_mode)
654 mode = nv_connector->scaling_mode;
656 if (mode != DRM_MODE_SCALE_NONE)
657 omode = nv_connector->native_mode;
661 oX = omode->hdisplay;
662 oY = omode->vdisplay;
663 if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
666 /* add overscan compensation if necessary, will keep the aspect
667 * ratio the same as the backend mode unless overridden by the
668 * user setting both hborder and vborder properties.
670 if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
671 (nv_connector->underscan == UNDERSCAN_AUTO &&
672 nv_connector->edid &&
673 drm_detect_hdmi_monitor(nv_connector->edid)))) {
674 u32 bX = nv_connector->underscan_hborder;
675 u32 bY = nv_connector->underscan_vborder;
676 u32 aspect = (oY << 19) / oX;
680 if (bY) oY -= (bY * 2);
681 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
683 oX -= (oX >> 4) + 32;
684 if (bY) oY -= (bY * 2);
685 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
689 /* handle CENTER/ASPECT scaling, taking into account the areas
690 * removed already for overscan compensation
693 case DRM_MODE_SCALE_CENTER:
694 oX = min((u32)umode->hdisplay, oX);
695 oY = min((u32)umode->vdisplay, oY);
697 case DRM_MODE_SCALE_ASPECT:
699 u32 aspect = (umode->hdisplay << 19) / umode->vdisplay;
700 oX = ((oY * aspect) + (aspect / 2)) >> 19;
702 u32 aspect = (umode->vdisplay << 19) / umode->hdisplay;
703 oY = ((oX * aspect) + (aspect / 2)) >> 19;
710 push = evo_wait(mast, 8);
712 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
713 /*XXX: SCALE_CTRL_ACTIVE??? */
714 evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2);
715 evo_data(push, (oY << 16) | oX);
716 evo_data(push, (oY << 16) | oX);
717 evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1);
718 evo_data(push, 0x00000000);
719 evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1);
720 evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
722 evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
723 evo_data(push, (oY << 16) | oX);
724 evo_data(push, (oY << 16) | oX);
725 evo_data(push, (oY << 16) | oX);
726 evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
727 evo_data(push, 0x00000000);
728 evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
729 evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
732 evo_kick(push, mast);
735 nv50_display_flip_stop(crtc);
736 nv50_display_flip_next(crtc, crtc->fb, NULL, 1);
744 nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
746 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
750 adj = (nv_crtc->color_vibrance > 0) ? 50 : 0;
751 vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff;
752 hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff;
754 push = evo_wait(mast, 16);
756 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
757 evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1);
758 evo_data(push, (hue << 20) | (vib << 8));
760 evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1);
761 evo_data(push, (hue << 20) | (vib << 8));
765 evo_mthd(push, 0x0080, 1);
766 evo_data(push, 0x00000000);
768 evo_kick(push, mast);
775 nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
776 int x, int y, bool update)
778 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
779 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
782 push = evo_wait(mast, 16);
784 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
785 evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1);
786 evo_data(push, nvfb->nvbo->bo.offset >> 8);
787 evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3);
788 evo_data(push, (fb->height << 16) | fb->width);
789 evo_data(push, nvfb->r_pitch);
790 evo_data(push, nvfb->r_format);
791 evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1);
792 evo_data(push, (y << 16) | x);
793 if (nv50_vers(mast) > NV50_DISP_MAST_CLASS) {
794 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
795 evo_data(push, nvfb->r_dma);
798 evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
799 evo_data(push, nvfb->nvbo->bo.offset >> 8);
800 evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
801 evo_data(push, (fb->height << 16) | fb->width);
802 evo_data(push, nvfb->r_pitch);
803 evo_data(push, nvfb->r_format);
804 evo_data(push, nvfb->r_dma);
805 evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
806 evo_data(push, (y << 16) | x);
810 evo_mthd(push, 0x0080, 1);
811 evo_data(push, 0x00000000);
813 evo_kick(push, mast);
816 nv_crtc->fb.tile_flags = nvfb->r_dma;
821 nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc)
823 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
824 u32 *push = evo_wait(mast, 16);
826 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
827 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
828 evo_data(push, 0x85000000);
829 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
831 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
832 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
833 evo_data(push, 0x85000000);
834 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
835 evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
836 evo_data(push, NvEvoVRAM);
838 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
839 evo_data(push, 0x85000000);
840 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
841 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
842 evo_data(push, NvEvoVRAM);
844 evo_kick(push, mast);
849 nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc)
851 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
852 u32 *push = evo_wait(mast, 16);
854 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
855 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
856 evo_data(push, 0x05000000);
858 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
859 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
860 evo_data(push, 0x05000000);
861 evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
862 evo_data(push, 0x00000000);
864 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
865 evo_data(push, 0x05000000);
866 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
867 evo_data(push, 0x00000000);
869 evo_kick(push, mast);
874 nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update)
876 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
879 nv50_crtc_cursor_show(nv_crtc);
881 nv50_crtc_cursor_hide(nv_crtc);
884 u32 *push = evo_wait(mast, 2);
886 evo_mthd(push, 0x0080, 1);
887 evo_data(push, 0x00000000);
888 evo_kick(push, mast);
894 nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
899 nv50_crtc_prepare(struct drm_crtc *crtc)
901 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
902 struct nv50_mast *mast = nv50_mast(crtc->dev);
905 nv50_display_flip_stop(crtc);
907 push = evo_wait(mast, 2);
909 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
910 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
911 evo_data(push, 0x00000000);
912 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
913 evo_data(push, 0x40000000);
915 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
916 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
917 evo_data(push, 0x00000000);
918 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
919 evo_data(push, 0x40000000);
920 evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
921 evo_data(push, 0x00000000);
923 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
924 evo_data(push, 0x00000000);
925 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
926 evo_data(push, 0x03000000);
927 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
928 evo_data(push, 0x00000000);
931 evo_kick(push, mast);
934 nv50_crtc_cursor_show_hide(nv_crtc, false, false);
938 nv50_crtc_commit(struct drm_crtc *crtc)
940 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
941 struct nv50_mast *mast = nv50_mast(crtc->dev);
944 push = evo_wait(mast, 32);
946 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
947 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
948 evo_data(push, NvEvoVRAM_LP);
949 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
950 evo_data(push, 0xc0000000);
951 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
953 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
954 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
955 evo_data(push, nv_crtc->fb.tile_flags);
956 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
957 evo_data(push, 0xc0000000);
958 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
959 evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
960 evo_data(push, NvEvoVRAM);
962 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
963 evo_data(push, nv_crtc->fb.tile_flags);
964 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
965 evo_data(push, 0x83000000);
966 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
967 evo_data(push, 0x00000000);
968 evo_data(push, 0x00000000);
969 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
970 evo_data(push, NvEvoVRAM);
971 evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
972 evo_data(push, 0xffffff00);
975 evo_kick(push, mast);
978 nv50_crtc_cursor_show_hide(nv_crtc, nv_crtc->cursor.visible, true);
979 nv50_display_flip_next(crtc, crtc->fb, NULL, 1);
983 nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
984 struct drm_display_mode *adjusted_mode)
990 nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
992 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->fb);
995 ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM);
1000 nvfb = nouveau_framebuffer(old_fb);
1001 nouveau_bo_unpin(nvfb->nvbo);
1008 nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
1009 struct drm_display_mode *mode, int x, int y,
1010 struct drm_framebuffer *old_fb)
1012 struct nv50_mast *mast = nv50_mast(crtc->dev);
1013 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1014 struct nouveau_connector *nv_connector;
1015 u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
1016 u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
1017 u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
1018 u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
1019 u32 vblan2e = 0, vblan2s = 1;
1023 hactive = mode->htotal;
1024 hsynce = mode->hsync_end - mode->hsync_start - 1;
1025 hbackp = mode->htotal - mode->hsync_end;
1026 hblanke = hsynce + hbackp;
1027 hfrontp = mode->hsync_start - mode->hdisplay;
1028 hblanks = mode->htotal - hfrontp - 1;
1030 vactive = mode->vtotal * vscan / ilace;
1031 vsynce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
1032 vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace;
1033 vblanke = vsynce + vbackp;
1034 vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
1035 vblanks = vactive - vfrontp - 1;
1036 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1037 vblan2e = vactive + vsynce + vbackp;
1038 vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
1039 vactive = (vactive * 2) + 1;
1042 ret = nv50_crtc_swap_fbs(crtc, old_fb);
1046 push = evo_wait(mast, 64);
1048 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1049 evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2);
1050 evo_data(push, 0x00800000 | mode->clock);
1051 evo_data(push, (ilace == 2) ? 2 : 0);
1052 evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6);
1053 evo_data(push, 0x00000000);
1054 evo_data(push, (vactive << 16) | hactive);
1055 evo_data(push, ( vsynce << 16) | hsynce);
1056 evo_data(push, (vblanke << 16) | hblanke);
1057 evo_data(push, (vblanks << 16) | hblanks);
1058 evo_data(push, (vblan2e << 16) | vblan2s);
1059 evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1);
1060 evo_data(push, 0x00000000);
1061 evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2);
1062 evo_data(push, 0x00000311);
1063 evo_data(push, 0x00000100);
1065 evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6);
1066 evo_data(push, 0x00000000);
1067 evo_data(push, (vactive << 16) | hactive);
1068 evo_data(push, ( vsynce << 16) | hsynce);
1069 evo_data(push, (vblanke << 16) | hblanke);
1070 evo_data(push, (vblanks << 16) | hblanks);
1071 evo_data(push, (vblan2e << 16) | vblan2s);
1072 evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
1073 evo_data(push, 0x00000000); /* ??? */
1074 evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
1075 evo_data(push, mode->clock * 1000);
1076 evo_data(push, 0x00200000); /* ??? */
1077 evo_data(push, mode->clock * 1000);
1078 evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
1079 evo_data(push, 0x00000311);
1080 evo_data(push, 0x00000100);
1083 evo_kick(push, mast);
1086 nv_connector = nouveau_crtc_connector_get(nv_crtc);
1087 nv50_crtc_set_dither(nv_crtc, false);
1088 nv50_crtc_set_scale(nv_crtc, false);
1089 nv50_crtc_set_color_vibrance(nv_crtc, false);
1090 nv50_crtc_set_image(nv_crtc, crtc->fb, x, y, false);
1095 nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
1096 struct drm_framebuffer *old_fb)
1098 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
1099 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1103 NV_DEBUG(drm, "No FB bound\n");
1107 ret = nv50_crtc_swap_fbs(crtc, old_fb);
1111 nv50_display_flip_stop(crtc);
1112 nv50_crtc_set_image(nv_crtc, crtc->fb, x, y, true);
1113 nv50_display_flip_next(crtc, crtc->fb, NULL, 1);
1118 nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
1119 struct drm_framebuffer *fb, int x, int y,
1120 enum mode_set_atomic state)
1122 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1123 nv50_display_flip_stop(crtc);
1124 nv50_crtc_set_image(nv_crtc, fb, x, y, true);
1129 nv50_crtc_lut_load(struct drm_crtc *crtc)
1131 struct nv50_disp *disp = nv50_disp(crtc->dev);
1132 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1133 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
1136 for (i = 0; i < 256; i++) {
1137 u16 r = nv_crtc->lut.r[i] >> 2;
1138 u16 g = nv_crtc->lut.g[i] >> 2;
1139 u16 b = nv_crtc->lut.b[i] >> 2;
1141 if (nv_mclass(disp->core) < NVD0_DISP_CLASS) {
1142 writew(r + 0x0000, lut + (i * 0x08) + 0);
1143 writew(g + 0x0000, lut + (i * 0x08) + 2);
1144 writew(b + 0x0000, lut + (i * 0x08) + 4);
1146 writew(r + 0x6000, lut + (i * 0x20) + 0);
1147 writew(g + 0x6000, lut + (i * 0x20) + 2);
1148 writew(b + 0x6000, lut + (i * 0x20) + 4);
1154 nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
1155 uint32_t handle, uint32_t width, uint32_t height)
1157 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1158 struct drm_device *dev = crtc->dev;
1159 struct drm_gem_object *gem;
1160 struct nouveau_bo *nvbo;
1161 bool visible = (handle != 0);
1165 if (width != 64 || height != 64)
1168 gem = drm_gem_object_lookup(dev, file_priv, handle);
1171 nvbo = nouveau_gem_object(gem);
1173 ret = nouveau_bo_map(nvbo);
1175 for (i = 0; i < 64 * 64; i++) {
1176 u32 v = nouveau_bo_rd32(nvbo, i);
1177 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v);
1179 nouveau_bo_unmap(nvbo);
1182 drm_gem_object_unreference_unlocked(gem);
1185 if (visible != nv_crtc->cursor.visible) {
1186 nv50_crtc_cursor_show_hide(nv_crtc, visible, true);
1187 nv_crtc->cursor.visible = visible;
1194 nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1196 struct nv50_curs *curs = nv50_curs(crtc);
1197 struct nv50_chan *chan = nv50_chan(curs);
1198 nv_wo32(chan->user, 0x0084, (y << 16) | (x & 0xffff));
1199 nv_wo32(chan->user, 0x0080, 0x00000000);
1204 nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
1205 uint32_t start, uint32_t size)
1207 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1208 u32 end = max(start + size, (u32)256);
1211 for (i = start; i < end; i++) {
1212 nv_crtc->lut.r[i] = r[i];
1213 nv_crtc->lut.g[i] = g[i];
1214 nv_crtc->lut.b[i] = b[i];
1217 nv50_crtc_lut_load(crtc);
1221 nv50_crtc_destroy(struct drm_crtc *crtc)
1223 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1224 struct nv50_disp *disp = nv50_disp(crtc->dev);
1225 struct nv50_head *head = nv50_head(crtc);
1226 nv50_dmac_destroy(disp->core, &head->ovly.base);
1227 nv50_pioc_destroy(disp->core, &head->oimm.base);
1228 nv50_dmac_destroy(disp->core, &head->sync.base);
1229 nv50_pioc_destroy(disp->core, &head->curs.base);
1230 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
1231 if (nv_crtc->cursor.nvbo)
1232 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1233 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
1234 nouveau_bo_unmap(nv_crtc->lut.nvbo);
1235 if (nv_crtc->lut.nvbo)
1236 nouveau_bo_unpin(nv_crtc->lut.nvbo);
1237 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
1238 drm_crtc_cleanup(crtc);
1242 static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = {
1243 .dpms = nv50_crtc_dpms,
1244 .prepare = nv50_crtc_prepare,
1245 .commit = nv50_crtc_commit,
1246 .mode_fixup = nv50_crtc_mode_fixup,
1247 .mode_set = nv50_crtc_mode_set,
1248 .mode_set_base = nv50_crtc_mode_set_base,
1249 .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
1250 .load_lut = nv50_crtc_lut_load,
1253 static const struct drm_crtc_funcs nv50_crtc_func = {
1254 .cursor_set = nv50_crtc_cursor_set,
1255 .cursor_move = nv50_crtc_cursor_move,
1256 .gamma_set = nv50_crtc_gamma_set,
1257 .set_config = drm_crtc_helper_set_config,
1258 .destroy = nv50_crtc_destroy,
1259 .page_flip = nouveau_crtc_page_flip,
1263 nv50_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
1268 nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
1273 nv50_crtc_create(struct drm_device *dev, struct nouveau_object *core, int index)
1275 struct nv50_disp *disp = nv50_disp(dev);
1276 struct nv50_head *head;
1277 struct drm_crtc *crtc;
1280 head = kzalloc(sizeof(*head), GFP_KERNEL);
1284 head->base.index = index;
1285 head->base.set_dither = nv50_crtc_set_dither;
1286 head->base.set_scale = nv50_crtc_set_scale;
1287 head->base.set_color_vibrance = nv50_crtc_set_color_vibrance;
1288 head->base.color_vibrance = 50;
1289 head->base.vibrant_hue = 0;
1290 head->base.cursor.set_offset = nv50_cursor_set_offset;
1291 head->base.cursor.set_pos = nv50_cursor_set_pos;
1292 for (i = 0; i < 256; i++) {
1293 head->base.lut.r[i] = i << 8;
1294 head->base.lut.g[i] = i << 8;
1295 head->base.lut.b[i] = i << 8;
1298 crtc = &head->base.base;
1299 drm_crtc_init(dev, crtc, &nv50_crtc_func);
1300 drm_crtc_helper_add(crtc, &nv50_crtc_hfunc);
1301 drm_mode_crtc_set_gamma_size(crtc, 256);
1303 ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
1304 0, 0x0000, NULL, &head->base.lut.nvbo);
1306 ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM);
1308 ret = nouveau_bo_map(head->base.lut.nvbo);
1310 nouveau_bo_unpin(head->base.lut.nvbo);
1313 nouveau_bo_ref(NULL, &head->base.lut.nvbo);
1319 nv50_crtc_lut_load(crtc);
1321 /* allocate cursor resources */
1322 ret = nv50_pioc_create(disp->core, NV50_DISP_CURS_CLASS, index,
1323 &(struct nv50_display_curs_class) {
1325 }, sizeof(struct nv50_display_curs_class),
1330 ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM,
1331 0, 0x0000, NULL, &head->base.cursor.nvbo);
1333 ret = nouveau_bo_pin(head->base.cursor.nvbo, TTM_PL_FLAG_VRAM);
1335 ret = nouveau_bo_map(head->base.cursor.nvbo);
1337 nouveau_bo_unpin(head->base.lut.nvbo);
1340 nouveau_bo_ref(NULL, &head->base.cursor.nvbo);
1346 /* allocate page flip / sync resources */
1347 ret = nv50_dmac_create(disp->core, NV50_DISP_SYNC_CLASS, index,
1348 &(struct nv50_display_sync_class) {
1349 .pushbuf = EVO_PUSH_HANDLE(SYNC, index),
1351 }, sizeof(struct nv50_display_sync_class),
1352 disp->sync->bo.offset, &head->sync.base);
1356 head->sync.sem.offset = EVO_SYNC(1 + index, 0x00);
1358 /* allocate overlay resources */
1359 ret = nv50_pioc_create(disp->core, NV50_DISP_OIMM_CLASS, index,
1360 &(struct nv50_display_oimm_class) {
1362 }, sizeof(struct nv50_display_oimm_class),
1367 ret = nv50_dmac_create(disp->core, NV50_DISP_OVLY_CLASS, index,
1368 &(struct nv50_display_ovly_class) {
1369 .pushbuf = EVO_PUSH_HANDLE(OVLY, index),
1371 }, sizeof(struct nv50_display_ovly_class),
1372 disp->sync->bo.offset, &head->ovly.base);
1378 nv50_crtc_destroy(crtc);
1382 /******************************************************************************
1384 *****************************************************************************/
1386 nv50_dac_dpms(struct drm_encoder *encoder, int mode)
1388 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1389 struct nv50_disp *disp = nv50_disp(encoder->dev);
1390 int or = nv_encoder->or;
1393 dpms_ctrl = 0x00000000;
1394 if (mode == DRM_MODE_DPMS_STANDBY || mode == DRM_MODE_DPMS_OFF)
1395 dpms_ctrl |= 0x00000001;
1396 if (mode == DRM_MODE_DPMS_SUSPEND || mode == DRM_MODE_DPMS_OFF)
1397 dpms_ctrl |= 0x00000004;
1399 nv_call(disp->core, NV50_DISP_DAC_PWR + or, dpms_ctrl);
1403 nv50_dac_mode_fixup(struct drm_encoder *encoder,
1404 const struct drm_display_mode *mode,
1405 struct drm_display_mode *adjusted_mode)
1407 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1408 struct nouveau_connector *nv_connector;
1410 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1411 if (nv_connector && nv_connector->native_mode) {
1412 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1413 int id = adjusted_mode->base.id;
1414 *adjusted_mode = *nv_connector->native_mode;
1415 adjusted_mode->base.id = id;
1423 nv50_dac_commit(struct drm_encoder *encoder)
1428 nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1429 struct drm_display_mode *adjusted_mode)
1431 struct nv50_mast *mast = nv50_mast(encoder->dev);
1432 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1433 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1436 nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1438 push = evo_wait(mast, 8);
1440 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1441 u32 syncs = 0x00000000;
1443 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1444 syncs |= 0x00000001;
1445 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1446 syncs |= 0x00000002;
1448 evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
1449 evo_data(push, 1 << nv_crtc->index);
1450 evo_data(push, syncs);
1452 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1453 u32 syncs = 0x00000001;
1455 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1456 syncs |= 0x00000008;
1457 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1458 syncs |= 0x00000010;
1460 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1461 magic |= 0x00000001;
1463 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1464 evo_data(push, syncs);
1465 evo_data(push, magic);
1466 evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
1467 evo_data(push, 1 << nv_crtc->index);
1470 evo_kick(push, mast);
1473 nv_encoder->crtc = encoder->crtc;
1477 nv50_dac_disconnect(struct drm_encoder *encoder)
1479 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1480 struct nv50_mast *mast = nv50_mast(encoder->dev);
1481 const int or = nv_encoder->or;
1484 if (nv_encoder->crtc) {
1485 nv50_crtc_prepare(nv_encoder->crtc);
1487 push = evo_wait(mast, 4);
1489 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1490 evo_mthd(push, 0x0400 + (or * 0x080), 1);
1491 evo_data(push, 0x00000000);
1493 evo_mthd(push, 0x0180 + (or * 0x020), 1);
1494 evo_data(push, 0x00000000);
1497 evo_mthd(push, 0x0080, 1);
1498 evo_data(push, 0x00000000);
1499 evo_kick(push, mast);
1503 nv_encoder->crtc = NULL;
1506 static enum drm_connector_status
1507 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1509 struct nv50_disp *disp = nv50_disp(encoder->dev);
1510 int ret, or = nouveau_encoder(encoder)->or;
1513 ret = nv_exec(disp->core, NV50_DISP_DAC_LOAD + or, &load, sizeof(load));
1514 if (ret || load != 7)
1515 return connector_status_disconnected;
1517 return connector_status_connected;
1521 nv50_dac_destroy(struct drm_encoder *encoder)
1523 drm_encoder_cleanup(encoder);
1527 static const struct drm_encoder_helper_funcs nv50_dac_hfunc = {
1528 .dpms = nv50_dac_dpms,
1529 .mode_fixup = nv50_dac_mode_fixup,
1530 .prepare = nv50_dac_disconnect,
1531 .commit = nv50_dac_commit,
1532 .mode_set = nv50_dac_mode_set,
1533 .disable = nv50_dac_disconnect,
1534 .get_crtc = nv50_display_crtc_get,
1535 .detect = nv50_dac_detect
1538 static const struct drm_encoder_funcs nv50_dac_func = {
1539 .destroy = nv50_dac_destroy,
1543 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
1545 struct drm_device *dev = connector->dev;
1546 struct nouveau_encoder *nv_encoder;
1547 struct drm_encoder *encoder;
1549 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1552 nv_encoder->dcb = dcbe;
1553 nv_encoder->or = ffs(dcbe->or) - 1;
1555 encoder = to_drm_encoder(nv_encoder);
1556 encoder->possible_crtcs = dcbe->heads;
1557 encoder->possible_clones = 0;
1558 drm_encoder_init(dev, encoder, &nv50_dac_func, DRM_MODE_ENCODER_DAC);
1559 drm_encoder_helper_add(encoder, &nv50_dac_hfunc);
1561 drm_mode_connector_attach_encoder(connector, encoder);
1565 /******************************************************************************
1567 *****************************************************************************/
1569 nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1571 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1572 struct nouveau_connector *nv_connector;
1573 struct nv50_disp *disp = nv50_disp(encoder->dev);
1575 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1576 if (!drm_detect_monitor_audio(nv_connector->edid))
1579 drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
1581 nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or,
1582 nv_connector->base.eld,
1583 nv_connector->base.eld[2] * 4);
1587 nv50_audio_disconnect(struct drm_encoder *encoder)
1589 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1590 struct nv50_disp *disp = nv50_disp(encoder->dev);
1592 nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or, NULL, 0);
1595 /******************************************************************************
1597 *****************************************************************************/
1599 nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1601 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1602 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1603 struct nouveau_connector *nv_connector;
1604 struct nv50_disp *disp = nv50_disp(encoder->dev);
1605 const u32 moff = (nv_crtc->index << 3) | nv_encoder->or;
1606 u32 rekey = 56; /* binary driver, and tegra constant */
1609 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1610 if (!drm_detect_hdmi_monitor(nv_connector->edid))
1613 max_ac_packet = mode->htotal - mode->hdisplay;
1614 max_ac_packet -= rekey;
1615 max_ac_packet -= 18; /* constant from tegra */
1616 max_ac_packet /= 32;
1618 nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff,
1619 NV84_DISP_SOR_HDMI_PWR_STATE_ON |
1620 (max_ac_packet << 16) | rekey);
1622 nv50_audio_mode_set(encoder, mode);
1626 nv50_hdmi_disconnect(struct drm_encoder *encoder)
1628 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1629 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1630 struct nv50_disp *disp = nv50_disp(encoder->dev);
1631 const u32 moff = (nv_crtc->index << 3) | nv_encoder->or;
1633 nv50_audio_disconnect(encoder);
1635 nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff, 0x00000000);
1638 /******************************************************************************
1640 *****************************************************************************/
1642 nv50_sor_dpms(struct drm_encoder *encoder, int mode)
1644 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1645 struct drm_device *dev = encoder->dev;
1646 struct nv50_disp *disp = nv50_disp(dev);
1647 struct drm_encoder *partner;
1648 int or = nv_encoder->or;
1650 nv_encoder->last_dpms = mode;
1652 list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
1653 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
1655 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
1658 if (nv_partner != nv_encoder &&
1659 nv_partner->dcb->or == nv_encoder->dcb->or) {
1660 if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
1666 nv_call(disp->core, NV50_DISP_SOR_PWR + or, (mode == DRM_MODE_DPMS_ON));
1668 if (nv_encoder->dcb->type == DCB_OUTPUT_DP)
1669 nouveau_dp_dpms(encoder, mode, nv_encoder->dp.datarate, disp->core);
1673 nv50_sor_mode_fixup(struct drm_encoder *encoder,
1674 const struct drm_display_mode *mode,
1675 struct drm_display_mode *adjusted_mode)
1677 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1678 struct nouveau_connector *nv_connector;
1680 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1681 if (nv_connector && nv_connector->native_mode) {
1682 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1683 int id = adjusted_mode->base.id;
1684 *adjusted_mode = *nv_connector->native_mode;
1685 adjusted_mode->base.id = id;
1693 nv50_sor_disconnect(struct drm_encoder *encoder)
1695 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1696 struct nv50_mast *mast = nv50_mast(encoder->dev);
1697 const int or = nv_encoder->or;
1700 if (nv_encoder->crtc) {
1701 nv50_crtc_prepare(nv_encoder->crtc);
1703 push = evo_wait(mast, 4);
1705 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1706 evo_mthd(push, 0x0600 + (or * 0x40), 1);
1707 evo_data(push, 0x00000000);
1709 evo_mthd(push, 0x0200 + (or * 0x20), 1);
1710 evo_data(push, 0x00000000);
1713 evo_mthd(push, 0x0080, 1);
1714 evo_data(push, 0x00000000);
1715 evo_kick(push, mast);
1718 nv50_hdmi_disconnect(encoder);
1721 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1722 nv_encoder->crtc = NULL;
1726 nv50_sor_prepare(struct drm_encoder *encoder)
1728 nv50_sor_disconnect(encoder);
1729 if (nouveau_encoder(encoder)->dcb->type == DCB_OUTPUT_DP)
1730 evo_sync(encoder->dev);
1734 nv50_sor_commit(struct drm_encoder *encoder)
1739 nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1740 struct drm_display_mode *mode)
1742 struct nv50_disp *disp = nv50_disp(encoder->dev);
1743 struct nv50_mast *mast = nv50_mast(encoder->dev);
1744 struct drm_device *dev = encoder->dev;
1745 struct nouveau_drm *drm = nouveau_drm(dev);
1746 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1747 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1748 struct nouveau_connector *nv_connector;
1749 struct nvbios *bios = &drm->vbios;
1750 u32 *push, lvds = 0;
1751 u8 owner = 1 << nv_crtc->index;
1755 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1756 switch (nv_encoder->dcb->type) {
1757 case DCB_OUTPUT_TMDS:
1758 if (nv_encoder->dcb->sorconf.link & 1) {
1759 if (mode->clock < 165000)
1767 nv50_hdmi_mode_set(encoder, mode);
1769 case DCB_OUTPUT_LVDS:
1772 if (bios->fp_no_ddc) {
1773 if (bios->fp.dual_link)
1775 if (bios->fp.if_is_24bit)
1778 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1779 if (((u8 *)nv_connector->edid)[121] == 2)
1782 if (mode->clock >= bios->fp.duallink_transition_clk) {
1786 if (lvds & 0x0100) {
1787 if (bios->fp.strapless_is_24bit & 2)
1790 if (bios->fp.strapless_is_24bit & 1)
1794 if (nv_connector->base.display_info.bpc == 8)
1798 nv_call(disp->core, NV50_DISP_SOR_LVDS_SCRIPT + nv_encoder->or, lvds);
1801 if (nv_connector->base.display_info.bpc == 6) {
1802 nv_encoder->dp.datarate = mode->clock * 18 / 8;
1805 if (nv_connector->base.display_info.bpc == 8) {
1806 nv_encoder->dp.datarate = mode->clock * 24 / 8;
1809 nv_encoder->dp.datarate = mode->clock * 30 / 8;
1813 if (nv_encoder->dcb->sorconf.link & 1)
1823 nv50_sor_dpms(encoder, DRM_MODE_DPMS_ON);
1825 push = evo_wait(nv50_mast(dev), 8);
1827 if (nv50_vers(mast) < NVD0_DISP_CLASS) {
1828 evo_mthd(push, 0x0600 + (nv_encoder->or * 0x040), 1);
1829 evo_data(push, (depth << 16) | (proto << 8) | owner);
1831 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1832 u32 syncs = 0x00000001;
1834 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1835 syncs |= 0x00000008;
1836 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1837 syncs |= 0x00000010;
1839 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1840 magic |= 0x00000001;
1842 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1843 evo_data(push, syncs | (depth << 6));
1844 evo_data(push, magic);
1845 evo_mthd(push, 0x0200 + (nv_encoder->or * 0x020), 1);
1846 evo_data(push, owner | (proto << 8));
1849 evo_kick(push, mast);
1852 nv_encoder->crtc = encoder->crtc;
1856 nv50_sor_destroy(struct drm_encoder *encoder)
1858 drm_encoder_cleanup(encoder);
1862 static const struct drm_encoder_helper_funcs nv50_sor_hfunc = {
1863 .dpms = nv50_sor_dpms,
1864 .mode_fixup = nv50_sor_mode_fixup,
1865 .prepare = nv50_sor_prepare,
1866 .commit = nv50_sor_commit,
1867 .mode_set = nv50_sor_mode_set,
1868 .disable = nv50_sor_disconnect,
1869 .get_crtc = nv50_display_crtc_get,
1872 static const struct drm_encoder_funcs nv50_sor_func = {
1873 .destroy = nv50_sor_destroy,
1877 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1879 struct drm_device *dev = connector->dev;
1880 struct nouveau_encoder *nv_encoder;
1881 struct drm_encoder *encoder;
1883 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1886 nv_encoder->dcb = dcbe;
1887 nv_encoder->or = ffs(dcbe->or) - 1;
1888 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1890 encoder = to_drm_encoder(nv_encoder);
1891 encoder->possible_crtcs = dcbe->heads;
1892 encoder->possible_clones = 0;
1893 drm_encoder_init(dev, encoder, &nv50_sor_func, DRM_MODE_ENCODER_TMDS);
1894 drm_encoder_helper_add(encoder, &nv50_sor_hfunc);
1896 drm_mode_connector_attach_encoder(connector, encoder);
1900 /******************************************************************************
1902 *****************************************************************************/
1904 nv50_display_fini(struct drm_device *dev)
1909 nv50_display_init(struct drm_device *dev)
1911 u32 *push = evo_wait(nv50_mast(dev), 32);
1913 evo_mthd(push, 0x0088, 1);
1914 evo_data(push, NvEvoSync);
1915 evo_kick(push, nv50_mast(dev));
1916 return evo_sync(dev);
1923 nv50_display_destroy(struct drm_device *dev)
1925 struct nv50_disp *disp = nv50_disp(dev);
1927 nv50_dmac_destroy(disp->core, &disp->mast.base);
1929 nouveau_bo_unmap(disp->sync);
1931 nouveau_bo_unpin(disp->sync);
1932 nouveau_bo_ref(NULL, &disp->sync);
1934 nouveau_display(dev)->priv = NULL;
1939 nv50_display_create(struct drm_device *dev)
1941 static const u16 oclass[] = {
1950 struct nouveau_device *device = nouveau_dev(dev);
1951 struct nouveau_drm *drm = nouveau_drm(dev);
1952 struct dcb_table *dcb = &drm->vbios.dcb;
1953 struct drm_connector *connector, *tmp;
1954 struct nv50_disp *disp;
1955 struct dcb_output *dcbe;
1958 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
1962 nouveau_display(dev)->priv = disp;
1963 nouveau_display(dev)->dtor = nv50_display_destroy;
1964 nouveau_display(dev)->init = nv50_display_init;
1965 nouveau_display(dev)->fini = nv50_display_fini;
1967 /* small shared memory area we use for notifiers and semaphores */
1968 ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
1969 0, 0x0000, NULL, &disp->sync);
1971 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM);
1973 ret = nouveau_bo_map(disp->sync);
1975 nouveau_bo_unpin(disp->sync);
1978 nouveau_bo_ref(NULL, &disp->sync);
1984 /* attempt to allocate a supported evo display class */
1986 for (i = 0; ret && i < ARRAY_SIZE(oclass); i++) {
1987 ret = nouveau_object_new(nv_object(drm), NVDRM_DEVICE,
1988 0xd1500000, oclass[i], NULL, 0,
1995 /* allocate master evo channel */
1996 ret = nv50_dmac_create(disp->core, NV50_DISP_MAST_CLASS, 0,
1997 &(struct nv50_display_mast_class) {
1998 .pushbuf = EVO_PUSH_HANDLE(MAST, 0),
1999 }, sizeof(struct nv50_display_mast_class),
2000 disp->sync->bo.offset, &disp->mast.base);
2004 /* create crtc objects to represent the hw heads */
2005 if (nv_mclass(disp->core) >= NVD0_DISP_CLASS)
2006 crtcs = nv_rd32(device, 0x022448);
2010 for (i = 0; i < crtcs; i++) {
2011 ret = nv50_crtc_create(dev, disp->core, i);
2016 /* create encoder/connector objects based on VBIOS DCB table */
2017 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2018 connector = nouveau_connector_create(dev, dcbe->connector);
2019 if (IS_ERR(connector))
2022 if (dcbe->location != DCB_LOC_ON_CHIP) {
2023 NV_WARN(drm, "skipping off-chip encoder %d/%d\n",
2024 dcbe->type, ffs(dcbe->or) - 1);
2028 switch (dcbe->type) {
2029 case DCB_OUTPUT_TMDS:
2030 case DCB_OUTPUT_LVDS:
2032 nv50_sor_create(connector, dcbe);
2034 case DCB_OUTPUT_ANALOG:
2035 nv50_dac_create(connector, dcbe);
2038 NV_WARN(drm, "skipping unsupported encoder %d/%d\n",
2039 dcbe->type, ffs(dcbe->or) - 1);
2044 /* cull any connectors we created that don't have an encoder */
2045 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2046 if (connector->encoder_ids[0])
2049 NV_WARN(drm, "%s has no encoders, removing\n",
2050 drm_get_connector_name(connector));
2051 connector->funcs->destroy(connector);
2056 nv50_display_destroy(dev);