drivers/gpu/drm/nouveau/nv50_display.c

   1 /*
   2  * Copyright (C) 2008 Maarten Maathuis.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "nv50_display.h"
  28 #include "nouveau_crtc.h"
  29 #include "nouveau_encoder.h"
  30 #include "nouveau_connector.h"
  31 #include "nouveau_fb.h"
  32 #include "nouveau_fbcon.h"
  33 #include "drm_crtc_helper.h"
  34
  35 static void
  36 nv50_evo_channel_del(struct nouveau_channel **pchan)
  37 {
  38         struct nouveau_channel *chan = *pchan;
  39
  40         if (!chan)
  41                 return;
  42         *pchan = NULL;
  43
  44         nouveau_gpuobj_channel_takedown(chan);
  45         nouveau_bo_ref(NULL, &chan->pushbuf_bo);
  46
  47         if (chan->user)
  48                 iounmap(chan->user);
  49
  50         kfree(chan);
  51 }
  52
  53 static int
  54 nv50_evo_dmaobj_new(struct nouveau_channel *evo, uint32_t class, uint32_t name,
  55                     uint32_t tile_flags, uint32_t magic_flags,
  56                     uint32_t offset, uint32_t limit)
  57 {
  58         struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
  59         struct drm_device *dev = evo->dev;
  60         struct nouveau_gpuobj *obj = NULL;
  61         int ret;
  62
  63         ret = nouveau_gpuobj_new(dev, evo, 6*4, 32, 0, &obj);
  64         if (ret)
  65                 return ret;
  66         obj->engine = NVOBJ_ENGINE_DISPLAY;
  67
  68         ret = nouveau_gpuobj_ref_add(dev, evo, name, obj, NULL);
  69         if (ret) {
  70                 nouveau_gpuobj_del(dev, &obj);
  71                 return ret;
  72         }
  73
  74         nv_wo32(dev, obj, 0, (tile_flags << 22) | (magic_flags << 16) | class);
  75         nv_wo32(dev, obj, 1, limit);
  76         nv_wo32(dev, obj, 2, offset);
  77         nv_wo32(dev, obj, 3, 0x00000000);
  78         nv_wo32(dev, obj, 4, 0x00000000);
  79         if (dev_priv->card_type < NV_C0)
  80                 nv_wo32(dev, obj, 5, 0x00010000);
  81         else
  82                 nv_wo32(dev, obj, 5, 0x00020000);
  83         dev_priv->engine.instmem.flush(dev);
  84
  85         return 0;
  86 }
  87
  88 static int
  89 nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pchan)
  90 {
  91         struct drm_nouveau_private *dev_priv = dev->dev_private;
  92         struct nouveau_channel *chan;
  93         int ret;
  94
  95         chan = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
  96         if (!chan)
  97                 return -ENOMEM;
  98         *pchan = chan;
  99
 100         chan->id = -1;
 101         chan->dev = dev;
 102         chan->user_get = 4;
 103         chan->user_put = 0;
 104
 105         INIT_LIST_HEAD(&chan->ramht_refs);
 106
 107         ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 32768, 0x1000,
 108                                      NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
 109         if (ret) {
 110                 NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
 111                 nv50_evo_channel_del(pchan);
 112                 return ret;
 113         }
 114
 115         ret = drm_mm_init(&chan->ramin_heap,
 116                           chan->ramin->gpuobj->im_pramin->start, 32768);
 117         if (ret) {
 118                 NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
 119                 nv50_evo_channel_del(pchan);
 120                 return ret;
 121         }
 122
 123         ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 4096, 16,
 124                                      0, &chan->ramht);
 125         if (ret) {
 126                 NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
 127                 nv50_evo_channel_del(pchan);
 128                 return ret;
 129         }
 130
 131         if (dev_priv->chipset != 0x50) {
 132                 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB16, 0x70, 0x19,
 133                                           0, 0xffffffff);
 134                 if (ret) {
 135                         nv50_evo_channel_del(pchan);
 136                         return ret;
 137                 }
 138
 139
 140                 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB32, 0x7a, 0x19,
 141                                           0, 0xffffffff);
 142                 if (ret) {
 143                         nv50_evo_channel_del(pchan);
 144                         return ret;
 145                 }
 146         }
 147
 148         ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoVRAM, 0, 0x19,
 149                                   0, dev_priv->vram_size);
 150         if (ret) {
 151                 nv50_evo_channel_del(pchan);
 152                 return ret;
 153         }
 154
 155         ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0,
 156                              false, true, &chan->pushbuf_bo);
 157         if (ret == 0)
 158                 ret = nouveau_bo_pin(chan->pushbuf_bo, TTM_PL_FLAG_VRAM);
 159         if (ret) {
 160                 NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
 161                 nv50_evo_channel_del(pchan);
 162                 return ret;
 163         }
 164
 165         ret = nouveau_bo_map(chan->pushbuf_bo);
 166         if (ret) {
 167                 NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
 168                 nv50_evo_channel_del(pchan);
 169                 return ret;
 170         }
 171
 172         chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
 173                                         NV50_PDISPLAY_USER(0), PAGE_SIZE);
 174         if (!chan->user) {
 175                 NV_ERROR(dev, "Error mapping EVO control regs.\n");
 176                 nv50_evo_channel_del(pchan);
 177                 return -ENOMEM;
 178         }
 179
 180         return 0;
 181 }
 182
 183 int
 184 nv50_display_early_init(struct drm_device *dev)
 185 {
 186         return 0;
 187 }
 188
 189 void
 190 nv50_display_late_takedown(struct drm_device *dev)
 191 {
 192 }
 193
 194 int
 195 nv50_display_init(struct drm_device *dev)
 196 {
 197         struct drm_nouveau_private *dev_priv = dev->dev_private;
 198         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
 199         struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
 200         struct nouveau_channel *evo = dev_priv->evo;
 201         struct drm_connector *connector;
 202         uint32_t val, ram_amount;
 203         uint64_t start;
 204         int ret, i;
 205
 206         NV_DEBUG_KMS(dev, "\n");
 207
 208         nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
 209         /*
 210          * I think the 0x006101XX range is some kind of main control area
 211          * that enables things.
 212          */
 213         /* CRTC? */
 214         for (i = 0; i < 2; i++) {
 215                 val = nv_rd32(dev, 0x00616100 + (i * 0x800));
 216                 nv_wr32(dev, 0x00610190 + (i * 0x10), val);
 217                 val = nv_rd32(dev, 0x00616104 + (i * 0x800));
 218                 nv_wr32(dev, 0x00610194 + (i * 0x10), val);
 219                 val = nv_rd32(dev, 0x00616108 + (i * 0x800));
 220                 nv_wr32(dev, 0x00610198 + (i * 0x10), val);
 221                 val = nv_rd32(dev, 0x0061610c + (i * 0x800));
 222                 nv_wr32(dev, 0x0061019c + (i * 0x10), val);
 223         }
 224         /* DAC */
 225         for (i = 0; i < 3; i++) {
 226                 val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
 227                 nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
 228         }
 229         /* SOR */
 230         for (i = 0; i < 4; i++) {
 231                 val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
 232                 nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
 233         }
 234         /* Something not yet in use, tv-out maybe. */
 235         for (i = 0; i < 3; i++) {
 236                 val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
 237                 nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
 238         }
 239
 240         for (i = 0; i < 3; i++) {
 241                 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
 242                         NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
 243                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
 244         }
 245
 246         /* This used to be in crtc unblank, but seems out of place there. */
 247         nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0);
 248         /* RAM is clamped to 256 MiB. */
 249         ram_amount = dev_priv->vram_size;
 250         NV_DEBUG_KMS(dev, "ram_amount %d\n", ram_amount);
 251         if (ram_amount > 256*1024*1024)
 252                 ram_amount = 256*1024*1024;
 253         nv_wr32(dev, NV50_PDISPLAY_RAM_AMOUNT, ram_amount - 1);
 254         nv_wr32(dev, NV50_PDISPLAY_UNK_388, 0x150000);
 255         nv_wr32(dev, NV50_PDISPLAY_UNK_38C, 0);
 256
 257         /* The precise purpose is unknown, i suspect it has something to do
 258          * with text mode.
 259          */
 260         if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) {
 261                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100);
 262                 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1);
 263                 if (!nv_wait(0x006194e8, 2, 0)) {
 264                         NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n");
 265                         NV_ERROR(dev, "0x6194e8 = 0x%08x\n",
 266                                                 nv_rd32(dev, 0x6194e8));
 267                         return -EBUSY;
 268                 }
 269         }
 270
 271         /* taken from nv bug #12637, attempts to un-wedge the hw if it's
 272          * stuck in some unspecified state
 273          */
 274         start = ptimer->read(dev);
 275         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x2b00);
 276         while ((val = nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0))) & 0x1e0000) {
 277                 if ((val & 0x9f0000) == 0x20000)
 278                         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
 279                                                         val | 0x800000);
 280
 281                 if ((val & 0x3f0000) == 0x30000)
 282                         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
 283                                                         val | 0x200000);
 284
 285                 if (ptimer->read(dev) - start > 1000000000ULL) {
 286                         NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) != 0\n");
 287                         NV_ERROR(dev, "0x610200 = 0x%08x\n", val);
 288                         return -EBUSY;
 289                 }
 290         }
 291
 292         nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_ENABLE);
 293         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1000b03);
 294         if (!nv_wait(NV50_PDISPLAY_CHANNEL_STAT(0), 0x40000000, 0x40000000)) {
 295                 NV_ERROR(dev, "timeout: (0x610200 & 0x40000000) == 0x40000000\n");
 296                 NV_ERROR(dev, "0x610200 = 0x%08x\n",
 297                           nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
 298                 return -EBUSY;
 299         }
 300
 301         for (i = 0; i < 2; i++) {
 302                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
 303                 if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 304                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
 305                         NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
 306                         NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
 307                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 308                         return -EBUSY;
 309                 }
 310
 311                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 312                         NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
 313                 if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 314                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
 315                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
 316                         NV_ERROR(dev, "timeout: "
 317                                       "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
 318                         NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
 319                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 320                         return -EBUSY;
 321                 }
 322         }
 323
 324         nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->instance >> 8) | 9);
 325
 326         /* initialise fifo */
 327         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_DMA_CB(0),
 328                 ((evo->pushbuf_bo->bo.mem.mm_node->start << PAGE_SHIFT) >> 8) |
 329                 NV50_PDISPLAY_CHANNEL_DMA_CB_LOCATION_VRAM |
 330                 NV50_PDISPLAY_CHANNEL_DMA_CB_VALID);
 331         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK2(0), 0x00010000);
 332         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK3(0), 0x00000002);
 333         if (!nv_wait(0x610200, 0x80000000, 0x00000000)) {
 334                 NV_ERROR(dev, "timeout: (0x610200 & 0x80000000) == 0\n");
 335                 NV_ERROR(dev, "0x610200 = 0x%08x\n", nv_rd32(dev, 0x610200));
 336                 return -EBUSY;
 337         }
 338         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
 339                 (nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)) & ~0x00000003) |
 340                  NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
 341         nv_wr32(dev, NV50_PDISPLAY_USER_PUT(0), 0);
 342         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x01000003 |
 343                 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
 344         nv_wr32(dev, 0x610300, nv_rd32(dev, 0x610300) & ~1);
 345
 346         evo->dma.max = (4096/4) - 2;
 347         evo->dma.put = 0;
 348         evo->dma.cur = evo->dma.put;
 349         evo->dma.free = evo->dma.max - evo->dma.cur;
 350
 351         ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
 352         if (ret)
 353                 return ret;
 354
 355         for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
 356                 OUT_RING(evo, 0);
 357
 358         ret = RING_SPACE(evo, 11);
 359         if (ret)
 360                 return ret;
 361         BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2);
 362         OUT_RING(evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
 363         OUT_RING(evo, NV50_EVO_DMA_NOTIFY_HANDLE_NONE);
 364         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, FB_DMA), 1);
 365         OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
 366         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK0800), 1);
 367         OUT_RING(evo, 0);
 368         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, DISPLAY_START), 1);
 369         OUT_RING(evo, 0);
 370         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK082C), 1);
 371         OUT_RING(evo, 0);
 372         FIRE_RING(evo);
 373         if (!nv_wait(0x640004, 0xffffffff, evo->dma.put << 2))
 374                 NV_ERROR(dev, "evo pushbuf stalled\n");
 375
 376         /* enable clock change interrupts. */
 377         nv_wr32(dev, 0x610028, 0x00010001);
 378         nv_wr32(dev, NV50_PDISPLAY_INTR_EN, (NV50_PDISPLAY_INTR_EN_CLK_UNK10 |
 379                                              NV50_PDISPLAY_INTR_EN_CLK_UNK20 |
 380                                              NV50_PDISPLAY_INTR_EN_CLK_UNK40));
 381
 382         /* enable hotplug interrupts */
 383         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 384                 struct nouveau_connector *conn = nouveau_connector(connector);
 385
 386                 if (conn->dcb->gpio_tag == 0xff)
 387                         continue;
 388
 389                 pgpio->irq_enable(dev, conn->dcb->gpio_tag, true);
 390         }
 391
 392         return 0;
 393 }
 394
 395 static int nv50_display_disable(struct drm_device *dev)
 396 {
 397         struct drm_nouveau_private *dev_priv = dev->dev_private;
 398         struct drm_crtc *drm_crtc;
 399         int ret, i;
 400
 401         NV_DEBUG_KMS(dev, "\n");
 402
 403         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 404                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 405
 406                 nv50_crtc_blank(crtc, true);
 407         }
 408
 409         ret = RING_SPACE(dev_priv->evo, 2);
 410         if (ret == 0) {
 411                 BEGIN_RING(dev_priv->evo, 0, NV50_EVO_UPDATE, 1);
 412                 OUT_RING(dev_priv->evo, 0);
 413         }
 414         FIRE_RING(dev_priv->evo);
 415
 416         /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
 417          * cleaning up?
 418          */
 419         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 420                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 421                 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
 422
 423                 if (!crtc->base.enabled)
 424                         continue;
 425
 426                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask);
 427                 if (!nv_wait(NV50_PDISPLAY_INTR_1, mask, mask)) {
 428                         NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == "
 429                                       "0x%08x\n", mask, mask);
 430                         NV_ERROR(dev, "0x610024 = 0x%08x\n",
 431                                  nv_rd32(dev, NV50_PDISPLAY_INTR_1));
 432                 }
 433         }
 434
 435         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0);
 436         nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, 0);
 437         if (!nv_wait(NV50_PDISPLAY_CHANNEL_STAT(0), 0x1e0000, 0)) {
 438                 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) == 0\n");
 439                 NV_ERROR(dev, "0x610200 = 0x%08x\n",
 440                           nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
 441         }
 442
 443         for (i = 0; i < 3; i++) {
 444                 if (!nv_wait(NV50_PDISPLAY_SOR_DPMS_STATE(i),
 445                              NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
 446                         NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
 447                         NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
 448                                   nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
 449                 }
 450         }
 451
 452         /* disable interrupts. */
 453         nv_wr32(dev, NV50_PDISPLAY_INTR_EN, 0x00000000);
 454
 455         /* disable hotplug interrupts */
 456         nv_wr32(dev, 0xe054, 0xffffffff);
 457         nv_wr32(dev, 0xe050, 0x00000000);
 458         if (dev_priv->chipset >= 0x90) {
 459                 nv_wr32(dev, 0xe074, 0xffffffff);
 460                 nv_wr32(dev, 0xe070, 0x00000000);
 461         }
 462         return 0;
 463 }
 464
 465 int nv50_display_create(struct drm_device *dev)
 466 {
 467         struct drm_nouveau_private *dev_priv = dev->dev_private;
 468         struct dcb_table *dcb = &dev_priv->vbios.dcb;
 469         struct drm_connector *connector, *ct;
 470         int ret, i;
 471
 472         NV_DEBUG_KMS(dev, "\n");
 473
 474         /* init basic kernel modesetting */
 475         drm_mode_config_init(dev);
 476
 477         /* Initialise some optional connector properties. */
 478         drm_mode_create_scaling_mode_property(dev);
 479         drm_mode_create_dithering_property(dev);
 480
 481         dev->mode_config.min_width = 0;
 482         dev->mode_config.min_height = 0;
 483
 484         dev->mode_config.funcs = (void *)&nouveau_mode_config_funcs;
 485
 486         dev->mode_config.max_width = 8192;
 487         dev->mode_config.max_height = 8192;
 488
 489         dev->mode_config.fb_base = dev_priv->fb_phys;
 490
 491         /* Create EVO channel */
 492         ret = nv50_evo_channel_new(dev, &dev_priv->evo);
 493         if (ret) {
 494                 NV_ERROR(dev, "Error creating EVO channel: %d\n", ret);
 495                 return ret;
 496         }
 497
 498         /* Create CRTC objects */
 499         for (i = 0; i < 2; i++)
 500                 nv50_crtc_create(dev, i);
 501
 502         /* We setup the encoders from the BIOS table */
 503         for (i = 0 ; i < dcb->entries; i++) {
 504                 struct dcb_entry *entry = &dcb->entry[i];
 505
 506                 if (entry->location != DCB_LOC_ON_CHIP) {
 507                         NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
 508                                 entry->type, ffs(entry->or) - 1);
 509                         continue;
 510                 }
 511
 512                 connector = nouveau_connector_create(dev, entry->connector);
 513                 if (IS_ERR(connector))
 514                         continue;
 515
 516                 switch (entry->type) {
 517                 case OUTPUT_TMDS:
 518                 case OUTPUT_LVDS:
 519                 case OUTPUT_DP:
 520                         nv50_sor_create(connector, entry);
 521                         break;
 522                 case OUTPUT_ANALOG:
 523                         nv50_dac_create(connector, entry);
 524                         break;
 525                 default:
 526                         NV_WARN(dev, "DCB encoder %d unknown\n", entry->type);
 527                         continue;
 528                 }
 529         }
 530
 531         list_for_each_entry_safe(connector, ct,
 532                                  &dev->mode_config.connector_list, head) {
 533                 if (!connector->encoder_ids[0]) {
 534                         NV_WARN(dev, "%s has no encoders, removing\n",
 535                                 drm_get_connector_name(connector));
 536                         connector->funcs->destroy(connector);
 537                 }
 538         }
 539
 540         ret = nv50_display_init(dev);
 541         if (ret) {
 542                 nv50_display_destroy(dev);
 543                 return ret;
 544         }
 545
 546         return 0;
 547 }
 548
 549 void
 550 nv50_display_destroy(struct drm_device *dev)
 551 {
 552         struct drm_nouveau_private *dev_priv = dev->dev_private;
 553
 554         NV_DEBUG_KMS(dev, "\n");
 555
 556         drm_mode_config_cleanup(dev);
 557
 558         nv50_display_disable(dev);
 559         nv50_evo_channel_del(&dev_priv->evo);
 560 }
 561
 562 static u16
 563 nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
 564                            u32 mc, int pxclk)
 565 {
 566         struct drm_nouveau_private *dev_priv = dev->dev_private;
 567         struct nouveau_connector *nv_connector = NULL;
 568         struct drm_encoder *encoder;
 569         struct nvbios *bios = &dev_priv->vbios;
 570         u32 script = 0, or;
 571
 572         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 573                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 574
 575                 if (nv_encoder->dcb != dcb)
 576                         continue;
 577
 578                 nv_connector = nouveau_encoder_connector_get(nv_encoder);
 579                 break;
 580         }
 581
 582         or = ffs(dcb->or) - 1;
 583         switch (dcb->type) {
 584         case OUTPUT_LVDS:
 585                 script = (mc >> 8) & 0xf;
 586                 if (bios->fp_no_ddc) {
 587                         if (bios->fp.dual_link)
 588                                 script |= 0x0100;
 589                         if (bios->fp.if_is_24bit)
 590                                 script |= 0x0200;
 591                 } else {
 592                         if (pxclk >= bios->fp.duallink_transition_clk) {
 593                                 script |= 0x0100;
 594                                 if (bios->fp.strapless_is_24bit & 2)
 595                                         script |= 0x0200;
 596                         } else
 597                         if (bios->fp.strapless_is_24bit & 1)
 598                                 script |= 0x0200;
 599
 600                         if (nv_connector && nv_connector->edid &&
 601                             (nv_connector->edid->revision >= 4) &&
 602                             (nv_connector->edid->input & 0x70) >= 0x20)
 603                                 script |= 0x0200;
 604                 }
 605
 606                 if (nouveau_uscript_lvds >= 0) {
 607                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
 608                                      "for output LVDS-%d\n", script,
 609                                      nouveau_uscript_lvds, or);
 610                         script = nouveau_uscript_lvds;
 611                 }
 612                 break;
 613         case OUTPUT_TMDS:
 614                 script = (mc >> 8) & 0xf;
 615                 if (pxclk >= 165000)
 616                         script |= 0x0100;
 617
 618                 if (nouveau_uscript_tmds >= 0) {
 619                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
 620                                      "for output TMDS-%d\n", script,
 621                                      nouveau_uscript_tmds, or);
 622                         script = nouveau_uscript_tmds;
 623                 }
 624                 break;
 625         case OUTPUT_DP:
 626                 script = (mc >> 8) & 0xf;
 627                 break;
 628         case OUTPUT_ANALOG:
 629                 script = 0xff;
 630                 break;
 631         default:
 632                 NV_ERROR(dev, "modeset on unsupported output type!\n");
 633                 break;
 634         }
 635
 636         return script;
 637 }
 638
 639 static void
 640 nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
 641 {
 642         struct drm_nouveau_private *dev_priv = dev->dev_private;
 643         struct nouveau_channel *chan;
 644         struct list_head *entry, *tmp;
 645
 646         list_for_each_safe(entry, tmp, &dev_priv->vbl_waiting) {
 647                 chan = list_entry(entry, struct nouveau_channel, nvsw.vbl_wait);
 648
 649                 nouveau_bo_wr32(chan->notifier_bo, chan->nvsw.vblsem_offset,
 650                                                 chan->nvsw.vblsem_rval);
 651                 list_del(&chan->nvsw.vbl_wait);
 652         }
 653 }
 654
 655 static void
 656 nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr)
 657 {
 658         intr &= NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
 659
 660         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0)
 661                 nv50_display_vblank_crtc_handler(dev, 0);
 662
 663         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1)
 664                 nv50_display_vblank_crtc_handler(dev, 1);
 665
 666         nv_wr32(dev, NV50_PDISPLAY_INTR_EN, nv_rd32(dev,
 667                      NV50_PDISPLAY_INTR_EN) & ~intr);
 668         nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr);
 669 }
 670
 671 static void
 672 nv50_display_unk10_handler(struct drm_device *dev)
 673 {
 674         struct drm_nouveau_private *dev_priv = dev->dev_private;
 675         u32 unk30 = nv_rd32(dev, 0x610030), mc;
 676         int i, crtc, or, type = OUTPUT_ANY;
 677
 678         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 679         dev_priv->evo_irq.dcb = NULL;
 680
 681         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
 682
 683         /* Determine which CRTC we're dealing with, only 1 ever will be
 684          * signalled at the same time with the current nouveau code.
 685          */
 686         crtc = ffs((unk30 & 0x00000060) >> 5) - 1;
 687         if (crtc < 0)
 688                 goto ack;
 689
 690         /* Nothing needs to be done for the encoder */
 691         crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
 692         if (crtc < 0)
 693                 goto ack;
 694
 695         /* Find which encoder was connected to the CRTC */
 696         for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
 697                 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
 698                 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
 699                 if (!(mc & (1 << crtc)))
 700                         continue;
 701
 702                 switch ((mc & 0x00000f00) >> 8) {
 703                 case 0: type = OUTPUT_ANALOG; break;
 704                 case 1: type = OUTPUT_TV; break;
 705                 default:
 706                         NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
 707                         goto ack;
 708                 }
 709
 710                 or = i;
 711         }
 712
 713         for (i = 0; type == OUTPUT_ANY && i < 4; i++) {
 714                 if (dev_priv->chipset  < 0x90 ||
 715                     dev_priv->chipset == 0x92 ||
 716                     dev_priv->chipset == 0xa0)
 717                         mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
 718                 else
 719                         mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
 720
 721                 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
 722                 if (!(mc & (1 << crtc)))
 723                         continue;
 724
 725                 switch ((mc & 0x00000f00) >> 8) {
 726                 case 0: type = OUTPUT_LVDS; break;
 727                 case 1: type = OUTPUT_TMDS; break;
 728                 case 2: type = OUTPUT_TMDS; break;
 729                 case 5: type = OUTPUT_TMDS; break;
 730                 case 8: type = OUTPUT_DP; break;
 731                 case 9: type = OUTPUT_DP; break;
 732                 default:
 733                         NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
 734                         goto ack;
 735                 }
 736
 737                 or = i;
 738         }
 739
 740         /* There was no encoder to disable */
 741         if (type == OUTPUT_ANY)
 742                 goto ack;
 743
 744         /* Disable the encoder */
 745         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
 746                 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
 747
 748                 if (dcb->type == type && (dcb->or & (1 << or))) {
 749                         nouveau_bios_run_display_table(dev, dcb, 0, -1);
 750                         dev_priv->evo_irq.dcb = dcb;
 751                         goto ack;
 752                 }
 753         }
 754
 755         NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
 756 ack:
 757         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
 758         nv_wr32(dev, 0x610030, 0x80000000);
 759 }
 760
 761 static void
 762 nv50_display_unk20_dp_hack(struct drm_device *dev, struct dcb_entry *dcb)
 763 {
 764         int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
 765         struct drm_encoder *encoder;
 766         uint32_t tmp, unk0 = 0, unk1 = 0;
 767
 768         if (dcb->type != OUTPUT_DP)
 769                 return;
 770
 771         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 772                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 773
 774                 if (nv_encoder->dcb == dcb) {
 775                         unk0 = nv_encoder->dp.unk0;
 776                         unk1 = nv_encoder->dp.unk1;
 777                         break;
 778                 }
 779         }
 780
 781         if (unk0 || unk1) {
 782                 tmp  = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
 783                 tmp &= 0xfffffe03;
 784                 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp | unk0);
 785
 786                 tmp  = nv_rd32(dev, NV50_SOR_DP_UNK128(or, link));
 787                 tmp &= 0xfef080c0;
 788                 nv_wr32(dev, NV50_SOR_DP_UNK128(or, link), tmp | unk1);
 789         }
 790 }
 791
 792 static void
 793 nv50_display_unk20_handler(struct drm_device *dev)
 794 {
 795         struct drm_nouveau_private *dev_priv = dev->dev_private;
 796         u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc;
 797         struct dcb_entry *dcb;
 798         int i, crtc, or, type = OUTPUT_ANY;
 799
 800         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 801         dcb = dev_priv->evo_irq.dcb;
 802         if (dcb) {
 803                 nouveau_bios_run_display_table(dev, dcb, 0, -2);
 804                 dev_priv->evo_irq.dcb = NULL;
 805         }
 806
 807         /* CRTC clock change requested? */
 808         crtc = ffs((unk30 & 0x00000600) >> 9) - 1;
 809         if (crtc >= 0) {
 810                 pclk  = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK));
 811                 pclk &= 0x003fffff;
 812
 813                 nv50_crtc_set_clock(dev, crtc, pclk);
 814
 815                 tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc));
 816                 tmp &= ~0x000000f;
 817                 nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp);
 818         }
 819
 820         /* Nothing needs to be done for the encoder */
 821         crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
 822         if (crtc < 0)
 823                 goto ack;
 824         pclk  = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff;
 825
 826         /* Find which encoder is connected to the CRTC */
 827         for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
 828                 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i));
 829                 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
 830                 if (!(mc & (1 << crtc)))
 831                         continue;
 832
 833                 switch ((mc & 0x00000f00) >> 8) {
 834                 case 0: type = OUTPUT_ANALOG; break;
 835                 case 1: type = OUTPUT_TV; break;
 836                 default:
 837                         NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
 838                         goto ack;
 839                 }
 840
 841                 or = i;
 842         }
 843
 844         for (i = 0; type == OUTPUT_ANY && i < 4; i++) {
 845                 if (dev_priv->chipset  < 0x90 ||
 846                     dev_priv->chipset == 0x92 ||
 847                     dev_priv->chipset == 0xa0)
 848                         mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(i));
 849                 else
 850                         mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(i));
 851
 852                 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
 853                 if (!(mc & (1 << crtc)))
 854                         continue;
 855
 856                 switch ((mc & 0x00000f00) >> 8) {
 857                 case 0: type = OUTPUT_LVDS; break;
 858                 case 1: type = OUTPUT_TMDS; break;
 859                 case 2: type = OUTPUT_TMDS; break;
 860                 case 5: type = OUTPUT_TMDS; break;
 861                 case 8: type = OUTPUT_DP; break;
 862                 case 9: type = OUTPUT_DP; break;
 863                 default:
 864                         NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
 865                         goto ack;
 866                 }
 867
 868                 or = i;
 869         }
 870
 871         if (type == OUTPUT_ANY)
 872                 goto ack;
 873
 874         /* Enable the encoder */
 875         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
 876                 dcb = &dev_priv->vbios.dcb.entry[i];
 877                 if (dcb->type == type && (dcb->or & (1 << or)))
 878                         break;
 879         }
 880
 881         if (i == dev_priv->vbios.dcb.entries) {
 882                 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
 883                 goto ack;
 884         }
 885
 886         script = nv50_display_script_select(dev, dcb, mc, pclk);
 887         nouveau_bios_run_display_table(dev, dcb, script, pclk);
 888
 889         nv50_display_unk20_dp_hack(dev, dcb);
 890
 891         if (dcb->type != OUTPUT_ANALOG) {
 892                 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
 893                 tmp &= ~0x00000f0f;
 894                 if (script & 0x0100)
 895                         tmp |= 0x00000101;
 896                 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
 897         } else {
 898                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
 899         }
 900
 901         dev_priv->evo_irq.dcb = dcb;
 902         dev_priv->evo_irq.pclk = pclk;
 903         dev_priv->evo_irq.script = script;
 904
 905 ack:
 906         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
 907         nv_wr32(dev, 0x610030, 0x80000000);
 908 }
 909
 910 /* If programming a TMDS output on a SOR that can also be configured for
 911  * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
 912  *
 913  * It looks like the VBIOS TMDS scripts make an attempt at this, however,
 914  * the VBIOS scripts on at least one board I have only switch it off on
 915  * link 0, causing a blank display if the output has previously been
 916  * programmed for DisplayPort.
 917  */
 918 static void
 919 nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_entry *dcb)
 920 {
 921         int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
 922         struct drm_encoder *encoder;
 923         u32 tmp;
 924
 925         if (dcb->type != OUTPUT_TMDS)
 926                 return;
 927
 928         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 929                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 930
 931                 if (nv_encoder->dcb->type == OUTPUT_DP &&
 932                     nv_encoder->dcb->or & (1 << or)) {
 933                         tmp  = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
 934                         tmp &= ~NV50_SOR_DP_CTRL_ENABLED;
 935                         nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
 936                         break;
 937                 }
 938         }
 939 }
 940
 941 static void
 942 nv50_display_unk40_handler(struct drm_device *dev)
 943 {
 944         struct drm_nouveau_private *dev_priv = dev->dev_private;
 945         struct dcb_entry *dcb = dev_priv->evo_irq.dcb;
 946         u16 script = dev_priv->evo_irq.script;
 947         u32 unk30 = nv_rd32(dev, 0x610030), pclk = dev_priv->evo_irq.pclk;
 948
 949         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 950         dev_priv->evo_irq.dcb = NULL;
 951         if (!dcb)
 952                 goto ack;
 953
 954         nouveau_bios_run_display_table(dev, dcb, script, -pclk);
 955         nv50_display_unk40_dp_set_tmds(dev, dcb);
 956
 957 ack:
 958         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
 959         nv_wr32(dev, 0x610030, 0x80000000);
 960         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8);
 961 }
 962
 963 void
 964 nv50_display_irq_handler_bh(struct work_struct *work)
 965 {
 966         struct drm_nouveau_private *dev_priv =
 967                 container_of(work, struct drm_nouveau_private, irq_work);
 968         struct drm_device *dev = dev_priv->dev;
 969
 970         for (;;) {
 971                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
 972                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
 973
 974                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
 975
 976                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
 977                         nv50_display_unk10_handler(dev);
 978                 else
 979                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
 980                         nv50_display_unk20_handler(dev);
 981                 else
 982                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
 983                         nv50_display_unk40_handler(dev);
 984                 else
 985                         break;
 986         }
 987
 988         nv_wr32(dev, NV03_PMC_INTR_EN_0, 1);
 989 }
 990
 991 static void
 992 nv50_display_error_handler(struct drm_device *dev)
 993 {
 994         uint32_t addr, data;
 995
 996         nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000);
 997         addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR);
 998         data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA);
 999
1000         NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x (0x%04x 0x%02x)\n",
1001                  0, addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
1002
1003         nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR, 0x90000000);
1004 }
1005
1006 void
1007 nv50_display_irq_hotplug_bh(struct work_struct *work)
1008 {
1009         struct drm_nouveau_private *dev_priv =
1010                 container_of(work, struct drm_nouveau_private, hpd_work);
1011         struct drm_device *dev = dev_priv->dev;
1012         struct drm_connector *connector;
1013         const uint32_t gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
1014         uint32_t unplug_mask, plug_mask, change_mask;
1015         uint32_t hpd0, hpd1 = 0;
1016
1017         hpd0 = nv_rd32(dev, 0xe054) & nv_rd32(dev, 0xe050);
1018         if (dev_priv->chipset >= 0x90)
1019                 hpd1 = nv_rd32(dev, 0xe074) & nv_rd32(dev, 0xe070);
1020
1021         plug_mask   = (hpd0 & 0x0000ffff) | (hpd1 << 16);
1022         unplug_mask = (hpd0 >> 16) | (hpd1 & 0xffff0000);
1023         change_mask = plug_mask | unplug_mask;
1024
1025         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1026                 struct drm_encoder_helper_funcs *helper;
1027                 struct nouveau_connector *nv_connector =
1028                         nouveau_connector(connector);
1029                 struct nouveau_encoder *nv_encoder;
1030                 struct dcb_gpio_entry *gpio;
1031                 uint32_t reg;
1032                 bool plugged;
1033
1034                 if (!nv_connector->dcb)
1035                         continue;
1036
1037                 gpio = nouveau_bios_gpio_entry(dev, nv_connector->dcb->gpio_tag);
1038                 if (!gpio || !(change_mask & (1 << gpio->line)))
1039                         continue;
1040
1041                 reg = nv_rd32(dev, gpio_reg[gpio->line >> 3]);
1042                 plugged = !!(reg & (4 << ((gpio->line & 7) << 2)));
1043                 NV_INFO(dev, "%splugged %s\n", plugged ? "" : "un",
1044                         drm_get_connector_name(connector)) ;
1045
1046                 if (!connector->encoder || !connector->encoder->crtc ||
1047                     !connector->encoder->crtc->enabled)
1048                         continue;
1049                 nv_encoder = nouveau_encoder(connector->encoder);
1050                 helper = connector->encoder->helper_private;
1051
1052                 if (nv_encoder->dcb->type != OUTPUT_DP)
1053                         continue;
1054
1055                 if (plugged)
1056                         helper->dpms(connector->encoder, DRM_MODE_DPMS_ON);
1057                 else
1058                         helper->dpms(connector->encoder, DRM_MODE_DPMS_OFF);
1059         }
1060
1061         nv_wr32(dev, 0xe054, nv_rd32(dev, 0xe054));
1062         if (dev_priv->chipset >= 0x90)
1063                 nv_wr32(dev, 0xe074, nv_rd32(dev, 0xe074));
1064
1065         drm_helper_hpd_irq_event(dev);
1066 }
1067
1068 void
1069 nv50_display_irq_handler(struct drm_device *dev)
1070 {
1071         struct drm_nouveau_private *dev_priv = dev->dev_private;
1072         uint32_t delayed = 0;
1073
1074         if (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_HOTPLUG) {
1075                 if (!work_pending(&dev_priv->hpd_work))
1076                         queue_work(dev_priv->wq, &dev_priv->hpd_work);
1077         }
1078
1079         while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
1080                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
1081                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
1082                 uint32_t clock;
1083
1084                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
1085
1086                 if (!intr0 && !(intr1 & ~delayed))
1087                         break;
1088
1089                 if (intr0 & 0x00010000) {
1090                         nv50_display_error_handler(dev);
1091                         intr0 &= ~0x00010000;
1092                 }
1093
1094                 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
1095                         nv50_display_vblank_handler(dev, intr1);
1096                         intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
1097                 }
1098
1099                 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
1100                                   NV50_PDISPLAY_INTR_1_CLK_UNK20 |
1101                                   NV50_PDISPLAY_INTR_1_CLK_UNK40));
1102                 if (clock) {
1103                         nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
1104                         if (!work_pending(&dev_priv->irq_work))
1105                                 queue_work(dev_priv->wq, &dev_priv->irq_work);
1106                         delayed |= clock;
1107                         intr1 &= ~clock;
1108                 }
1109
1110                 if (intr0) {
1111                         NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
1112                         nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0);
1113                 }
1114
1115                 if (intr1) {
1116                         NV_ERROR(dev,
1117                                  "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
1118                         nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1);
1119                 }
1120         }
1121 }
1122