drivers/gpu/drm/nouveau/nv50_display.c

   1 /*
   2  * Copyright (C) 2008 Maarten Maathuis.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
  28 #include "nv50_display.h"
  29 #include "nouveau_crtc.h"
  30 #include "nouveau_encoder.h"
  31 #include "nouveau_connector.h"
  32 #include "nouveau_fb.h"
  33 #include "nouveau_fbcon.h"
  34 #include "drm_crtc_helper.h"
  35 #include "nouveau_fence.h"
  36
  37 static void nv50_display_isr(struct drm_device *);
  38 static void nv50_display_bh(unsigned long);
  39
  40 static inline int
  41 nv50_sor_nr(struct drm_device *dev)
  42 {
  43         struct drm_nouveau_private *dev_priv = dev->dev_private;
  44
  45         if (dev_priv->chipset  < 0x90 ||
  46             dev_priv->chipset == 0x92 ||
  47             dev_priv->chipset == 0xa0)
  48                 return 2;
  49
  50         return 4;
  51 }
  52
  53 u32
  54 nv50_display_active_crtcs(struct drm_device *dev)
  55 {
  56         struct drm_nouveau_private *dev_priv = dev->dev_private;
  57         u32 mask = 0;
  58         int i;
  59
  60         if (dev_priv->chipset  < 0x90 ||
  61             dev_priv->chipset == 0x92 ||
  62             dev_priv->chipset == 0xa0) {
  63                 for (i = 0; i < 2; i++)
  64                         mask |= nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
  65         } else {
  66                 for (i = 0; i < 4; i++)
  67                         mask |= nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
  68         }
  69
  70         for (i = 0; i < 3; i++)
  71                 mask |= nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
  72
  73         return mask & 3;
  74 }
  75
  76 int
  77 nv50_display_early_init(struct drm_device *dev)
  78 {
  79         return 0;
  80 }
  81
  82 void
  83 nv50_display_late_takedown(struct drm_device *dev)
  84 {
  85 }
  86
  87 int
  88 nv50_display_sync(struct drm_device *dev)
  89 {
  90         struct nv50_display *disp = nv50_display(dev);
  91         struct nouveau_channel *evo = disp->master;
  92         u64 start;
  93         int ret;
  94
  95         ret = RING_SPACE(evo, 6);
  96         if (ret == 0) {
  97                 BEGIN_NV04(evo, 0, 0x0084, 1);
  98                 OUT_RING  (evo, 0x80000000);
  99                 BEGIN_NV04(evo, 0, 0x0080, 1);
 100                 OUT_RING  (evo, 0);
 101                 BEGIN_NV04(evo, 0, 0x0084, 1);
 102                 OUT_RING  (evo, 0x00000000);
 103
 104                 nv_wo32(disp->ramin, 0x2000, 0x00000000);
 105                 FIRE_RING (evo);
 106
 107                 start = nv_timer_read(dev);
 108                 do {
 109                         if (nv_ro32(disp->ramin, 0x2000))
 110                                 return 0;
 111                 } while (nv_timer_read(dev) - start < 2000000000ULL);
 112         }
 113
 114         return 0;
 115 }
 116
 117 int
 118 nv50_display_init(struct drm_device *dev)
 119 {
 120         struct nouveau_channel *evo;
 121         int ret, i;
 122         u32 val;
 123
 124         NV_DEBUG_KMS(dev, "\n");
 125
 126         nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
 127
 128         /*
 129          * I think the 0x006101XX range is some kind of main control area
 130          * that enables things.
 131          */
 132         /* CRTC? */
 133         for (i = 0; i < 2; i++) {
 134                 val = nv_rd32(dev, 0x00616100 + (i * 0x800));
 135                 nv_wr32(dev, 0x00610190 + (i * 0x10), val);
 136                 val = nv_rd32(dev, 0x00616104 + (i * 0x800));
 137                 nv_wr32(dev, 0x00610194 + (i * 0x10), val);
 138                 val = nv_rd32(dev, 0x00616108 + (i * 0x800));
 139                 nv_wr32(dev, 0x00610198 + (i * 0x10), val);
 140                 val = nv_rd32(dev, 0x0061610c + (i * 0x800));
 141                 nv_wr32(dev, 0x0061019c + (i * 0x10), val);
 142         }
 143
 144         /* DAC */
 145         for (i = 0; i < 3; i++) {
 146                 val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
 147                 nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
 148         }
 149
 150         /* SOR */
 151         for (i = 0; i < nv50_sor_nr(dev); i++) {
 152                 val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
 153                 nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
 154         }
 155
 156         /* EXT */
 157         for (i = 0; i < 3; i++) {
 158                 val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
 159                 nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
 160         }
 161
 162         for (i = 0; i < 3; i++) {
 163                 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
 164                         NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
 165                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
 166         }
 167
 168         /* The precise purpose is unknown, i suspect it has something to do
 169          * with text mode.
 170          */
 171         if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) {
 172                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100);
 173                 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1);
 174                 if (!nv_wait(dev, 0x006194e8, 2, 0)) {
 175                         NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n");
 176                         NV_ERROR(dev, "0x6194e8 = 0x%08x\n",
 177                                                 nv_rd32(dev, 0x6194e8));
 178                         return -EBUSY;
 179                 }
 180         }
 181
 182         for (i = 0; i < 2; i++) {
 183                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
 184                 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 185                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
 186                         NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
 187                         NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
 188                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 189                         return -EBUSY;
 190                 }
 191
 192                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 193                         NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
 194                 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 195                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
 196                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
 197                         NV_ERROR(dev, "timeout: "
 198                                       "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
 199                         NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
 200                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 201                         return -EBUSY;
 202                 }
 203         }
 204
 205         nv_wr32(dev, NV50_PDISPLAY_PIO_CTRL, 0x00000000);
 206         nv_mask(dev, NV50_PDISPLAY_INTR_0, 0x00000000, 0x00000000);
 207         nv_wr32(dev, NV50_PDISPLAY_INTR_EN_0, 0x00000000);
 208         nv_mask(dev, NV50_PDISPLAY_INTR_1, 0x00000000, 0x00000000);
 209         nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1,
 210                      NV50_PDISPLAY_INTR_EN_1_CLK_UNK10 |
 211                      NV50_PDISPLAY_INTR_EN_1_CLK_UNK20 |
 212                      NV50_PDISPLAY_INTR_EN_1_CLK_UNK40);
 213
 214         ret = nv50_evo_init(dev);
 215         if (ret)
 216                 return ret;
 217         evo = nv50_display(dev)->master;
 218
 219         nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (nv50_display(dev)->ramin->addr >> 8) | 9);
 220
 221         ret = RING_SPACE(evo, 3);
 222         if (ret)
 223                 return ret;
 224         BEGIN_NV04(evo, 0, NV50_EVO_UNK84, 2);
 225         OUT_RING  (evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
 226         OUT_RING  (evo, NvEvoSync);
 227
 228         return nv50_display_sync(dev);
 229 }
 230
 231 void
 232 nv50_display_fini(struct drm_device *dev)
 233 {
 234         struct nv50_display *disp = nv50_display(dev);
 235         struct nouveau_channel *evo = disp->master;
 236         struct drm_crtc *drm_crtc;
 237         int ret, i;
 238
 239         NV_DEBUG_KMS(dev, "\n");
 240
 241         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 242                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 243
 244                 nv50_crtc_blank(crtc, true);
 245         }
 246
 247         ret = RING_SPACE(evo, 2);
 248         if (ret == 0) {
 249                 BEGIN_NV04(evo, 0, NV50_EVO_UPDATE, 1);
 250                 OUT_RING(evo, 0);
 251         }
 252         FIRE_RING(evo);
 253
 254         /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
 255          * cleaning up?
 256          */
 257         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 258                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 259                 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
 260
 261                 if (!crtc->base.enabled)
 262                         continue;
 263
 264                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask);
 265                 if (!nv_wait(dev, NV50_PDISPLAY_INTR_1, mask, mask)) {
 266                         NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == "
 267                                       "0x%08x\n", mask, mask);
 268                         NV_ERROR(dev, "0x610024 = 0x%08x\n",
 269                                  nv_rd32(dev, NV50_PDISPLAY_INTR_1));
 270                 }
 271         }
 272
 273         for (i = 0; i < 2; i++) {
 274                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0);
 275                 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 276                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
 277                         NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
 278                         NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
 279                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 280                 }
 281         }
 282
 283         nv50_evo_fini(dev);
 284
 285         for (i = 0; i < 3; i++) {
 286                 if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i),
 287                              NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
 288                         NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
 289                         NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
 290                                   nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
 291                 }
 292         }
 293
 294         /* disable interrupts. */
 295         nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1, 0x00000000);
 296 }
 297
 298 int
 299 nv50_display_create(struct drm_device *dev)
 300 {
 301         struct drm_nouveau_private *dev_priv = dev->dev_private;
 302         struct dcb_table *dcb = &dev_priv->vbios.dcb;
 303         struct drm_connector *connector, *ct;
 304         struct nv50_display *priv;
 305         int ret, i;
 306
 307         NV_DEBUG_KMS(dev, "\n");
 308
 309         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 310         if (!priv)
 311                 return -ENOMEM;
 312         dev_priv->engine.display.priv = priv;
 313
 314         /* Create CRTC objects */
 315         for (i = 0; i < 2; i++) {
 316                 ret = nv50_crtc_create(dev, i);
 317                 if (ret)
 318                         return ret;
 319         }
 320
 321         /* We setup the encoders from the BIOS table */
 322         for (i = 0 ; i < dcb->entries; i++) {
 323                 struct dcb_output *entry = &dcb->entry[i];
 324
 325                 if (entry->location != DCB_LOC_ON_CHIP) {
 326                         NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
 327                                 entry->type, ffs(entry->or) - 1);
 328                         continue;
 329                 }
 330
 331                 connector = nouveau_connector_create(dev, entry->connector);
 332                 if (IS_ERR(connector))
 333                         continue;
 334
 335                 switch (entry->type) {
 336                 case DCB_OUTPUT_TMDS:
 337                 case DCB_OUTPUT_LVDS:
 338                 case DCB_OUTPUT_DP:
 339                         nv50_sor_create(connector, entry);
 340                         break;
 341                 case DCB_OUTPUT_ANALOG:
 342                         nv50_dac_create(connector, entry);
 343                         break;
 344                 default:
 345                         NV_WARN(dev, "DCB encoder %d unknown\n", entry->type);
 346                         continue;
 347                 }
 348         }
 349
 350         list_for_each_entry_safe(connector, ct,
 351                                  &dev->mode_config.connector_list, head) {
 352                 if (!connector->encoder_ids[0]) {
 353                         NV_WARN(dev, "%s has no encoders, removing\n",
 354                                 drm_get_connector_name(connector));
 355                         connector->funcs->destroy(connector);
 356                 }
 357         }
 358
 359         tasklet_init(&priv->tasklet, nv50_display_bh, (unsigned long)dev);
 360         nouveau_irq_register(dev, 26, nv50_display_isr);
 361
 362         ret = nv50_evo_create(dev);
 363         if (ret) {
 364                 nv50_display_destroy(dev);
 365                 return ret;
 366         }
 367
 368         return 0;
 369 }
 370
 371 void
 372 nv50_display_destroy(struct drm_device *dev)
 373 {
 374         struct nv50_display *disp = nv50_display(dev);
 375
 376         NV_DEBUG_KMS(dev, "\n");
 377
 378         nv50_evo_destroy(dev);
 379         nouveau_irq_unregister(dev, 26);
 380         kfree(disp);
 381 }
 382
 383 void
 384 nv50_display_flip_stop(struct drm_crtc *crtc)
 385 {
 386         struct nv50_display *disp = nv50_display(crtc->dev);
 387         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 388         struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index];
 389         struct nouveau_channel *evo = dispc->sync;
 390         int ret;
 391
 392         ret = RING_SPACE(evo, 8);
 393         if (ret) {
 394                 WARN_ON(1);
 395                 return;
 396         }
 397
 398         BEGIN_NV04(evo, 0, 0x0084, 1);
 399         OUT_RING  (evo, 0x00000000);
 400         BEGIN_NV04(evo, 0, 0x0094, 1);
 401         OUT_RING  (evo, 0x00000000);
 402         BEGIN_NV04(evo, 0, 0x00c0, 1);
 403         OUT_RING  (evo, 0x00000000);
 404         BEGIN_NV04(evo, 0, 0x0080, 1);
 405         OUT_RING  (evo, 0x00000000);
 406         FIRE_RING (evo);
 407 }
 408
 409 int
 410 nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 411                        struct nouveau_channel *chan)
 412 {
 413         struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
 414         struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
 415         struct nv50_display *disp = nv50_display(crtc->dev);
 416         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 417         struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index];
 418         struct nouveau_channel *evo = dispc->sync;
 419         int ret;
 420
 421         ret = RING_SPACE(evo, chan ? 25 : 27);
 422         if (unlikely(ret))
 423                 return ret;
 424
 425         /* synchronise with the rendering channel, if necessary */
 426         if (likely(chan)) {
 427                 ret = RING_SPACE(chan, 10);
 428                 if (ret) {
 429                         WIND_RING(evo);
 430                         return ret;
 431                 }
 432
 433                 if (dev_priv->chipset < 0xc0) {
 434                         BEGIN_NV04(chan, 0, 0x0060, 2);
 435                         OUT_RING  (chan, NvEvoSema0 + nv_crtc->index);
 436                         OUT_RING  (chan, dispc->sem.offset);
 437                         BEGIN_NV04(chan, 0, 0x006c, 1);
 438                         OUT_RING  (chan, 0xf00d0000 | dispc->sem.value);
 439                         BEGIN_NV04(chan, 0, 0x0064, 2);
 440                         OUT_RING  (chan, dispc->sem.offset ^ 0x10);
 441                         OUT_RING  (chan, 0x74b1e000);
 442                         BEGIN_NV04(chan, 0, 0x0060, 1);
 443                         if (dev_priv->chipset < 0x84)
 444                                 OUT_RING  (chan, NvSema);
 445                         else
 446                                 OUT_RING  (chan, chan->vram);
 447                 } else {
 448                         u64 offset = nvc0_fence_crtc(chan, nv_crtc->index);
 449                         offset += dispc->sem.offset;
 450                         BEGIN_NVC0(chan, 0, 0x0010, 4);
 451                         OUT_RING  (chan, upper_32_bits(offset));
 452                         OUT_RING  (chan, lower_32_bits(offset));
 453                         OUT_RING  (chan, 0xf00d0000 | dispc->sem.value);
 454                         OUT_RING  (chan, 0x1002);
 455                         BEGIN_NVC0(chan, 0, 0x0010, 4);
 456                         OUT_RING  (chan, upper_32_bits(offset));
 457                         OUT_RING  (chan, lower_32_bits(offset ^ 0x10));
 458                         OUT_RING  (chan, 0x74b1e000);
 459                         OUT_RING  (chan, 0x1001);
 460                 }
 461                 FIRE_RING (chan);
 462         } else {
 463                 nouveau_bo_wr32(dispc->sem.bo, dispc->sem.offset / 4,
 464                                 0xf00d0000 | dispc->sem.value);
 465         }
 466
 467         /* queue the flip on the crtc's "display sync" channel */
 468         BEGIN_NV04(evo, 0, 0x0100, 1);
 469         OUT_RING  (evo, 0xfffe0000);
 470         if (chan) {
 471                 BEGIN_NV04(evo, 0, 0x0084, 1);
 472                 OUT_RING  (evo, 0x00000100);
 473         } else {
 474                 BEGIN_NV04(evo, 0, 0x0084, 1);
 475                 OUT_RING  (evo, 0x00000010);
 476                 /* allows gamma somehow, PDISP will bitch at you if
 477                  * you don't wait for vblank before changing this..
 478                  */
 479                 BEGIN_NV04(evo, 0, 0x00e0, 1);
 480                 OUT_RING  (evo, 0x40000000);
 481         }
 482         BEGIN_NV04(evo, 0, 0x0088, 4);
 483         OUT_RING  (evo, dispc->sem.offset);
 484         OUT_RING  (evo, 0xf00d0000 | dispc->sem.value);
 485         OUT_RING  (evo, 0x74b1e000);
 486         OUT_RING  (evo, NvEvoSync);
 487         BEGIN_NV04(evo, 0, 0x00a0, 2);
 488         OUT_RING  (evo, 0x00000000);
 489         OUT_RING  (evo, 0x00000000);
 490         BEGIN_NV04(evo, 0, 0x00c0, 1);
 491         OUT_RING  (evo, nv_fb->r_dma);
 492         BEGIN_NV04(evo, 0, 0x0110, 2);
 493         OUT_RING  (evo, 0x00000000);
 494         OUT_RING  (evo, 0x00000000);
 495         BEGIN_NV04(evo, 0, 0x0800, 5);
 496         OUT_RING  (evo, nv_fb->nvbo->bo.offset >> 8);
 497         OUT_RING  (evo, 0);
 498         OUT_RING  (evo, (fb->height << 16) | fb->width);
 499         OUT_RING  (evo, nv_fb->r_pitch);
 500         OUT_RING  (evo, nv_fb->r_format);
 501         BEGIN_NV04(evo, 0, 0x0080, 1);
 502         OUT_RING  (evo, 0x00000000);
 503         FIRE_RING (evo);
 504
 505         dispc->sem.offset ^= 0x10;
 506         dispc->sem.value++;
 507         return 0;
 508 }
 509
 510 static u16
 511 nv50_display_script_select(struct drm_device *dev, struct dcb_output *dcb,
 512                            u32 mc, int pxclk)
 513 {
 514         struct drm_nouveau_private *dev_priv = dev->dev_private;
 515         struct nouveau_connector *nv_connector = NULL;
 516         struct drm_encoder *encoder;
 517         struct nvbios *bios = &dev_priv->vbios;
 518         u32 script = 0, or;
 519
 520         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 521                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 522
 523                 if (nv_encoder->dcb != dcb)
 524                         continue;
 525
 526                 nv_connector = nouveau_encoder_connector_get(nv_encoder);
 527                 break;
 528         }
 529
 530         or = ffs(dcb->or) - 1;
 531         switch (dcb->type) {
 532         case DCB_OUTPUT_LVDS:
 533                 script = (mc >> 8) & 0xf;
 534                 if (bios->fp_no_ddc) {
 535                         if (bios->fp.dual_link)
 536                                 script |= 0x0100;
 537                         if (bios->fp.if_is_24bit)
 538                                 script |= 0x0200;
 539                 } else {
 540                         /* determine number of lvds links */
 541                         if (nv_connector && nv_connector->edid &&
 542                             nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
 543                                 /* http://www.spwg.org */
 544                                 if (((u8 *)nv_connector->edid)[121] == 2)
 545                                         script |= 0x0100;
 546                         } else
 547                         if (pxclk >= bios->fp.duallink_transition_clk) {
 548                                 script |= 0x0100;
 549                         }
 550
 551                         /* determine panel depth */
 552                         if (script & 0x0100) {
 553                                 if (bios->fp.strapless_is_24bit & 2)
 554                                         script |= 0x0200;
 555                         } else {
 556                                 if (bios->fp.strapless_is_24bit & 1)
 557                                         script |= 0x0200;
 558                         }
 559
 560                         if (nv_connector && nv_connector->edid &&
 561                             (nv_connector->edid->revision >= 4) &&
 562                             (nv_connector->edid->input & 0x70) >= 0x20)
 563                                 script |= 0x0200;
 564                 }
 565
 566                 if (nouveau_uscript_lvds >= 0) {
 567                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
 568                                      "for output LVDS-%d\n", script,
 569                                      nouveau_uscript_lvds, or);
 570                         script = nouveau_uscript_lvds;
 571                 }
 572                 break;
 573         case DCB_OUTPUT_TMDS:
 574                 script = (mc >> 8) & 0xf;
 575                 if (pxclk >= 165000)
 576                         script |= 0x0100;
 577
 578                 if (nouveau_uscript_tmds >= 0) {
 579                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
 580                                      "for output TMDS-%d\n", script,
 581                                      nouveau_uscript_tmds, or);
 582                         script = nouveau_uscript_tmds;
 583                 }
 584                 break;
 585         case DCB_OUTPUT_DP:
 586                 script = (mc >> 8) & 0xf;
 587                 break;
 588         case DCB_OUTPUT_ANALOG:
 589                 script = 0xff;
 590                 break;
 591         default:
 592                 NV_ERROR(dev, "modeset on unsupported output type!\n");
 593                 break;
 594         }
 595
 596         return script;
 597 }
 598
 599 static void
 600 nv50_display_unk10_handler(struct drm_device *dev)
 601 {
 602         struct drm_nouveau_private *dev_priv = dev->dev_private;
 603         struct nv50_display *disp = nv50_display(dev);
 604         u32 unk30 = nv_rd32(dev, 0x610030), mc;
 605         int i, crtc, or = 0, type = DCB_OUTPUT_ANY;
 606
 607         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 608         disp->irq.dcb = NULL;
 609
 610         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
 611
 612         /* Determine which CRTC we're dealing with, only 1 ever will be
 613          * signalled at the same time with the current nouveau code.
 614          */
 615         crtc = ffs((unk30 & 0x00000060) >> 5) - 1;
 616         if (crtc < 0)
 617                 goto ack;
 618
 619         /* Nothing needs to be done for the encoder */
 620         crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
 621         if (crtc < 0)
 622                 goto ack;
 623
 624         /* Find which encoder was connected to the CRTC */
 625         for (i = 0; type == DCB_OUTPUT_ANY && i < 3; i++) {
 626                 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
 627                 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
 628                 if (!(mc & (1 << crtc)))
 629                         continue;
 630
 631                 switch ((mc & 0x00000f00) >> 8) {
 632                 case 0: type = DCB_OUTPUT_ANALOG; break;
 633                 case 1: type = DCB_OUTPUT_TV; break;
 634                 default:
 635                         NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
 636                         goto ack;
 637                 }
 638
 639                 or = i;
 640         }
 641
 642         for (i = 0; type == DCB_OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
 643                 if (dev_priv->chipset  < 0x90 ||
 644                     dev_priv->chipset == 0x92 ||
 645                     dev_priv->chipset == 0xa0)
 646                         mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
 647                 else
 648                         mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
 649
 650                 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
 651                 if (!(mc & (1 << crtc)))
 652                         continue;
 653
 654                 switch ((mc & 0x00000f00) >> 8) {
 655                 case 0: type = DCB_OUTPUT_LVDS; break;
 656                 case 1: type = DCB_OUTPUT_TMDS; break;
 657                 case 2: type = DCB_OUTPUT_TMDS; break;
 658                 case 5: type = DCB_OUTPUT_TMDS; break;
 659                 case 8: type = DCB_OUTPUT_DP; break;
 660                 case 9: type = DCB_OUTPUT_DP; break;
 661                 default:
 662                         NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
 663                         goto ack;
 664                 }
 665
 666                 or = i;
 667         }
 668
 669         /* There was no encoder to disable */
 670         if (type == DCB_OUTPUT_ANY)
 671                 goto ack;
 672
 673         /* Disable the encoder */
 674         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
 675                 struct dcb_output *dcb = &dev_priv->vbios.dcb.entry[i];
 676
 677                 if (dcb->type == type && (dcb->or & (1 << or))) {
 678                         nouveau_bios_run_display_table(dev, 0, -1, dcb, -1);
 679                         disp->irq.dcb = dcb;
 680                         goto ack;
 681                 }
 682         }
 683
 684         NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
 685 ack:
 686         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
 687         nv_wr32(dev, 0x610030, 0x80000000);
 688 }
 689
 690 static void
 691 nv50_display_unk20_handler(struct drm_device *dev)
 692 {
 693         struct drm_nouveau_private *dev_priv = dev->dev_private;
 694         struct nv50_display *disp = nv50_display(dev);
 695         u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc = 0;
 696         struct dcb_output *dcb;
 697         int i, crtc, or = 0, type = DCB_OUTPUT_ANY;
 698
 699         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 700         dcb = disp->irq.dcb;
 701         if (dcb) {
 702                 nouveau_bios_run_display_table(dev, 0, -2, dcb, -1);
 703                 disp->irq.dcb = NULL;
 704         }
 705
 706         /* CRTC clock change requested? */
 707         crtc = ffs((unk30 & 0x00000600) >> 9) - 1;
 708         if (crtc >= 0) {
 709                 pclk  = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK));
 710                 pclk &= 0x003fffff;
 711                 if (pclk)
 712                         nv50_crtc_set_clock(dev, crtc, pclk);
 713
 714                 tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc));
 715                 tmp &= ~0x000000f;
 716                 nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp);
 717         }
 718
 719         /* Nothing needs to be done for the encoder */
 720         crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
 721         if (crtc < 0)
 722                 goto ack;
 723         pclk  = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff;
 724
 725         /* Find which encoder is connected to the CRTC */
 726         for (i = 0; type == DCB_OUTPUT_ANY && i < 3; i++) {
 727                 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i));
 728                 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
 729                 if (!(mc & (1 << crtc)))
 730                         continue;
 731
 732                 switch ((mc & 0x00000f00) >> 8) {
 733                 case 0: type = DCB_OUTPUT_ANALOG; break;
 734                 case 1: type = DCB_OUTPUT_TV; break;
 735                 default:
 736                         NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
 737                         goto ack;
 738                 }
 739
 740                 or = i;
 741         }
 742
 743         for (i = 0; type == DCB_OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
 744                 if (dev_priv->chipset  < 0x90 ||
 745                     dev_priv->chipset == 0x92 ||
 746                     dev_priv->chipset == 0xa0)
 747                         mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(i));
 748                 else
 749                         mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(i));
 750
 751                 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
 752                 if (!(mc & (1 << crtc)))
 753                         continue;
 754
 755                 switch ((mc & 0x00000f00) >> 8) {
 756                 case 0: type = DCB_OUTPUT_LVDS; break;
 757                 case 1: type = DCB_OUTPUT_TMDS; break;
 758                 case 2: type = DCB_OUTPUT_TMDS; break;
 759                 case 5: type = DCB_OUTPUT_TMDS; break;
 760                 case 8: type = DCB_OUTPUT_DP; break;
 761                 case 9: type = DCB_OUTPUT_DP; break;
 762                 default:
 763                         NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
 764                         goto ack;
 765                 }
 766
 767                 or = i;
 768         }
 769
 770         if (type == DCB_OUTPUT_ANY)
 771                 goto ack;
 772
 773         /* Enable the encoder */
 774         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
 775                 dcb = &dev_priv->vbios.dcb.entry[i];
 776                 if (dcb->type == type && (dcb->or & (1 << or)))
 777                         break;
 778         }
 779
 780         if (i == dev_priv->vbios.dcb.entries) {
 781                 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
 782                 goto ack;
 783         }
 784
 785         script = nv50_display_script_select(dev, dcb, mc, pclk);
 786         nouveau_bios_run_display_table(dev, script, pclk, dcb, -1);
 787
 788         if (type == DCB_OUTPUT_DP) {
 789                 int link = !(dcb->dpconf.sor.link & 1);
 790                 if ((mc & 0x000f0000) == 0x00020000)
 791                         nv50_sor_dp_calc_tu(dev, or, link, pclk, 18);
 792                 else
 793                         nv50_sor_dp_calc_tu(dev, or, link, pclk, 24);
 794         }
 795
 796         if (dcb->type != DCB_OUTPUT_ANALOG) {
 797                 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
 798                 tmp &= ~0x00000f0f;
 799                 if (script & 0x0100)
 800                         tmp |= 0x00000101;
 801                 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
 802         } else {
 803                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
 804         }
 805
 806         disp->irq.dcb = dcb;
 807         disp->irq.pclk = pclk;
 808         disp->irq.script = script;
 809
 810 ack:
 811         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
 812         nv_wr32(dev, 0x610030, 0x80000000);
 813 }
 814
 815 /* If programming a TMDS output on a SOR that can also be configured for
 816  * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
 817  *
 818  * It looks like the VBIOS TMDS scripts make an attempt at this, however,
 819  * the VBIOS scripts on at least one board I have only switch it off on
 820  * link 0, causing a blank display if the output has previously been
 821  * programmed for DisplayPort.
 822  */
 823 static void
 824 nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_output *dcb)
 825 {
 826         int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
 827         struct drm_encoder *encoder;
 828         u32 tmp;
 829
 830         if (dcb->type != DCB_OUTPUT_TMDS)
 831                 return;
 832
 833         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 834                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 835
 836                 if (nv_encoder->dcb->type == DCB_OUTPUT_DP &&
 837                     nv_encoder->dcb->or & (1 << or)) {
 838                         tmp  = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
 839                         tmp &= ~NV50_SOR_DP_CTRL_ENABLED;
 840                         nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
 841                         break;
 842                 }
 843         }
 844 }
 845
 846 static void
 847 nv50_display_unk40_handler(struct drm_device *dev)
 848 {
 849         struct nv50_display *disp = nv50_display(dev);
 850         struct dcb_output *dcb = disp->irq.dcb;
 851         u16 script = disp->irq.script;
 852         u32 unk30 = nv_rd32(dev, 0x610030), pclk = disp->irq.pclk;
 853
 854         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 855         disp->irq.dcb = NULL;
 856         if (!dcb)
 857                 goto ack;
 858
 859         nouveau_bios_run_display_table(dev, script, -pclk, dcb, -1);
 860         nv50_display_unk40_dp_set_tmds(dev, dcb);
 861
 862 ack:
 863         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
 864         nv_wr32(dev, 0x610030, 0x80000000);
 865         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8);
 866 }
 867
 868 static void
 869 nv50_display_bh(unsigned long data)
 870 {
 871         struct drm_device *dev = (struct drm_device *)data;
 872
 873         for (;;) {
 874                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
 875                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
 876
 877                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
 878
 879                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
 880                         nv50_display_unk10_handler(dev);
 881                 else
 882                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
 883                         nv50_display_unk20_handler(dev);
 884                 else
 885                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
 886                         nv50_display_unk40_handler(dev);
 887                 else
 888                         break;
 889         }
 890
 891         nv_wr32(dev, NV03_PMC_INTR_EN_0, 1);
 892 }
 893
 894 static void
 895 nv50_display_error_handler(struct drm_device *dev)
 896 {
 897         u32 channels = (nv_rd32(dev, NV50_PDISPLAY_INTR_0) & 0x001f0000) >> 16;
 898         u32 addr, data;
 899         int chid;
 900
 901         for (chid = 0; chid < 5; chid++) {
 902                 if (!(channels & (1 << chid)))
 903                         continue;
 904
 905                 nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000 << chid);
 906                 addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid));
 907                 data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA(chid));
 908                 NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x "
 909                               "(0x%04x 0x%02x)\n", chid,
 910                          addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
 911
 912                 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid), 0x90000000);
 913         }
 914 }
 915
 916 static void
 917 nv50_display_isr(struct drm_device *dev)
 918 {
 919         struct nv50_display *disp = nv50_display(dev);
 920         uint32_t delayed = 0;
 921
 922         while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
 923                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
 924                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
 925                 uint32_t clock;
 926
 927                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
 928
 929                 if (!intr0 && !(intr1 & ~delayed))
 930                         break;
 931
 932                 if (intr0 & 0x001f0000) {
 933                         nv50_display_error_handler(dev);
 934                         intr0 &= ~0x001f0000;
 935                 }
 936
 937                 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
 938                         intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
 939                         delayed |= NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
 940                 }
 941
 942                 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
 943                                   NV50_PDISPLAY_INTR_1_CLK_UNK20 |
 944                                   NV50_PDISPLAY_INTR_1_CLK_UNK40));
 945                 if (clock) {
 946                         nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
 947                         tasklet_schedule(&disp->tasklet);
 948                         delayed |= clock;
 949                         intr1 &= ~clock;
 950                 }
 951
 952                 if (intr0) {
 953                         NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
 954                         nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0);
 955                 }
 956
 957                 if (intr1) {
 958                         NV_ERROR(dev,
 959                                  "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
 960                         nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1);
 961                 }
 962         }
 963 }