drivers/gpu/drm/nouveau/nv50_display.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <linux/dma-mapping.h>
  26
  27 #include <drm/drmP.h>
  28 #include <drm/drm_crtc_helper.h>
  29 #include <drm/drm_plane_helper.h>
  30 #include <drm/drm_dp_helper.h>
  31 #include <drm/drm_fb_helper.h>
  32
  33 #include <nvif/class.h>
  34 #include <nvif/cl0002.h>
  35 #include <nvif/cl5070.h>
  36 #include <nvif/cl507a.h>
  37 #include <nvif/cl507b.h>
  38 #include <nvif/cl507c.h>
  39 #include <nvif/cl507d.h>
  40 #include <nvif/cl507e.h>
  41
  42 #include "nouveau_drv.h"
  43 #include "nouveau_dma.h"
  44 #include "nouveau_gem.h"
  45 #include "nouveau_connector.h"
  46 #include "nouveau_encoder.h"
  47 #include "nouveau_crtc.h"
  48 #include "nouveau_fence.h"
  49 #include "nv50_display.h"
  50
  51 #define EVO_DMA_NR 9
  52
  53 #define EVO_MASTER  (0x00)
  54 #define EVO_FLIP(c) (0x01 + (c))
  55 #define EVO_OVLY(c) (0x05 + (c))
  56 #define EVO_OIMM(c) (0x09 + (c))
  57 #define EVO_CURS(c) (0x0d + (c))
  58
  59 /* offsets in shared sync bo of various structures */
  60 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
  61 #define EVO_MAST_NTFY     EVO_SYNC(      0, 0x00)
  62 #define EVO_FLIP_SEM0(c)  EVO_SYNC((c) + 1, 0x00)
  63 #define EVO_FLIP_SEM1(c)  EVO_SYNC((c) + 1, 0x10)
  64
  65 /******************************************************************************
  66  * EVO channel
  67  *****************************************************************************/
  68
  69 struct nv50_chan {
  70         struct nvif_object user;
  71         struct nvif_device *device;
  72 };
  73
  74 static int
  75 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
  76                  const s32 *oclass, u8 head, void *data, u32 size,
  77                  struct nv50_chan *chan)
  78 {
  79         struct nvif_sclass *sclass;
  80         int ret, i, n;
  81
  82         chan->device = device;
  83
  84         ret = n = nvif_object_sclass_get(disp, &sclass);
  85         if (ret < 0)
  86                 return ret;
  87
  88         while (oclass[0]) {
  89                 for (i = 0; i < n; i++) {
  90                         if (sclass[i].oclass == oclass[0]) {
  91                                 ret = nvif_object_init(disp, 0, oclass[0],
  92                                                        data, size, &chan->user);
  93                                 if (ret == 0)
  94                                         nvif_object_map(&chan->user);
  95                                 nvif_object_sclass_put(&sclass);
  96                                 return ret;
  97                         }
  98                 }
  99                 oclass++;
 100         }
 101
 102         nvif_object_sclass_put(&sclass);
 103         return -ENOSYS;
 104 }
 105
 106 static void
 107 nv50_chan_destroy(struct nv50_chan *chan)
 108 {
 109         nvif_object_fini(&chan->user);
 110 }
 111
 112 /******************************************************************************
 113  * PIO EVO channel
 114  *****************************************************************************/
 115
 116 struct nv50_pioc {
 117         struct nv50_chan base;
 118 };
 119
 120 static void
 121 nv50_pioc_destroy(struct nv50_pioc *pioc)
 122 {
 123         nv50_chan_destroy(&pioc->base);
 124 }
 125
 126 static int
 127 nv50_pioc_create(struct nvif_device *device, struct nvif_object *disp,
 128                  const s32 *oclass, u8 head, void *data, u32 size,
 129                  struct nv50_pioc *pioc)
 130 {
 131         return nv50_chan_create(device, disp, oclass, head, data, size,
 132                                 &pioc->base);
 133 }
 134
 135 /******************************************************************************
 136  * Cursor Immediate
 137  *****************************************************************************/
 138
 139 struct nv50_curs {
 140         struct nv50_pioc base;
 141 };
 142
 143 static int
 144 nv50_curs_create(struct nvif_device *device, struct nvif_object *disp,
 145                  int head, struct nv50_curs *curs)
 146 {
 147         struct nv50_disp_cursor_v0 args = {
 148                 .head = head,
 149         };
 150         static const s32 oclass[] = {
 151                 GK104_DISP_CURSOR,
 152                 GF110_DISP_CURSOR,
 153                 GT214_DISP_CURSOR,
 154                 G82_DISP_CURSOR,
 155                 NV50_DISP_CURSOR,
 156                 0
 157         };
 158
 159         return nv50_pioc_create(device, disp, oclass, head, &args, sizeof(args),
 160                                 &curs->base);
 161 }
 162
 163 /******************************************************************************
 164  * Overlay Immediate
 165  *****************************************************************************/
 166
 167 struct nv50_oimm {
 168         struct nv50_pioc base;
 169 };
 170
 171 static int
 172 nv50_oimm_create(struct nvif_device *device, struct nvif_object *disp,
 173                  int head, struct nv50_oimm *oimm)
 174 {
 175         struct nv50_disp_cursor_v0 args = {
 176                 .head = head,
 177         };
 178         static const s32 oclass[] = {
 179                 GK104_DISP_OVERLAY,
 180                 GF110_DISP_OVERLAY,
 181                 GT214_DISP_OVERLAY,
 182                 G82_DISP_OVERLAY,
 183                 NV50_DISP_OVERLAY,
 184                 0
 185         };
 186
 187         return nv50_pioc_create(device, disp, oclass, head, &args, sizeof(args),
 188                                 &oimm->base);
 189 }
 190
 191 /******************************************************************************
 192  * DMA EVO channel
 193  *****************************************************************************/
 194
 195 struct nv50_dmac {
 196         struct nv50_chan base;
 197         dma_addr_t handle;
 198         u32 *ptr;
 199
 200         struct nvif_object sync;
 201         struct nvif_object vram;
 202
 203         /* Protects against concurrent pushbuf access to this channel, lock is
 204          * grabbed by evo_wait (if the pushbuf reservation is successful) and
 205          * dropped again by evo_kick. */
 206         struct mutex lock;
 207 };
 208
 209 static void
 210 nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp)
 211 {
 212         struct nvif_device *device = dmac->base.device;
 213
 214         nvif_object_fini(&dmac->vram);
 215         nvif_object_fini(&dmac->sync);
 216
 217         nv50_chan_destroy(&dmac->base);
 218
 219         if (dmac->ptr) {
 220                 struct device *dev = nvxx_device(device)->dev;
 221                 dma_free_coherent(dev, PAGE_SIZE, dmac->ptr, dmac->handle);
 222         }
 223 }
 224
 225 static int
 226 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 227                  const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
 228                  struct nv50_dmac *dmac)
 229 {
 230         struct nv50_disp_core_channel_dma_v0 *args = data;
 231         struct nvif_object pushbuf;
 232         int ret;
 233
 234         mutex_init(&dmac->lock);
 235
 236         dmac->ptr = dma_alloc_coherent(nvxx_device(device)->dev, PAGE_SIZE,
 237                                        &dmac->handle, GFP_KERNEL);
 238         if (!dmac->ptr)
 239                 return -ENOMEM;
 240
 241         ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY,
 242                                &(struct nv_dma_v0) {
 243                                         .target = NV_DMA_V0_TARGET_PCI_US,
 244                                         .access = NV_DMA_V0_ACCESS_RD,
 245                                         .start = dmac->handle + 0x0000,
 246                                         .limit = dmac->handle + 0x0fff,
 247                                }, sizeof(struct nv_dma_v0), &pushbuf);
 248         if (ret)
 249                 return ret;
 250
 251         args->pushbuf = nvif_handle(&pushbuf);
 252
 253         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 254                                &dmac->base);
 255         nvif_object_fini(&pushbuf);
 256         if (ret)
 257                 return ret;
 258
 259         ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
 260                                &(struct nv_dma_v0) {
 261                                         .target = NV_DMA_V0_TARGET_VRAM,
 262                                         .access = NV_DMA_V0_ACCESS_RDWR,
 263                                         .start = syncbuf + 0x0000,
 264                                         .limit = syncbuf + 0x0fff,
 265                                }, sizeof(struct nv_dma_v0),
 266                                &dmac->sync);
 267         if (ret)
 268                 return ret;
 269
 270         ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
 271                                &(struct nv_dma_v0) {
 272                                         .target = NV_DMA_V0_TARGET_VRAM,
 273                                         .access = NV_DMA_V0_ACCESS_RDWR,
 274                                         .start = 0,
 275                                         .limit = device->info.ram_user - 1,
 276                                }, sizeof(struct nv_dma_v0),
 277                                &dmac->vram);
 278         if (ret)
 279                 return ret;
 280
 281         return ret;
 282 }
 283
 284 /******************************************************************************
 285  * Core
 286  *****************************************************************************/
 287
 288 struct nv50_mast {
 289         struct nv50_dmac base;
 290 };
 291
 292 static int
 293 nv50_core_create(struct nvif_device *device, struct nvif_object *disp,
 294                  u64 syncbuf, struct nv50_mast *core)
 295 {
 296         struct nv50_disp_core_channel_dma_v0 args = {
 297                 .pushbuf = 0xb0007d00,
 298         };
 299         static const s32 oclass[] = {
 300                 GP104_DISP_CORE_CHANNEL_DMA,
 301                 GP100_DISP_CORE_CHANNEL_DMA,
 302                 GM200_DISP_CORE_CHANNEL_DMA,
 303                 GM107_DISP_CORE_CHANNEL_DMA,
 304                 GK110_DISP_CORE_CHANNEL_DMA,
 305                 GK104_DISP_CORE_CHANNEL_DMA,
 306                 GF110_DISP_CORE_CHANNEL_DMA,
 307                 GT214_DISP_CORE_CHANNEL_DMA,
 308                 GT206_DISP_CORE_CHANNEL_DMA,
 309                 GT200_DISP_CORE_CHANNEL_DMA,
 310                 G82_DISP_CORE_CHANNEL_DMA,
 311                 NV50_DISP_CORE_CHANNEL_DMA,
 312                 0
 313         };
 314
 315         return nv50_dmac_create(device, disp, oclass, 0, &args, sizeof(args),
 316                                 syncbuf, &core->base);
 317 }
 318
 319 /******************************************************************************
 320  * Base
 321  *****************************************************************************/
 322
 323 struct nv50_sync {
 324         struct nv50_dmac base;
 325         u32 addr;
 326         u32 data;
 327 };
 328
 329 static int
 330 nv50_base_create(struct nvif_device *device, struct nvif_object *disp,
 331                  int head, u64 syncbuf, struct nv50_sync *base)
 332 {
 333         struct nv50_disp_base_channel_dma_v0 args = {
 334                 .pushbuf = 0xb0007c00 | head,
 335                 .head = head,
 336         };
 337         static const s32 oclass[] = {
 338                 GK110_DISP_BASE_CHANNEL_DMA,
 339                 GK104_DISP_BASE_CHANNEL_DMA,
 340                 GF110_DISP_BASE_CHANNEL_DMA,
 341                 GT214_DISP_BASE_CHANNEL_DMA,
 342                 GT200_DISP_BASE_CHANNEL_DMA,
 343                 G82_DISP_BASE_CHANNEL_DMA,
 344                 NV50_DISP_BASE_CHANNEL_DMA,
 345                 0
 346         };
 347
 348         return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
 349                                 syncbuf, &base->base);
 350 }
 351
 352 /******************************************************************************
 353  * Overlay
 354  *****************************************************************************/
 355
 356 struct nv50_ovly {
 357         struct nv50_dmac base;
 358 };
 359
 360 static int
 361 nv50_ovly_create(struct nvif_device *device, struct nvif_object *disp,
 362                  int head, u64 syncbuf, struct nv50_ovly *ovly)
 363 {
 364         struct nv50_disp_overlay_channel_dma_v0 args = {
 365                 .pushbuf = 0xb0007e00 | head,
 366                 .head = head,
 367         };
 368         static const s32 oclass[] = {
 369                 GK104_DISP_OVERLAY_CONTROL_DMA,
 370                 GF110_DISP_OVERLAY_CONTROL_DMA,
 371                 GT214_DISP_OVERLAY_CHANNEL_DMA,
 372                 GT200_DISP_OVERLAY_CHANNEL_DMA,
 373                 G82_DISP_OVERLAY_CHANNEL_DMA,
 374                 NV50_DISP_OVERLAY_CHANNEL_DMA,
 375                 0
 376         };
 377
 378         return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
 379                                 syncbuf, &ovly->base);
 380 }
 381
 382 struct nv50_head {
 383         struct nouveau_crtc base;
 384         struct nouveau_bo *image;
 385         struct nv50_curs curs;
 386         struct nv50_sync sync;
 387         struct nv50_ovly ovly;
 388         struct nv50_oimm oimm;
 389 };
 390
 391 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
 392 #define nv50_curs(c) (&nv50_head(c)->curs)
 393 #define nv50_sync(c) (&nv50_head(c)->sync)
 394 #define nv50_ovly(c) (&nv50_head(c)->ovly)
 395 #define nv50_oimm(c) (&nv50_head(c)->oimm)
 396 #define nv50_chan(c) (&(c)->base.base)
 397 #define nv50_vers(c) nv50_chan(c)->user.oclass
 398
 399 struct nv50_fbdma {
 400         struct list_head head;
 401         struct nvif_object core;
 402         struct nvif_object base[4];
 403 };
 404
 405 struct nv50_disp {
 406         struct nvif_object *disp;
 407         struct nv50_mast mast;
 408
 409         struct list_head fbdma;
 410
 411         struct nouveau_bo *sync;
 412 };
 413
 414 static struct nv50_disp *
 415 nv50_disp(struct drm_device *dev)
 416 {
 417         return nouveau_display(dev)->priv;
 418 }
 419
 420 #define nv50_mast(d) (&nv50_disp(d)->mast)
 421
 422 static struct drm_crtc *
 423 nv50_display_crtc_get(struct drm_encoder *encoder)
 424 {
 425         return nouveau_encoder(encoder)->crtc;
 426 }
 427
 428 /******************************************************************************
 429  * EVO channel helpers
 430  *****************************************************************************/
 431 static u32 *
 432 evo_wait(void *evoc, int nr)
 433 {
 434         struct nv50_dmac *dmac = evoc;
 435         struct nvif_device *device = dmac->base.device;
 436         u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
 437
 438         mutex_lock(&dmac->lock);
 439         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 440                 dmac->ptr[put] = 0x20000000;
 441
 442                 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
 443                 if (nvif_msec(device, 2000,
 444                         if (!nvif_rd32(&dmac->base.user, 0x0004))
 445                                 break;
 446                 ) < 0) {
 447                         mutex_unlock(&dmac->lock);
 448                         printk(KERN_ERR "nouveau: evo channel stalled\n");
 449                         return NULL;
 450                 }
 451
 452                 put = 0;
 453         }
 454
 455         return dmac->ptr + put;
 456 }
 457
 458 static void
 459 evo_kick(u32 *push, void *evoc)
 460 {
 461         struct nv50_dmac *dmac = evoc;
 462         nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 463         mutex_unlock(&dmac->lock);
 464 }
 465
 466 #define evo_mthd(p,m,s) do {                                                   \
 467         const u32 _m = (m), _s = (s);                                          \
 468         if (drm_debug & DRM_UT_KMS)                                            \
 469                 printk(KERN_ERR "%04x %d %s\n", _m, _s, __func__);             \
 470         *((p)++) = ((_s << 18) | _m);                                          \
 471 } while(0)
 472
 473 #define evo_data(p,d) do {                                                     \
 474         const u32 _d = (d);                                                    \
 475         if (drm_debug & DRM_UT_KMS)                                            \
 476                 printk(KERN_ERR "\t%08x\n", _d);                               \
 477         *((p)++) = _d;                                                         \
 478 } while(0)
 479
 480 static bool
 481 evo_sync_wait(void *data)
 482 {
 483         if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000)
 484                 return true;
 485         usleep_range(1, 2);
 486         return false;
 487 }
 488
 489 static int
 490 evo_sync(struct drm_device *dev)
 491 {
 492         struct nvif_device *device = &nouveau_drm(dev)->device;
 493         struct nv50_disp *disp = nv50_disp(dev);
 494         struct nv50_mast *mast = nv50_mast(dev);
 495         u32 *push = evo_wait(mast, 8);
 496         if (push) {
 497                 nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
 498                 evo_mthd(push, 0x0084, 1);
 499                 evo_data(push, 0x80000000 | EVO_MAST_NTFY);
 500                 evo_mthd(push, 0x0080, 2);
 501                 evo_data(push, 0x00000000);
 502                 evo_data(push, 0x00000000);
 503                 evo_kick(push, mast);
 504                 if (nvif_msec(device, 2000,
 505                         if (evo_sync_wait(disp->sync))
 506                                 break;
 507                 ) >= 0)
 508                         return 0;
 509         }
 510
 511         return -EBUSY;
 512 }
 513
 514 /******************************************************************************
 515  * Page flipping channel
 516  *****************************************************************************/
 517 struct nouveau_bo *
 518 nv50_display_crtc_sema(struct drm_device *dev, int crtc)
 519 {
 520         return nv50_disp(dev)->sync;
 521 }
 522
 523 struct nv50_display_flip {
 524         struct nv50_disp *disp;
 525         struct nv50_sync *chan;
 526 };
 527
 528 static bool
 529 nv50_display_flip_wait(void *data)
 530 {
 531         struct nv50_display_flip *flip = data;
 532         if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) ==
 533                                               flip->chan->data)
 534                 return true;
 535         usleep_range(1, 2);
 536         return false;
 537 }
 538
 539 void
 540 nv50_display_flip_stop(struct drm_crtc *crtc)
 541 {
 542         struct nvif_device *device = &nouveau_drm(crtc->dev)->device;
 543         struct nv50_display_flip flip = {
 544                 .disp = nv50_disp(crtc->dev),
 545                 .chan = nv50_sync(crtc),
 546         };
 547         u32 *push;
 548
 549         push = evo_wait(flip.chan, 8);
 550         if (push) {
 551                 evo_mthd(push, 0x0084, 1);
 552                 evo_data(push, 0x00000000);
 553                 evo_mthd(push, 0x0094, 1);
 554                 evo_data(push, 0x00000000);
 555                 evo_mthd(push, 0x00c0, 1);
 556                 evo_data(push, 0x00000000);
 557                 evo_mthd(push, 0x0080, 1);
 558                 evo_data(push, 0x00000000);
 559                 evo_kick(push, flip.chan);
 560         }
 561
 562         nvif_msec(device, 2000,
 563                 if (nv50_display_flip_wait(&flip))
 564                         break;
 565         );
 566 }
 567
 568 int
 569 nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 570                        struct nouveau_channel *chan, u32 swap_interval)
 571 {
 572         struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
 573         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 574         struct nv50_head *head = nv50_head(crtc);
 575         struct nv50_sync *sync = nv50_sync(crtc);
 576         u32 *push;
 577         int ret;
 578
 579         if (crtc->primary->fb->width != fb->width ||
 580             crtc->primary->fb->height != fb->height)
 581                 return -EINVAL;
 582
 583         swap_interval <<= 4;
 584         if (swap_interval == 0)
 585                 swap_interval |= 0x100;
 586         if (chan == NULL)
 587                 evo_sync(crtc->dev);
 588
 589         push = evo_wait(sync, 128);
 590         if (unlikely(push == NULL))
 591                 return -EBUSY;
 592
 593         if (chan && chan->user.oclass < G82_CHANNEL_GPFIFO) {
 594                 ret = RING_SPACE(chan, 8);
 595                 if (ret)
 596                         return ret;
 597
 598                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
 599                 OUT_RING  (chan, NvEvoSema0 + nv_crtc->index);
 600                 OUT_RING  (chan, sync->addr ^ 0x10);
 601                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
 602                 OUT_RING  (chan, sync->data + 1);
 603                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
 604                 OUT_RING  (chan, sync->addr);
 605                 OUT_RING  (chan, sync->data);
 606         } else
 607         if (chan && chan->user.oclass < FERMI_CHANNEL_GPFIFO) {
 608                 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
 609                 ret = RING_SPACE(chan, 12);
 610                 if (ret)
 611                         return ret;
 612
 613                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
 614                 OUT_RING  (chan, chan->vram.handle);
 615                 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 616                 OUT_RING  (chan, upper_32_bits(addr ^ 0x10));
 617                 OUT_RING  (chan, lower_32_bits(addr ^ 0x10));
 618                 OUT_RING  (chan, sync->data + 1);
 619                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
 620                 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 621                 OUT_RING  (chan, upper_32_bits(addr));
 622                 OUT_RING  (chan, lower_32_bits(addr));
 623                 OUT_RING  (chan, sync->data);
 624                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL);
 625         } else
 626         if (chan) {
 627                 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
 628                 ret = RING_SPACE(chan, 10);
 629                 if (ret)
 630                         return ret;
 631
 632                 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 633                 OUT_RING  (chan, upper_32_bits(addr ^ 0x10));
 634                 OUT_RING  (chan, lower_32_bits(addr ^ 0x10));
 635                 OUT_RING  (chan, sync->data + 1);
 636                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG |
 637                                  NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
 638                 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 639                 OUT_RING  (chan, upper_32_bits(addr));
 640                 OUT_RING  (chan, lower_32_bits(addr));
 641                 OUT_RING  (chan, sync->data);
 642                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL |
 643                                  NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
 644         }
 645
 646         if (chan) {
 647                 sync->addr ^= 0x10;
 648                 sync->data++;
 649                 FIRE_RING (chan);
 650         }
 651
 652         /* queue the flip */
 653         evo_mthd(push, 0x0100, 1);
 654         evo_data(push, 0xfffe0000);
 655         evo_mthd(push, 0x0084, 1);
 656         evo_data(push, swap_interval);
 657         if (!(swap_interval & 0x00000100)) {
 658                 evo_mthd(push, 0x00e0, 1);
 659                 evo_data(push, 0x40000000);
 660         }
 661         evo_mthd(push, 0x0088, 4);
 662         evo_data(push, sync->addr);
 663         evo_data(push, sync->data++);
 664         evo_data(push, sync->data);
 665         evo_data(push, sync->base.sync.handle);
 666         evo_mthd(push, 0x00a0, 2);
 667         evo_data(push, 0x00000000);
 668         evo_data(push, 0x00000000);
 669         evo_mthd(push, 0x00c0, 1);
 670         evo_data(push, nv_fb->r_handle);
 671         evo_mthd(push, 0x0110, 2);
 672         evo_data(push, 0x00000000);
 673         evo_data(push, 0x00000000);
 674         if (nv50_vers(sync) < GF110_DISP_BASE_CHANNEL_DMA) {
 675                 evo_mthd(push, 0x0800, 5);
 676                 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
 677                 evo_data(push, 0);
 678                 evo_data(push, (fb->height << 16) | fb->width);
 679                 evo_data(push, nv_fb->r_pitch);
 680                 evo_data(push, nv_fb->r_format);
 681         } else {
 682                 evo_mthd(push, 0x0400, 5);
 683                 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
 684                 evo_data(push, 0);
 685                 evo_data(push, (fb->height << 16) | fb->width);
 686                 evo_data(push, nv_fb->r_pitch);
 687                 evo_data(push, nv_fb->r_format);
 688         }
 689         evo_mthd(push, 0x0080, 1);
 690         evo_data(push, 0x00000000);
 691         evo_kick(push, sync);
 692
 693         nouveau_bo_ref(nv_fb->nvbo, &head->image);
 694         return 0;
 695 }
 696
 697 /******************************************************************************
 698  * CRTC
 699  *****************************************************************************/
 700 static int
 701 nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
 702 {
 703         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 704         struct nouveau_connector *nv_connector;
 705         struct drm_connector *connector;
 706         u32 *push, mode = 0x00;
 707
 708         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 709         connector = &nv_connector->base;
 710         if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
 711                 if (nv_crtc->base.primary->fb->depth > connector->display_info.bpc * 3)
 712                         mode = DITHERING_MODE_DYNAMIC2X2;
 713         } else {
 714                 mode = nv_connector->dithering_mode;
 715         }
 716
 717         if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
 718                 if (connector->display_info.bpc >= 8)
 719                         mode |= DITHERING_DEPTH_8BPC;
 720         } else {
 721                 mode |= nv_connector->dithering_depth;
 722         }
 723
 724         push = evo_wait(mast, 4);
 725         if (push) {
 726                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 727                         evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1);
 728                         evo_data(push, mode);
 729                 } else
 730                 if (nv50_vers(mast) < GK104_DISP_CORE_CHANNEL_DMA) {
 731                         evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1);
 732                         evo_data(push, mode);
 733                 } else {
 734                         evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1);
 735                         evo_data(push, mode);
 736                 }
 737
 738                 if (update) {
 739                         evo_mthd(push, 0x0080, 1);
 740                         evo_data(push, 0x00000000);
 741                 }
 742                 evo_kick(push, mast);
 743         }
 744
 745         return 0;
 746 }
 747
 748 static int
 749 nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
 750 {
 751         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 752         struct drm_display_mode *omode, *umode = &nv_crtc->base.mode;
 753         struct drm_crtc *crtc = &nv_crtc->base;
 754         struct nouveau_connector *nv_connector;
 755         int mode = DRM_MODE_SCALE_NONE;
 756         u32 oX, oY, *push;
 757
 758         /* start off at the resolution we programmed the crtc for, this
 759          * effectively handles NONE/FULL scaling
 760          */
 761         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 762         if (nv_connector && nv_connector->native_mode) {
 763                 mode = nv_connector->scaling_mode;
 764                 if (nv_connector->scaling_full) /* non-EDID LVDS/eDP mode */
 765                         mode = DRM_MODE_SCALE_FULLSCREEN;
 766         }
 767
 768         if (mode != DRM_MODE_SCALE_NONE)
 769                 omode = nv_connector->native_mode;
 770         else
 771                 omode = umode;
 772
 773         oX = omode->hdisplay;
 774         oY = omode->vdisplay;
 775         if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
 776                 oY *= 2;
 777
 778         /* add overscan compensation if necessary, will keep the aspect
 779          * ratio the same as the backend mode unless overridden by the
 780          * user setting both hborder and vborder properties.
 781          */
 782         if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
 783                              (nv_connector->underscan == UNDERSCAN_AUTO &&
 784                               drm_detect_hdmi_monitor(nv_connector->edid)))) {
 785                 u32 bX = nv_connector->underscan_hborder;
 786                 u32 bY = nv_connector->underscan_vborder;
 787                 u32 aspect = (oY << 19) / oX;
 788
 789                 if (bX) {
 790                         oX -= (bX * 2);
 791                         if (bY) oY -= (bY * 2);
 792                         else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
 793                 } else {
 794                         oX -= (oX >> 4) + 32;
 795                         if (bY) oY -= (bY * 2);
 796                         else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
 797                 }
 798         }
 799
 800         /* handle CENTER/ASPECT scaling, taking into account the areas
 801          * removed already for overscan compensation
 802          */
 803         switch (mode) {
 804         case DRM_MODE_SCALE_CENTER:
 805                 oX = min((u32)umode->hdisplay, oX);
 806                 oY = min((u32)umode->vdisplay, oY);
 807                 /* fall-through */
 808         case DRM_MODE_SCALE_ASPECT:
 809                 if (oY < oX) {
 810                         u32 aspect = (umode->hdisplay << 19) / umode->vdisplay;
 811                         oX = ((oY * aspect) + (aspect / 2)) >> 19;
 812                 } else {
 813                         u32 aspect = (umode->vdisplay << 19) / umode->hdisplay;
 814                         oY = ((oX * aspect) + (aspect / 2)) >> 19;
 815                 }
 816                 break;
 817         default:
 818                 break;
 819         }
 820
 821         push = evo_wait(mast, 8);
 822         if (push) {
 823                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 824                         /*XXX: SCALE_CTRL_ACTIVE??? */
 825                         evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2);
 826                         evo_data(push, (oY << 16) | oX);
 827                         evo_data(push, (oY << 16) | oX);
 828                         evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1);
 829                         evo_data(push, 0x00000000);
 830                         evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1);
 831                         evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
 832                 } else {
 833                         evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
 834                         evo_data(push, (oY << 16) | oX);
 835                         evo_data(push, (oY << 16) | oX);
 836                         evo_data(push, (oY << 16) | oX);
 837                         evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
 838                         evo_data(push, 0x00000000);
 839                         evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
 840                         evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
 841                 }
 842
 843                 evo_kick(push, mast);
 844
 845                 if (update) {
 846                         nv50_display_flip_stop(crtc);
 847                         nv50_display_flip_next(crtc, crtc->primary->fb,
 848                                                NULL, 1);
 849                 }
 850         }
 851
 852         return 0;
 853 }
 854
 855 static int
 856 nv50_crtc_set_raster_vblank_dmi(struct nouveau_crtc *nv_crtc, u32 usec)
 857 {
 858         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 859         u32 *push;
 860
 861         push = evo_wait(mast, 8);
 862         if (!push)
 863                 return -ENOMEM;
 864
 865         evo_mthd(push, 0x0828 + (nv_crtc->index * 0x400), 1);
 866         evo_data(push, usec);
 867         evo_kick(push, mast);
 868         return 0;
 869 }
 870
 871 static int
 872 nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
 873 {
 874         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 875         u32 *push, hue, vib;
 876         int adj;
 877
 878         adj = (nv_crtc->color_vibrance > 0) ? 50 : 0;
 879         vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff;
 880         hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff;
 881
 882         push = evo_wait(mast, 16);
 883         if (push) {
 884                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 885                         evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1);
 886                         evo_data(push, (hue << 20) | (vib << 8));
 887                 } else {
 888                         evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1);
 889                         evo_data(push, (hue << 20) | (vib << 8));
 890                 }
 891
 892                 if (update) {
 893                         evo_mthd(push, 0x0080, 1);
 894                         evo_data(push, 0x00000000);
 895                 }
 896                 evo_kick(push, mast);
 897         }
 898
 899         return 0;
 900 }
 901
 902 static int
 903 nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
 904                     int x, int y, bool update)
 905 {
 906         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
 907         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 908         u32 *push;
 909
 910         push = evo_wait(mast, 16);
 911         if (push) {
 912                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 913                         evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1);
 914                         evo_data(push, nvfb->nvbo->bo.offset >> 8);
 915                         evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3);
 916                         evo_data(push, (fb->height << 16) | fb->width);
 917                         evo_data(push, nvfb->r_pitch);
 918                         evo_data(push, nvfb->r_format);
 919                         evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1);
 920                         evo_data(push, (y << 16) | x);
 921                         if (nv50_vers(mast) > NV50_DISP_CORE_CHANNEL_DMA) {
 922                                 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
 923                                 evo_data(push, nvfb->r_handle);
 924                         }
 925                 } else {
 926                         evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
 927                         evo_data(push, nvfb->nvbo->bo.offset >> 8);
 928                         evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
 929                         evo_data(push, (fb->height << 16) | fb->width);
 930                         evo_data(push, nvfb->r_pitch);
 931                         evo_data(push, nvfb->r_format);
 932                         evo_data(push, nvfb->r_handle);
 933                         evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
 934                         evo_data(push, (y << 16) | x);
 935                 }
 936
 937                 if (update) {
 938                         evo_mthd(push, 0x0080, 1);
 939                         evo_data(push, 0x00000000);
 940                 }
 941                 evo_kick(push, mast);
 942         }
 943
 944         nv_crtc->fb.handle = nvfb->r_handle;
 945         return 0;
 946 }
 947
 948 static void
 949 nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc)
 950 {
 951         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 952         u32 *push = evo_wait(mast, 16);
 953         if (push) {
 954                 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
 955                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
 956                         evo_data(push, 0x85000000);
 957                         evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 958                 } else
 959                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 960                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
 961                         evo_data(push, 0x85000000);
 962                         evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 963                         evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
 964                         evo_data(push, mast->base.vram.handle);
 965                 } else {
 966                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
 967                         evo_data(push, 0x85000000);
 968                         evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 969                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 970                         evo_data(push, mast->base.vram.handle);
 971                 }
 972                 evo_kick(push, mast);
 973         }
 974         nv_crtc->cursor.visible = true;
 975 }
 976
 977 static void
 978 nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc)
 979 {
 980         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 981         u32 *push = evo_wait(mast, 16);
 982         if (push) {
 983                 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
 984                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
 985                         evo_data(push, 0x05000000);
 986                 } else
 987                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 988                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
 989                         evo_data(push, 0x05000000);
 990                         evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
 991                         evo_data(push, 0x00000000);
 992                 } else {
 993                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
 994                         evo_data(push, 0x05000000);
 995                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 996                         evo_data(push, 0x00000000);
 997                 }
 998                 evo_kick(push, mast);
 999         }
1000         nv_crtc->cursor.visible = false;
1001 }
1002
1003 static void
1004 nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update)
1005 {
1006         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
1007
1008         if (show && nv_crtc->cursor.nvbo && nv_crtc->base.enabled)
1009                 nv50_crtc_cursor_show(nv_crtc);
1010         else
1011                 nv50_crtc_cursor_hide(nv_crtc);
1012
1013         if (update) {
1014                 u32 *push = evo_wait(mast, 2);
1015                 if (push) {
1016                         evo_mthd(push, 0x0080, 1);
1017                         evo_data(push, 0x00000000);
1018                         evo_kick(push, mast);
1019                 }
1020         }
1021 }
1022
1023 static void
1024 nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
1025 {
1026 }
1027
1028 static void
1029 nv50_crtc_prepare(struct drm_crtc *crtc)
1030 {
1031         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1032         struct nv50_mast *mast = nv50_mast(crtc->dev);
1033         u32 *push;
1034
1035         nv50_display_flip_stop(crtc);
1036
1037         push = evo_wait(mast, 6);
1038         if (push) {
1039                 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
1040                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1041                         evo_data(push, 0x00000000);
1042                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
1043                         evo_data(push, 0x40000000);
1044                 } else
1045                 if (nv50_vers(mast) <  GF110_DISP_CORE_CHANNEL_DMA) {
1046                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1047                         evo_data(push, 0x00000000);
1048                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
1049                         evo_data(push, 0x40000000);
1050                         evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
1051                         evo_data(push, 0x00000000);
1052                 } else {
1053                         evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
1054                         evo_data(push, 0x00000000);
1055                         evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
1056                         evo_data(push, 0x03000000);
1057                         evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
1058                         evo_data(push, 0x00000000);
1059                 }
1060
1061                 evo_kick(push, mast);
1062         }
1063
1064         nv50_crtc_cursor_show_hide(nv_crtc, false, false);
1065 }
1066
1067 static void
1068 nv50_crtc_commit(struct drm_crtc *crtc)
1069 {
1070         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1071         struct nv50_mast *mast = nv50_mast(crtc->dev);
1072         u32 *push;
1073
1074         push = evo_wait(mast, 32);
1075         if (push) {
1076                 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
1077                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1078                         evo_data(push, nv_crtc->fb.handle);
1079                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1080                         evo_data(push, 0xc0000000);
1081                         evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1082                 } else
1083                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1084                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1085                         evo_data(push, nv_crtc->fb.handle);
1086                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1087                         evo_data(push, 0xc0000000);
1088                         evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1089                         evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
1090                         evo_data(push, mast->base.vram.handle);
1091                 } else {
1092                         evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
1093                         evo_data(push, nv_crtc->fb.handle);
1094                         evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
1095                         evo_data(push, 0x83000000);
1096                         evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1097                         evo_data(push, 0x00000000);
1098                         evo_data(push, 0x00000000);
1099                         evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
1100                         evo_data(push, mast->base.vram.handle);
1101                         evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
1102                         evo_data(push, 0xffffff00);
1103                 }
1104
1105                 evo_kick(push, mast);
1106         }
1107
1108         nv50_crtc_cursor_show_hide(nv_crtc, true, true);
1109         nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
1110 }
1111
1112 static bool
1113 nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1114                      struct drm_display_mode *adjusted_mode)
1115 {
1116         drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
1117         return true;
1118 }
1119
1120 static int
1121 nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
1122 {
1123         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb);
1124         struct nv50_head *head = nv50_head(crtc);
1125         int ret;
1126
1127         ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM, true);
1128         if (ret == 0) {
1129                 if (head->image)
1130                         nouveau_bo_unpin(head->image);
1131                 nouveau_bo_ref(nvfb->nvbo, &head->image);
1132         }
1133
1134         return ret;
1135 }
1136
1137 static int
1138 nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
1139                    struct drm_display_mode *mode, int x, int y,
1140                    struct drm_framebuffer *old_fb)
1141 {
1142         struct nv50_mast *mast = nv50_mast(crtc->dev);
1143         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1144         struct nouveau_connector *nv_connector;
1145         u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
1146         u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
1147         u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
1148         u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
1149         u32 vblan2e = 0, vblan2s = 1, vblankus = 0;
1150         u32 *push;
1151         int ret;
1152
1153         hactive = mode->htotal;
1154         hsynce  = mode->hsync_end - mode->hsync_start - 1;
1155         hbackp  = mode->htotal - mode->hsync_end;
1156         hblanke = hsynce + hbackp;
1157         hfrontp = mode->hsync_start - mode->hdisplay;
1158         hblanks = mode->htotal - hfrontp - 1;
1159
1160         vactive = mode->vtotal * vscan / ilace;
1161         vsynce  = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
1162         vbackp  = (mode->vtotal - mode->vsync_end) * vscan / ilace;
1163         vblanke = vsynce + vbackp;
1164         vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
1165         vblanks = vactive - vfrontp - 1;
1166         /* XXX: Safe underestimate, even "0" works */
1167         vblankus = (vactive - mode->vdisplay - 2) * hactive;
1168         vblankus *= 1000;
1169         vblankus /= mode->clock;
1170
1171         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1172                 vblan2e = vactive + vsynce + vbackp;
1173                 vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
1174                 vactive = (vactive * 2) + 1;
1175         }
1176
1177         ret = nv50_crtc_swap_fbs(crtc, old_fb);
1178         if (ret)
1179                 return ret;
1180
1181         push = evo_wait(mast, 64);
1182         if (push) {
1183                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1184                         evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2);
1185                         evo_data(push, 0x00800000 | mode->clock);
1186                         evo_data(push, (ilace == 2) ? 2 : 0);
1187                         evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6);
1188                         evo_data(push, 0x00000000);
1189                         evo_data(push, (vactive << 16) | hactive);
1190                         evo_data(push, ( vsynce << 16) | hsynce);
1191                         evo_data(push, (vblanke << 16) | hblanke);
1192                         evo_data(push, (vblanks << 16) | hblanks);
1193                         evo_data(push, (vblan2e << 16) | vblan2s);
1194                         evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1);
1195                         evo_data(push, 0x00000000);
1196                         evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2);
1197                         evo_data(push, 0x00000311);
1198                         evo_data(push, 0x00000100);
1199                 } else {
1200                         evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6);
1201                         evo_data(push, 0x00000000);
1202                         evo_data(push, (vactive << 16) | hactive);
1203                         evo_data(push, ( vsynce << 16) | hsynce);
1204                         evo_data(push, (vblanke << 16) | hblanke);
1205                         evo_data(push, (vblanks << 16) | hblanks);
1206                         evo_data(push, (vblan2e << 16) | vblan2s);
1207                         evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
1208                         evo_data(push, 0x00000000); /* ??? */
1209                         evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
1210                         evo_data(push, mode->clock * 1000);
1211                         evo_data(push, 0x00200000); /* ??? */
1212                         evo_data(push, mode->clock * 1000);
1213                         evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
1214                         evo_data(push, 0x00000311);
1215                         evo_data(push, 0x00000100);
1216                 }
1217
1218                 evo_kick(push, mast);
1219         }
1220
1221         nv_connector = nouveau_crtc_connector_get(nv_crtc);
1222         nv50_crtc_set_dither(nv_crtc, false);
1223         nv50_crtc_set_scale(nv_crtc, false);
1224
1225         /* G94 only accepts this after setting scale */
1226         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA)
1227                 nv50_crtc_set_raster_vblank_dmi(nv_crtc, vblankus);
1228
1229         nv50_crtc_set_color_vibrance(nv_crtc, false);
1230         nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, false);
1231         return 0;
1232 }
1233
1234 static int
1235 nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
1236                         struct drm_framebuffer *old_fb)
1237 {
1238         struct nouveau_drm *drm = nouveau_drm(crtc->dev);
1239         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1240         int ret;
1241
1242         if (!crtc->primary->fb) {
1243                 NV_DEBUG(drm, "No FB bound\n");
1244                 return 0;
1245         }
1246
1247         ret = nv50_crtc_swap_fbs(crtc, old_fb);
1248         if (ret)
1249                 return ret;
1250
1251         nv50_display_flip_stop(crtc);
1252         nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, true);
1253         nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
1254         return 0;
1255 }
1256
1257 static int
1258 nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
1259                                struct drm_framebuffer *fb, int x, int y,
1260                                enum mode_set_atomic state)
1261 {
1262         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1263         nv50_display_flip_stop(crtc);
1264         nv50_crtc_set_image(nv_crtc, fb, x, y, true);
1265         return 0;
1266 }
1267
1268 static void
1269 nv50_crtc_lut_load(struct drm_crtc *crtc)
1270 {
1271         struct nv50_disp *disp = nv50_disp(crtc->dev);
1272         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1273         void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
1274         int i;
1275
1276         for (i = 0; i < 256; i++) {
1277                 u16 r = nv_crtc->lut.r[i] >> 2;
1278                 u16 g = nv_crtc->lut.g[i] >> 2;
1279                 u16 b = nv_crtc->lut.b[i] >> 2;
1280
1281                 if (disp->disp->oclass < GF110_DISP) {
1282                         writew(r + 0x0000, lut + (i * 0x08) + 0);
1283                         writew(g + 0x0000, lut + (i * 0x08) + 2);
1284                         writew(b + 0x0000, lut + (i * 0x08) + 4);
1285                 } else {
1286                         writew(r + 0x6000, lut + (i * 0x20) + 0);
1287                         writew(g + 0x6000, lut + (i * 0x20) + 2);
1288                         writew(b + 0x6000, lut + (i * 0x20) + 4);
1289                 }
1290         }
1291 }
1292
1293 static void
1294 nv50_crtc_disable(struct drm_crtc *crtc)
1295 {
1296         struct nv50_head *head = nv50_head(crtc);
1297         evo_sync(crtc->dev);
1298         if (head->image)
1299                 nouveau_bo_unpin(head->image);
1300         nouveau_bo_ref(NULL, &head->image);
1301 }
1302
1303 static int
1304 nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
1305                      uint32_t handle, uint32_t width, uint32_t height)
1306 {
1307         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1308         struct drm_gem_object *gem = NULL;
1309         struct nouveau_bo *nvbo = NULL;
1310         int ret = 0;
1311
1312         if (handle) {
1313                 if (width != 64 || height != 64)
1314                         return -EINVAL;
1315
1316                 gem = drm_gem_object_lookup(file_priv, handle);
1317                 if (unlikely(!gem))
1318                         return -ENOENT;
1319                 nvbo = nouveau_gem_object(gem);
1320
1321                 ret = nouveau_bo_pin(nvbo, TTM_PL_FLAG_VRAM, true);
1322         }
1323
1324         if (ret == 0) {
1325                 if (nv_crtc->cursor.nvbo)
1326                         nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1327                 nouveau_bo_ref(nvbo, &nv_crtc->cursor.nvbo);
1328         }
1329         drm_gem_object_unreference_unlocked(gem);
1330
1331         nv50_crtc_cursor_show_hide(nv_crtc, true, true);
1332         return ret;
1333 }
1334
1335 static int
1336 nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1337 {
1338         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1339         struct nv50_curs *curs = nv50_curs(crtc);
1340         struct nv50_chan *chan = nv50_chan(curs);
1341         nvif_wr32(&chan->user, 0x0084, (y << 16) | (x & 0xffff));
1342         nvif_wr32(&chan->user, 0x0080, 0x00000000);
1343
1344         nv_crtc->cursor_saved_x = x;
1345         nv_crtc->cursor_saved_y = y;
1346         return 0;
1347 }
1348
1349 static int
1350 nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
1351                     uint32_t size)
1352 {
1353         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1354         u32 i;
1355
1356         for (i = 0; i < size; i++) {
1357                 nv_crtc->lut.r[i] = r[i];
1358                 nv_crtc->lut.g[i] = g[i];
1359                 nv_crtc->lut.b[i] = b[i];
1360         }
1361
1362         nv50_crtc_lut_load(crtc);
1363
1364         return 0;
1365 }
1366
1367 static void
1368 nv50_crtc_cursor_restore(struct nouveau_crtc *nv_crtc, int x, int y)
1369 {
1370         nv50_crtc_cursor_move(&nv_crtc->base, x, y);
1371
1372         nv50_crtc_cursor_show_hide(nv_crtc, true, true);
1373 }
1374
1375 static void
1376 nv50_crtc_destroy(struct drm_crtc *crtc)
1377 {
1378         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1379         struct nv50_disp *disp = nv50_disp(crtc->dev);
1380         struct nv50_head *head = nv50_head(crtc);
1381         struct nv50_fbdma *fbdma;
1382
1383         list_for_each_entry(fbdma, &disp->fbdma, head) {
1384                 nvif_object_fini(&fbdma->base[nv_crtc->index]);
1385         }
1386
1387         nv50_dmac_destroy(&head->ovly.base, disp->disp);
1388         nv50_pioc_destroy(&head->oimm.base);
1389         nv50_dmac_destroy(&head->sync.base, disp->disp);
1390         nv50_pioc_destroy(&head->curs.base);
1391
1392         /*XXX: this shouldn't be necessary, but the core doesn't call
1393          *     disconnect() during the cleanup paths
1394          */
1395         if (head->image)
1396                 nouveau_bo_unpin(head->image);
1397         nouveau_bo_ref(NULL, &head->image);
1398
1399         /*XXX: ditto */
1400         if (nv_crtc->cursor.nvbo)
1401                 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1402         nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
1403
1404         nouveau_bo_unmap(nv_crtc->lut.nvbo);
1405         if (nv_crtc->lut.nvbo)
1406                 nouveau_bo_unpin(nv_crtc->lut.nvbo);
1407         nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
1408
1409         drm_crtc_cleanup(crtc);
1410         kfree(crtc);
1411 }
1412
1413 static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = {
1414         .dpms = nv50_crtc_dpms,
1415         .prepare = nv50_crtc_prepare,
1416         .commit = nv50_crtc_commit,
1417         .mode_fixup = nv50_crtc_mode_fixup,
1418         .mode_set = nv50_crtc_mode_set,
1419         .mode_set_base = nv50_crtc_mode_set_base,
1420         .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
1421         .load_lut = nv50_crtc_lut_load,
1422         .disable = nv50_crtc_disable,
1423 };
1424
1425 static const struct drm_crtc_funcs nv50_crtc_func = {
1426         .cursor_set = nv50_crtc_cursor_set,
1427         .cursor_move = nv50_crtc_cursor_move,
1428         .gamma_set = nv50_crtc_gamma_set,
1429         .set_config = nouveau_crtc_set_config,
1430         .destroy = nv50_crtc_destroy,
1431         .page_flip = nouveau_crtc_page_flip,
1432 };
1433
1434 static int
1435 nv50_crtc_create(struct drm_device *dev, int index)
1436 {
1437         struct nouveau_drm *drm = nouveau_drm(dev);
1438         struct nvif_device *device = &drm->device;
1439         struct nv50_disp *disp = nv50_disp(dev);
1440         struct nv50_head *head;
1441         struct drm_crtc *crtc;
1442         int ret, i;
1443
1444         head = kzalloc(sizeof(*head), GFP_KERNEL);
1445         if (!head)
1446                 return -ENOMEM;
1447
1448         head->base.index = index;
1449         head->base.color_vibrance = 50;
1450         head->base.vibrant_hue = 0;
1451         head->base.cursor.set_pos = nv50_crtc_cursor_restore;
1452         for (i = 0; i < 256; i++) {
1453                 head->base.lut.r[i] = i << 8;
1454                 head->base.lut.g[i] = i << 8;
1455                 head->base.lut.b[i] = i << 8;
1456         }
1457
1458         crtc = &head->base.base;
1459         drm_crtc_init(dev, crtc, &nv50_crtc_func);
1460         drm_crtc_helper_add(crtc, &nv50_crtc_hfunc);
1461         drm_mode_crtc_set_gamma_size(crtc, 256);
1462
1463         ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
1464                              0, 0x0000, NULL, NULL, &head->base.lut.nvbo);
1465         if (!ret) {
1466                 ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM, true);
1467                 if (!ret) {
1468                         ret = nouveau_bo_map(head->base.lut.nvbo);
1469                         if (ret)
1470                                 nouveau_bo_unpin(head->base.lut.nvbo);
1471                 }
1472                 if (ret)
1473                         nouveau_bo_ref(NULL, &head->base.lut.nvbo);
1474         }
1475
1476         if (ret)
1477                 goto out;
1478
1479         /* allocate cursor resources */
1480         ret = nv50_curs_create(device, disp->disp, index, &head->curs);
1481         if (ret)
1482                 goto out;
1483
1484         /* allocate page flip / sync resources */
1485         ret = nv50_base_create(device, disp->disp, index, disp->sync->bo.offset,
1486                                &head->sync);
1487         if (ret)
1488                 goto out;
1489
1490         head->sync.addr = EVO_FLIP_SEM0(index);
1491         head->sync.data = 0x00000000;
1492
1493         /* allocate overlay resources */
1494         ret = nv50_oimm_create(device, disp->disp, index, &head->oimm);
1495         if (ret)
1496                 goto out;
1497
1498         ret = nv50_ovly_create(device, disp->disp, index, disp->sync->bo.offset,
1499                                &head->ovly);
1500         if (ret)
1501                 goto out;
1502
1503 out:
1504         if (ret)
1505                 nv50_crtc_destroy(crtc);
1506         return ret;
1507 }
1508
1509 /******************************************************************************
1510  * Encoder helpers
1511  *****************************************************************************/
1512 static bool
1513 nv50_encoder_mode_fixup(struct drm_encoder *encoder,
1514                         const struct drm_display_mode *mode,
1515                         struct drm_display_mode *adjusted_mode)
1516 {
1517         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1518         struct nouveau_connector *nv_connector;
1519
1520         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1521         if (nv_connector && nv_connector->native_mode) {
1522                 nv_connector->scaling_full = false;
1523                 if (nv_connector->scaling_mode == DRM_MODE_SCALE_NONE) {
1524                         switch (nv_connector->type) {
1525                         case DCB_CONNECTOR_LVDS:
1526                         case DCB_CONNECTOR_LVDS_SPWG:
1527                         case DCB_CONNECTOR_eDP:
1528                                 /* force use of scaler for non-edid modes */
1529                                 if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
1530                                         return true;
1531                                 nv_connector->scaling_full = true;
1532                                 break;
1533                         default:
1534                                 return true;
1535                         }
1536                 }
1537
1538                 drm_mode_copy(adjusted_mode, nv_connector->native_mode);
1539         }
1540
1541         return true;
1542 }
1543
1544 /******************************************************************************
1545  * DAC
1546  *****************************************************************************/
1547 static void
1548 nv50_dac_dpms(struct drm_encoder *encoder, int mode)
1549 {
1550         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1551         struct nv50_disp *disp = nv50_disp(encoder->dev);
1552         struct {
1553                 struct nv50_disp_mthd_v1 base;
1554                 struct nv50_disp_dac_pwr_v0 pwr;
1555         } args = {
1556                 .base.version = 1,
1557                 .base.method = NV50_DISP_MTHD_V1_DAC_PWR,
1558                 .base.hasht  = nv_encoder->dcb->hasht,
1559                 .base.hashm  = nv_encoder->dcb->hashm,
1560                 .pwr.state = 1,
1561                 .pwr.data  = 1,
1562                 .pwr.vsync = (mode != DRM_MODE_DPMS_SUSPEND &&
1563                               mode != DRM_MODE_DPMS_OFF),
1564                 .pwr.hsync = (mode != DRM_MODE_DPMS_STANDBY &&
1565                               mode != DRM_MODE_DPMS_OFF),
1566         };
1567
1568         nvif_mthd(disp->disp, 0, &args, sizeof(args));
1569 }
1570
1571 static void
1572 nv50_dac_commit(struct drm_encoder *encoder)
1573 {
1574 }
1575
1576 static void
1577 nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1578                   struct drm_display_mode *adjusted_mode)
1579 {
1580         struct nv50_mast *mast = nv50_mast(encoder->dev);
1581         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1582         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1583         u32 *push;
1584
1585         nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1586
1587         push = evo_wait(mast, 8);
1588         if (push) {
1589                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1590                         u32 syncs = 0x00000000;
1591
1592                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1593                                 syncs |= 0x00000001;
1594                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1595                                 syncs |= 0x00000002;
1596
1597                         evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
1598                         evo_data(push, 1 << nv_crtc->index);
1599                         evo_data(push, syncs);
1600                 } else {
1601                         u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1602                         u32 syncs = 0x00000001;
1603
1604                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1605                                 syncs |= 0x00000008;
1606                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1607                                 syncs |= 0x00000010;
1608
1609                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1610                                 magic |= 0x00000001;
1611
1612                         evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1613                         evo_data(push, syncs);
1614                         evo_data(push, magic);
1615                         evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
1616                         evo_data(push, 1 << nv_crtc->index);
1617                 }
1618
1619                 evo_kick(push, mast);
1620         }
1621
1622         nv_encoder->crtc = encoder->crtc;
1623 }
1624
1625 static void
1626 nv50_dac_disconnect(struct drm_encoder *encoder)
1627 {
1628         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1629         struct nv50_mast *mast = nv50_mast(encoder->dev);
1630         const int or = nv_encoder->or;
1631         u32 *push;
1632
1633         if (nv_encoder->crtc) {
1634                 nv50_crtc_prepare(nv_encoder->crtc);
1635
1636                 push = evo_wait(mast, 4);
1637                 if (push) {
1638                         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1639                                 evo_mthd(push, 0x0400 + (or * 0x080), 1);
1640                                 evo_data(push, 0x00000000);
1641                         } else {
1642                                 evo_mthd(push, 0x0180 + (or * 0x020), 1);
1643                                 evo_data(push, 0x00000000);
1644                         }
1645                         evo_kick(push, mast);
1646                 }
1647         }
1648
1649         nv_encoder->crtc = NULL;
1650 }
1651
1652 static enum drm_connector_status
1653 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1654 {
1655         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1656         struct nv50_disp *disp = nv50_disp(encoder->dev);
1657         struct {
1658                 struct nv50_disp_mthd_v1 base;
1659                 struct nv50_disp_dac_load_v0 load;
1660         } args = {
1661                 .base.version = 1,
1662                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
1663                 .base.hasht  = nv_encoder->dcb->hasht,
1664                 .base.hashm  = nv_encoder->dcb->hashm,
1665         };
1666         int ret;
1667
1668         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
1669         if (args.load.data == 0)
1670                 args.load.data = 340;
1671
1672         ret = nvif_mthd(disp->disp, 0, &args, sizeof(args));
1673         if (ret || !args.load.load)
1674                 return connector_status_disconnected;
1675
1676         return connector_status_connected;
1677 }
1678
1679 static void
1680 nv50_dac_destroy(struct drm_encoder *encoder)
1681 {
1682         drm_encoder_cleanup(encoder);
1683         kfree(encoder);
1684 }
1685
1686 static const struct drm_encoder_helper_funcs nv50_dac_hfunc = {
1687         .dpms = nv50_dac_dpms,
1688         .mode_fixup = nv50_encoder_mode_fixup,
1689         .prepare = nv50_dac_disconnect,
1690         .commit = nv50_dac_commit,
1691         .mode_set = nv50_dac_mode_set,
1692         .disable = nv50_dac_disconnect,
1693         .get_crtc = nv50_display_crtc_get,
1694         .detect = nv50_dac_detect
1695 };
1696
1697 static const struct drm_encoder_funcs nv50_dac_func = {
1698         .destroy = nv50_dac_destroy,
1699 };
1700
1701 static int
1702 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
1703 {
1704         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1705         struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
1706         struct nvkm_i2c_bus *bus;
1707         struct nouveau_encoder *nv_encoder;
1708         struct drm_encoder *encoder;
1709         int type = DRM_MODE_ENCODER_DAC;
1710
1711         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1712         if (!nv_encoder)
1713                 return -ENOMEM;
1714         nv_encoder->dcb = dcbe;
1715         nv_encoder->or = ffs(dcbe->or) - 1;
1716
1717         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1718         if (bus)
1719                 nv_encoder->i2c = &bus->i2c;
1720
1721         encoder = to_drm_encoder(nv_encoder);
1722         encoder->possible_crtcs = dcbe->heads;
1723         encoder->possible_clones = 0;
1724         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
1725                          "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
1726         drm_encoder_helper_add(encoder, &nv50_dac_hfunc);
1727
1728         drm_mode_connector_attach_encoder(connector, encoder);
1729         return 0;
1730 }
1731
1732 /******************************************************************************
1733  * Audio
1734  *****************************************************************************/
1735 static void
1736 nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1737 {
1738         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1739         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1740         struct nouveau_connector *nv_connector;
1741         struct nv50_disp *disp = nv50_disp(encoder->dev);
1742         struct __packed {
1743                 struct {
1744                         struct nv50_disp_mthd_v1 mthd;
1745                         struct nv50_disp_sor_hda_eld_v0 eld;
1746                 } base;
1747                 u8 data[sizeof(nv_connector->base.eld)];
1748         } args = {
1749                 .base.mthd.version = 1,
1750                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
1751                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
1752                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
1753                                      (0x0100 << nv_crtc->index),
1754         };
1755
1756         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1757         if (!drm_detect_monitor_audio(nv_connector->edid))
1758                 return;
1759
1760         drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
1761         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
1762
1763         nvif_mthd(disp->disp, 0, &args,
1764                   sizeof(args.base) + drm_eld_size(args.data));
1765 }
1766
1767 static void
1768 nv50_audio_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
1769 {
1770         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1771         struct nv50_disp *disp = nv50_disp(encoder->dev);
1772         struct {
1773                 struct nv50_disp_mthd_v1 base;
1774                 struct nv50_disp_sor_hda_eld_v0 eld;
1775         } args = {
1776                 .base.version = 1,
1777                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
1778                 .base.hasht   = nv_encoder->dcb->hasht,
1779                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
1780                                 (0x0100 << nv_crtc->index),
1781         };
1782
1783         nvif_mthd(disp->disp, 0, &args, sizeof(args));
1784 }
1785
1786 /******************************************************************************
1787  * HDMI
1788  *****************************************************************************/
1789 static void
1790 nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1791 {
1792         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1793         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1794         struct nv50_disp *disp = nv50_disp(encoder->dev);
1795         struct {
1796                 struct nv50_disp_mthd_v1 base;
1797                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
1798         } args = {
1799                 .base.version = 1,
1800                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
1801                 .base.hasht  = nv_encoder->dcb->hasht,
1802                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
1803                                (0x0100 << nv_crtc->index),
1804                 .pwr.state = 1,
1805                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
1806         };
1807         struct nouveau_connector *nv_connector;
1808         u32 max_ac_packet;
1809
1810         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1811         if (!drm_detect_hdmi_monitor(nv_connector->edid))
1812                 return;
1813
1814         max_ac_packet  = mode->htotal - mode->hdisplay;
1815         max_ac_packet -= args.pwr.rekey;
1816         max_ac_packet -= 18; /* constant from tegra */
1817         args.pwr.max_ac_packet = max_ac_packet / 32;
1818
1819         nvif_mthd(disp->disp, 0, &args, sizeof(args));
1820         nv50_audio_mode_set(encoder, mode);
1821 }
1822
1823 static void
1824 nv50_hdmi_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
1825 {
1826         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1827         struct nv50_disp *disp = nv50_disp(encoder->dev);
1828         struct {
1829                 struct nv50_disp_mthd_v1 base;
1830                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
1831         } args = {
1832                 .base.version = 1,
1833                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
1834                 .base.hasht  = nv_encoder->dcb->hasht,
1835                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
1836                                (0x0100 << nv_crtc->index),
1837         };
1838
1839         nvif_mthd(disp->disp, 0, &args, sizeof(args));
1840 }
1841
1842 /******************************************************************************
1843  * MST
1844  *****************************************************************************/
1845 struct nv50_mstm {
1846         struct nouveau_encoder *outp;
1847
1848         struct drm_dp_mst_topology_mgr mgr;
1849 };
1850
1851 static int
1852 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
1853 {
1854         struct nouveau_encoder *outp = mstm->outp;
1855         struct {
1856                 struct nv50_disp_mthd_v1 base;
1857                 struct nv50_disp_sor_dp_mst_link_v0 mst;
1858         } args = {
1859                 .base.version = 1,
1860                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
1861                 .base.hasht = outp->dcb->hasht,
1862                 .base.hashm = outp->dcb->hashm,
1863                 .mst.state = state,
1864         };
1865         struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1866         struct nvif_object *disp = &drm->display->disp;
1867         int ret;
1868
1869         if (dpcd >= 0x12) {
1870                 ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CTRL, &dpcd);
1871                 if (ret < 0)
1872                         return ret;
1873
1874                 dpcd &= ~DP_MST_EN;
1875                 if (state)
1876                         dpcd |= DP_MST_EN;
1877
1878                 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, dpcd);
1879                 if (ret < 0)
1880                         return ret;
1881         }
1882
1883         return nvif_mthd(disp, 0, &args, sizeof(args));
1884 }
1885
1886 int
1887 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
1888 {
1889         int ret, state = 0;
1890
1891         if (!mstm)
1892                 return 0;
1893
1894         if (dpcd[0] >= 0x12 && allow) {
1895                 ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CAP, &dpcd[1]);
1896                 if (ret < 0)
1897                         return ret;
1898
1899                 state = dpcd[1] & DP_MST_CAP;
1900         }
1901
1902         ret = nv50_mstm_enable(mstm, dpcd[0], state);
1903         if (ret)
1904                 return ret;
1905
1906         ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, state);
1907         if (ret)
1908                 return nv50_mstm_enable(mstm, dpcd[0], 0);
1909
1910         return mstm->mgr.mst_state;
1911 }
1912
1913 static void
1914 nv50_mstm_del(struct nv50_mstm **pmstm)
1915 {
1916         struct nv50_mstm *mstm = *pmstm;
1917         if (mstm) {
1918                 kfree(*pmstm);
1919                 *pmstm = NULL;
1920         }
1921 }
1922
1923 static int
1924 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1925               int conn_base_id, struct nv50_mstm **pmstm)
1926 {
1927         const int max_payloads = hweight8(outp->dcb->heads);
1928         struct drm_device *dev = outp->base.base.dev;
1929         struct nv50_mstm *mstm;
1930         int ret;
1931
1932         if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1933                 return -ENOMEM;
1934         mstm->outp = outp;
1935
1936         ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev->dev, aux, aux_max,
1937                                            max_payloads, conn_base_id);
1938         if (ret)
1939                 return ret;
1940
1941         return 0;
1942 }
1943
1944 /******************************************************************************
1945  * SOR
1946  *****************************************************************************/
1947 static void
1948 nv50_sor_dpms(struct drm_encoder *encoder, int mode)
1949 {
1950         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1951         struct nv50_disp *disp = nv50_disp(encoder->dev);
1952         struct {
1953                 struct nv50_disp_mthd_v1 base;
1954                 struct nv50_disp_sor_pwr_v0 pwr;
1955         } args = {
1956                 .base.version = 1,
1957                 .base.method = NV50_DISP_MTHD_V1_SOR_PWR,
1958                 .base.hasht  = nv_encoder->dcb->hasht,
1959                 .base.hashm  = nv_encoder->dcb->hashm,
1960                 .pwr.state = mode == DRM_MODE_DPMS_ON,
1961         };
1962         struct {
1963                 struct nv50_disp_mthd_v1 base;
1964                 struct nv50_disp_sor_dp_pwr_v0 pwr;
1965         } link = {
1966                 .base.version = 1,
1967                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_PWR,
1968                 .base.hasht  = nv_encoder->dcb->hasht,
1969                 .base.hashm  = nv_encoder->dcb->hashm,
1970                 .pwr.state = mode == DRM_MODE_DPMS_ON,
1971         };
1972         struct drm_device *dev = encoder->dev;
1973         struct drm_encoder *partner;
1974
1975         nv_encoder->last_dpms = mode;
1976
1977         list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
1978                 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
1979
1980                 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
1981                         continue;
1982
1983                 if (nv_partner != nv_encoder &&
1984                     nv_partner->dcb->or == nv_encoder->dcb->or) {
1985                         if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
1986                                 return;
1987                         break;
1988                 }
1989         }
1990
1991         if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
1992                 args.pwr.state = 1;
1993                 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1994                 nvif_mthd(disp->disp, 0, &link, sizeof(link));
1995         } else {
1996                 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1997         }
1998 }
1999
2000 static void
2001 nv50_sor_ctrl(struct nouveau_encoder *nv_encoder, u32 mask, u32 data)
2002 {
2003         struct nv50_mast *mast = nv50_mast(nv_encoder->base.base.dev);
2004         u32 temp = (nv_encoder->ctrl & ~mask) | (data & mask), *push;
2005         if (temp != nv_encoder->ctrl && (push = evo_wait(mast, 2))) {
2006                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2007                         evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1);
2008                         evo_data(push, (nv_encoder->ctrl = temp));
2009                 } else {
2010                         evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
2011                         evo_data(push, (nv_encoder->ctrl = temp));
2012                 }
2013                 evo_kick(push, mast);
2014         }
2015 }
2016
2017 static void
2018 nv50_sor_disconnect(struct drm_encoder *encoder)
2019 {
2020         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2021         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
2022
2023         nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
2024         nv_encoder->crtc = NULL;
2025
2026         if (nv_crtc) {
2027                 nv50_crtc_prepare(&nv_crtc->base);
2028                 nv50_sor_ctrl(nv_encoder, 1 << nv_crtc->index, 0);
2029                 nv50_audio_disconnect(encoder, nv_crtc);
2030                 nv50_hdmi_disconnect(&nv_encoder->base.base, nv_crtc);
2031         }
2032 }
2033
2034 static void
2035 nv50_sor_commit(struct drm_encoder *encoder)
2036 {
2037 }
2038
2039 static void
2040 nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
2041                   struct drm_display_mode *mode)
2042 {
2043         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2044         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2045         struct {
2046                 struct nv50_disp_mthd_v1 base;
2047                 struct nv50_disp_sor_lvds_script_v0 lvds;
2048         } lvds = {
2049                 .base.version = 1,
2050                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
2051                 .base.hasht   = nv_encoder->dcb->hasht,
2052                 .base.hashm   = nv_encoder->dcb->hashm,
2053         };
2054         struct nv50_disp *disp = nv50_disp(encoder->dev);
2055         struct nv50_mast *mast = nv50_mast(encoder->dev);
2056         struct drm_device *dev = encoder->dev;
2057         struct nouveau_drm *drm = nouveau_drm(dev);
2058         struct nouveau_connector *nv_connector;
2059         struct nvbios *bios = &drm->vbios;
2060         u32 mask, ctrl;
2061         u8 owner = 1 << nv_crtc->index;
2062         u8 proto = 0xf;
2063         u8 depth = 0x0;
2064
2065         nv_connector = nouveau_encoder_connector_get(nv_encoder);
2066         nv_encoder->crtc = encoder->crtc;
2067
2068         switch (nv_encoder->dcb->type) {
2069         case DCB_OUTPUT_TMDS:
2070                 if (nv_encoder->dcb->sorconf.link & 1) {
2071                         proto = 0x1;
2072                         /* Only enable dual-link if:
2073                          *  - Need to (i.e. rate > 165MHz)
2074                          *  - DCB says we can
2075                          *  - Not an HDMI monitor, since there's no dual-link
2076                          *    on HDMI.
2077                          */
2078                         if (mode->clock >= 165000 &&
2079                             nv_encoder->dcb->duallink_possible &&
2080                             !drm_detect_hdmi_monitor(nv_connector->edid))
2081                                 proto |= 0x4;
2082                 } else {
2083                         proto = 0x2;
2084                 }
2085
2086                 nv50_hdmi_mode_set(&nv_encoder->base.base, mode);
2087                 break;
2088         case DCB_OUTPUT_LVDS:
2089                 proto = 0x0;
2090
2091                 if (bios->fp_no_ddc) {
2092                         if (bios->fp.dual_link)
2093                                 lvds.lvds.script |= 0x0100;
2094                         if (bios->fp.if_is_24bit)
2095                                 lvds.lvds.script |= 0x0200;
2096                 } else {
2097                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
2098                                 if (((u8 *)nv_connector->edid)[121] == 2)
2099                                         lvds.lvds.script |= 0x0100;
2100                         } else
2101                         if (mode->clock >= bios->fp.duallink_transition_clk) {
2102                                 lvds.lvds.script |= 0x0100;
2103                         }
2104
2105                         if (lvds.lvds.script & 0x0100) {
2106                                 if (bios->fp.strapless_is_24bit & 2)
2107                                         lvds.lvds.script |= 0x0200;
2108                         } else {
2109                                 if (bios->fp.strapless_is_24bit & 1)
2110                                         lvds.lvds.script |= 0x0200;
2111                         }
2112
2113                         if (nv_connector->base.display_info.bpc == 8)
2114                                 lvds.lvds.script |= 0x0200;
2115                 }
2116
2117                 nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds));
2118                 break;
2119         case DCB_OUTPUT_DP:
2120                 if (nv_connector->base.display_info.bpc == 6) {
2121                         nv_encoder->dp.datarate = mode->clock * 18 / 8;
2122                         depth = 0x2;
2123                 } else
2124                 if (nv_connector->base.display_info.bpc == 8) {
2125                         nv_encoder->dp.datarate = mode->clock * 24 / 8;
2126                         depth = 0x5;
2127                 } else {
2128                         nv_encoder->dp.datarate = mode->clock * 30 / 8;
2129                         depth = 0x6;
2130                 }
2131
2132                 if (nv_encoder->dcb->sorconf.link & 1)
2133                         proto = 0x8;
2134                 else
2135                         proto = 0x9;
2136                 nv50_audio_mode_set(encoder, mode);
2137                 break;
2138         default:
2139                 BUG_ON(1);
2140                 break;
2141         }
2142
2143         nv50_sor_dpms(&nv_encoder->base.base, DRM_MODE_DPMS_ON);
2144
2145         if (nv50_vers(mast) >= GF110_DISP) {
2146                 u32 *push = evo_wait(mast, 3);
2147                 if (push) {
2148                         u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
2149                         u32 syncs = 0x00000001;
2150
2151                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2152                                 syncs |= 0x00000008;
2153                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2154                                 syncs |= 0x00000010;
2155
2156                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2157                                 magic |= 0x00000001;
2158
2159                         evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
2160                         evo_data(push, syncs | (depth << 6));
2161                         evo_data(push, magic);
2162                         evo_kick(push, mast);
2163                 }
2164
2165                 ctrl = proto << 8;
2166                 mask = 0x00000f00;
2167         } else {
2168                 ctrl = (depth << 16) | (proto << 8);
2169                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2170                         ctrl |= 0x00001000;
2171                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2172                         ctrl |= 0x00002000;
2173                 mask = 0x000f3f00;
2174         }
2175
2176         nv50_sor_ctrl(nv_encoder, mask | owner, ctrl | owner);
2177 }
2178
2179 static void
2180 nv50_sor_destroy(struct drm_encoder *encoder)
2181 {
2182         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2183         nv50_mstm_del(&nv_encoder->dp.mstm);
2184         drm_encoder_cleanup(encoder);
2185         kfree(encoder);
2186 }
2187
2188 static const struct drm_encoder_helper_funcs nv50_sor_hfunc = {
2189         .dpms = nv50_sor_dpms,
2190         .mode_fixup = nv50_encoder_mode_fixup,
2191         .prepare = nv50_sor_disconnect,
2192         .commit = nv50_sor_commit,
2193         .mode_set = nv50_sor_mode_set,
2194         .disable = nv50_sor_disconnect,
2195         .get_crtc = nv50_display_crtc_get,
2196 };
2197
2198 static const struct drm_encoder_funcs nv50_sor_func = {
2199         .destroy = nv50_sor_destroy,
2200 };
2201
2202 static int
2203 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
2204 {
2205         struct nouveau_connector *nv_connector = nouveau_connector(connector);
2206         struct nouveau_drm *drm = nouveau_drm(connector->dev);
2207         struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
2208         struct nouveau_encoder *nv_encoder;
2209         struct drm_encoder *encoder;
2210         int type, ret;
2211
2212         switch (dcbe->type) {
2213         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
2214         case DCB_OUTPUT_TMDS:
2215         case DCB_OUTPUT_DP:
2216         default:
2217                 type = DRM_MODE_ENCODER_TMDS;
2218                 break;
2219         }
2220
2221         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2222         if (!nv_encoder)
2223                 return -ENOMEM;
2224         nv_encoder->dcb = dcbe;
2225         nv_encoder->or = ffs(dcbe->or) - 1;
2226         nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
2227
2228         encoder = to_drm_encoder(nv_encoder);
2229         encoder->possible_crtcs = dcbe->heads;
2230         encoder->possible_clones = 0;
2231         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
2232                          "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
2233         drm_encoder_helper_add(encoder, &nv50_sor_hfunc);
2234
2235         drm_mode_connector_attach_encoder(connector, encoder);
2236
2237         if (dcbe->type == DCB_OUTPUT_DP) {
2238                 struct nvkm_i2c_aux *aux =
2239                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
2240                 if (aux) {
2241                         nv_encoder->i2c = &aux->i2c;
2242                         nv_encoder->aux = aux;
2243                 }
2244
2245                 /*TODO: Use DP Info Table to check for support. */
2246                 if (nv50_disp(encoder->dev)->disp->oclass >= GF110_DISP) {
2247                         ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
2248                                             nv_connector->base.base.id,
2249                                             &nv_encoder->dp.mstm);
2250                         if (ret)
2251                                 return ret;
2252                 }
2253         } else {
2254                 struct nvkm_i2c_bus *bus =
2255                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
2256                 if (bus)
2257                         nv_encoder->i2c = &bus->i2c;
2258         }
2259
2260         return 0;
2261 }
2262
2263 /******************************************************************************
2264  * PIOR
2265  *****************************************************************************/
2266
2267 static void
2268 nv50_pior_dpms(struct drm_encoder *encoder, int mode)
2269 {
2270         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2271         struct nv50_disp *disp = nv50_disp(encoder->dev);
2272         struct {
2273                 struct nv50_disp_mthd_v1 base;
2274                 struct nv50_disp_pior_pwr_v0 pwr;
2275         } args = {
2276                 .base.version = 1,
2277                 .base.method = NV50_DISP_MTHD_V1_PIOR_PWR,
2278                 .base.hasht  = nv_encoder->dcb->hasht,
2279                 .base.hashm  = nv_encoder->dcb->hashm,
2280                 .pwr.state = mode == DRM_MODE_DPMS_ON,
2281                 .pwr.type = nv_encoder->dcb->type,
2282         };
2283
2284         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2285 }
2286
2287 static bool
2288 nv50_pior_mode_fixup(struct drm_encoder *encoder,
2289                      const struct drm_display_mode *mode,
2290                      struct drm_display_mode *adjusted_mode)
2291 {
2292         if (!nv50_encoder_mode_fixup(encoder, mode, adjusted_mode))
2293                 return false;
2294         adjusted_mode->clock *= 2;
2295         return true;
2296 }
2297
2298 static void
2299 nv50_pior_commit(struct drm_encoder *encoder)
2300 {
2301 }
2302
2303 static void
2304 nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
2305                    struct drm_display_mode *adjusted_mode)
2306 {
2307         struct nv50_mast *mast = nv50_mast(encoder->dev);
2308         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2309         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2310         struct nouveau_connector *nv_connector;
2311         u8 owner = 1 << nv_crtc->index;
2312         u8 proto, depth;
2313         u32 *push;
2314
2315         nv_connector = nouveau_encoder_connector_get(nv_encoder);
2316         switch (nv_connector->base.display_info.bpc) {
2317         case 10: depth = 0x6; break;
2318         case  8: depth = 0x5; break;
2319         case  6: depth = 0x2; break;
2320         default: depth = 0x0; break;
2321         }
2322
2323         switch (nv_encoder->dcb->type) {
2324         case DCB_OUTPUT_TMDS:
2325         case DCB_OUTPUT_DP:
2326                 proto = 0x0;
2327                 break;
2328         default:
2329                 BUG_ON(1);
2330                 break;
2331         }
2332
2333         nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON);
2334
2335         push = evo_wait(mast, 8);
2336         if (push) {
2337                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2338                         u32 ctrl = (depth << 16) | (proto << 8) | owner;
2339                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2340                                 ctrl |= 0x00001000;
2341                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2342                                 ctrl |= 0x00002000;
2343                         evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
2344                         evo_data(push, ctrl);
2345                 }
2346
2347                 evo_kick(push, mast);
2348         }
2349
2350         nv_encoder->crtc = encoder->crtc;
2351 }
2352
2353 static void
2354 nv50_pior_disconnect(struct drm_encoder *encoder)
2355 {
2356         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2357         struct nv50_mast *mast = nv50_mast(encoder->dev);
2358         const int or = nv_encoder->or;
2359         u32 *push;
2360
2361         if (nv_encoder->crtc) {
2362                 nv50_crtc_prepare(nv_encoder->crtc);
2363
2364                 push = evo_wait(mast, 4);
2365                 if (push) {
2366                         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2367                                 evo_mthd(push, 0x0700 + (or * 0x040), 1);
2368                                 evo_data(push, 0x00000000);
2369                         }
2370                         evo_kick(push, mast);
2371                 }
2372         }
2373
2374         nv_encoder->crtc = NULL;
2375 }
2376
2377 static void
2378 nv50_pior_destroy(struct drm_encoder *encoder)
2379 {
2380         drm_encoder_cleanup(encoder);
2381         kfree(encoder);
2382 }
2383
2384 static const struct drm_encoder_helper_funcs nv50_pior_hfunc = {
2385         .dpms = nv50_pior_dpms,
2386         .mode_fixup = nv50_pior_mode_fixup,
2387         .prepare = nv50_pior_disconnect,
2388         .commit = nv50_pior_commit,
2389         .mode_set = nv50_pior_mode_set,
2390         .disable = nv50_pior_disconnect,
2391         .get_crtc = nv50_display_crtc_get,
2392 };
2393
2394 static const struct drm_encoder_funcs nv50_pior_func = {
2395         .destroy = nv50_pior_destroy,
2396 };
2397
2398 static int
2399 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
2400 {
2401         struct nouveau_drm *drm = nouveau_drm(connector->dev);
2402         struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
2403         struct nvkm_i2c_bus *bus = NULL;
2404         struct nvkm_i2c_aux *aux = NULL;
2405         struct i2c_adapter *ddc;
2406         struct nouveau_encoder *nv_encoder;
2407         struct drm_encoder *encoder;
2408         int type;
2409
2410         switch (dcbe->type) {
2411         case DCB_OUTPUT_TMDS:
2412                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
2413                 ddc  = bus ? &bus->i2c : NULL;
2414                 type = DRM_MODE_ENCODER_TMDS;
2415                 break;
2416         case DCB_OUTPUT_DP:
2417                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
2418                 ddc  = aux ? &aux->i2c : NULL;
2419                 type = DRM_MODE_ENCODER_TMDS;
2420                 break;
2421         default:
2422                 return -ENODEV;
2423         }
2424
2425         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2426         if (!nv_encoder)
2427                 return -ENOMEM;
2428         nv_encoder->dcb = dcbe;
2429         nv_encoder->or = ffs(dcbe->or) - 1;
2430         nv_encoder->i2c = ddc;
2431         nv_encoder->aux = aux;
2432
2433         encoder = to_drm_encoder(nv_encoder);
2434         encoder->possible_crtcs = dcbe->heads;
2435         encoder->possible_clones = 0;
2436         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
2437                          "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
2438         drm_encoder_helper_add(encoder, &nv50_pior_hfunc);
2439
2440         drm_mode_connector_attach_encoder(connector, encoder);
2441         return 0;
2442 }
2443
2444 /******************************************************************************
2445  * Framebuffer
2446  *****************************************************************************/
2447
2448 static void
2449 nv50_fbdma_fini(struct nv50_fbdma *fbdma)
2450 {
2451         int i;
2452         for (i = 0; i < ARRAY_SIZE(fbdma->base); i++)
2453                 nvif_object_fini(&fbdma->base[i]);
2454         nvif_object_fini(&fbdma->core);
2455         list_del(&fbdma->head);
2456         kfree(fbdma);
2457 }
2458
2459 static int
2460 nv50_fbdma_init(struct drm_device *dev, u32 name, u64 offset, u64 length, u8 kind)
2461 {
2462         struct nouveau_drm *drm = nouveau_drm(dev);
2463         struct nv50_disp *disp = nv50_disp(dev);
2464         struct nv50_mast *mast = nv50_mast(dev);
2465         struct __attribute__ ((packed)) {
2466                 struct nv_dma_v0 base;
2467                 union {
2468                         struct nv50_dma_v0 nv50;
2469                         struct gf100_dma_v0 gf100;
2470                         struct gf119_dma_v0 gf119;
2471                 };
2472         } args = {};
2473         struct nv50_fbdma *fbdma;
2474         struct drm_crtc *crtc;
2475         u32 size = sizeof(args.base);
2476         int ret;
2477
2478         list_for_each_entry(fbdma, &disp->fbdma, head) {
2479                 if (fbdma->core.handle == name)
2480                         return 0;
2481         }
2482
2483         fbdma = kzalloc(sizeof(*fbdma), GFP_KERNEL);
2484         if (!fbdma)
2485                 return -ENOMEM;
2486         list_add(&fbdma->head, &disp->fbdma);
2487
2488         args.base.target = NV_DMA_V0_TARGET_VRAM;
2489         args.base.access = NV_DMA_V0_ACCESS_RDWR;
2490         args.base.start = offset;
2491         args.base.limit = offset + length - 1;
2492
2493         if (drm->device.info.chipset < 0x80) {
2494                 args.nv50.part = NV50_DMA_V0_PART_256;
2495                 size += sizeof(args.nv50);
2496         } else
2497         if (drm->device.info.chipset < 0xc0) {
2498                 args.nv50.part = NV50_DMA_V0_PART_256;
2499                 args.nv50.kind = kind;
2500                 size += sizeof(args.nv50);
2501         } else
2502         if (drm->device.info.chipset < 0xd0) {
2503                 args.gf100.kind = kind;
2504                 size += sizeof(args.gf100);
2505         } else {
2506                 args.gf119.page = GF119_DMA_V0_PAGE_LP;
2507                 args.gf119.kind = kind;
2508                 size += sizeof(args.gf119);
2509         }
2510
2511         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2512                 struct nv50_head *head = nv50_head(crtc);
2513                 int ret = nvif_object_init(&head->sync.base.base.user, name,
2514                                            NV_DMA_IN_MEMORY, &args, size,
2515                                            &fbdma->base[head->base.index]);
2516                 if (ret) {
2517                         nv50_fbdma_fini(fbdma);
2518                         return ret;
2519                 }
2520         }
2521
2522         ret = nvif_object_init(&mast->base.base.user, name, NV_DMA_IN_MEMORY,
2523                                &args, size, &fbdma->core);
2524         if (ret) {
2525                 nv50_fbdma_fini(fbdma);
2526                 return ret;
2527         }
2528
2529         return 0;
2530 }
2531
2532 static void
2533 nv50_fb_dtor(struct drm_framebuffer *fb)
2534 {
2535 }
2536
2537 static int
2538 nv50_fb_ctor(struct drm_framebuffer *fb)
2539 {
2540         struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
2541         struct nouveau_drm *drm = nouveau_drm(fb->dev);
2542         struct nouveau_bo *nvbo = nv_fb->nvbo;
2543         struct nv50_disp *disp = nv50_disp(fb->dev);
2544         u8 kind = nouveau_bo_tile_layout(nvbo) >> 8;
2545         u8 tile = nvbo->tile_mode;
2546
2547         if (drm->device.info.chipset >= 0xc0)
2548                 tile >>= 4; /* yep.. */
2549
2550         switch (fb->depth) {
2551         case  8: nv_fb->r_format = 0x1e00; break;
2552         case 15: nv_fb->r_format = 0xe900; break;
2553         case 16: nv_fb->r_format = 0xe800; break;
2554         case 24:
2555         case 32: nv_fb->r_format = 0xcf00; break;
2556         case 30: nv_fb->r_format = 0xd100; break;
2557         default:
2558                  NV_ERROR(drm, "unknown depth %d\n", fb->depth);
2559                  return -EINVAL;
2560         }
2561
2562         if (disp->disp->oclass < G82_DISP) {
2563                 nv_fb->r_pitch   = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2564                                             (fb->pitches[0] | 0x00100000);
2565                 nv_fb->r_format |= kind << 16;
2566         } else
2567         if (disp->disp->oclass < GF110_DISP) {
2568                 nv_fb->r_pitch  = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2569                                            (fb->pitches[0] | 0x00100000);
2570         } else {
2571                 nv_fb->r_pitch  = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2572                                            (fb->pitches[0] | 0x01000000);
2573         }
2574         nv_fb->r_handle = 0xffff0000 | kind;
2575
2576         return nv50_fbdma_init(fb->dev, nv_fb->r_handle, 0,
2577                                drm->device.info.ram_user, kind);
2578 }
2579
2580 /******************************************************************************
2581  * Init
2582  *****************************************************************************/
2583
2584 void
2585 nv50_display_fini(struct drm_device *dev)
2586 {
2587 }
2588
2589 int
2590 nv50_display_init(struct drm_device *dev)
2591 {
2592         struct nv50_disp *disp = nv50_disp(dev);
2593         struct drm_crtc *crtc;
2594         u32 *push;
2595
2596         push = evo_wait(nv50_mast(dev), 32);
2597         if (!push)
2598                 return -EBUSY;
2599
2600         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2601                 struct nv50_sync *sync = nv50_sync(crtc);
2602
2603                 nv50_crtc_lut_load(crtc);
2604                 nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data);
2605         }
2606
2607         evo_mthd(push, 0x0088, 1);
2608         evo_data(push, nv50_mast(dev)->base.sync.handle);
2609         evo_kick(push, nv50_mast(dev));
2610         return 0;
2611 }
2612
2613 void
2614 nv50_display_destroy(struct drm_device *dev)
2615 {
2616         struct nv50_disp *disp = nv50_disp(dev);
2617         struct nv50_fbdma *fbdma, *fbtmp;
2618
2619         list_for_each_entry_safe(fbdma, fbtmp, &disp->fbdma, head) {
2620                 nv50_fbdma_fini(fbdma);
2621         }
2622
2623         nv50_dmac_destroy(&disp->mast.base, disp->disp);
2624
2625         nouveau_bo_unmap(disp->sync);
2626         if (disp->sync)
2627                 nouveau_bo_unpin(disp->sync);
2628         nouveau_bo_ref(NULL, &disp->sync);
2629
2630         nouveau_display(dev)->priv = NULL;
2631         kfree(disp);
2632 }
2633
2634 int
2635 nv50_display_create(struct drm_device *dev)
2636 {
2637         struct nvif_device *device = &nouveau_drm(dev)->device;
2638         struct nouveau_drm *drm = nouveau_drm(dev);
2639         struct dcb_table *dcb = &drm->vbios.dcb;
2640         struct drm_connector *connector, *tmp;
2641         struct nv50_disp *disp;
2642         struct dcb_output *dcbe;
2643         int crtcs, ret, i;
2644
2645         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2646         if (!disp)
2647                 return -ENOMEM;
2648         INIT_LIST_HEAD(&disp->fbdma);
2649
2650         nouveau_display(dev)->priv = disp;
2651         nouveau_display(dev)->dtor = nv50_display_destroy;
2652         nouveau_display(dev)->init = nv50_display_init;
2653         nouveau_display(dev)->fini = nv50_display_fini;
2654         nouveau_display(dev)->fb_ctor = nv50_fb_ctor;
2655         nouveau_display(dev)->fb_dtor = nv50_fb_dtor;
2656         disp->disp = &nouveau_display(dev)->disp;
2657
2658         /* small shared memory area we use for notifiers and semaphores */
2659         ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2660                              0, 0x0000, NULL, NULL, &disp->sync);
2661         if (!ret) {
2662                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2663                 if (!ret) {
2664                         ret = nouveau_bo_map(disp->sync);
2665                         if (ret)
2666                                 nouveau_bo_unpin(disp->sync);
2667                 }
2668                 if (ret)
2669                         nouveau_bo_ref(NULL, &disp->sync);
2670         }
2671
2672         if (ret)
2673                 goto out;
2674
2675         /* allocate master evo channel */
2676         ret = nv50_core_create(device, disp->disp, disp->sync->bo.offset,
2677                               &disp->mast);
2678         if (ret)
2679                 goto out;
2680
2681         /* create crtc objects to represent the hw heads */
2682         if (disp->disp->oclass >= GF110_DISP)
2683                 crtcs = nvif_rd32(&device->object, 0x022448);
2684         else
2685                 crtcs = 2;
2686
2687         for (i = 0; i < crtcs; i++) {
2688                 ret = nv50_crtc_create(dev, i);
2689                 if (ret)
2690                         goto out;
2691         }
2692
2693         /* create encoder/connector objects based on VBIOS DCB table */
2694         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2695                 connector = nouveau_connector_create(dev, dcbe->connector);
2696                 if (IS_ERR(connector))
2697                         continue;
2698
2699                 if (dcbe->location == DCB_LOC_ON_CHIP) {
2700                         switch (dcbe->type) {
2701                         case DCB_OUTPUT_TMDS:
2702                         case DCB_OUTPUT_LVDS:
2703                         case DCB_OUTPUT_DP:
2704                                 ret = nv50_sor_create(connector, dcbe);
2705                                 break;
2706                         case DCB_OUTPUT_ANALOG:
2707                                 ret = nv50_dac_create(connector, dcbe);
2708                                 break;
2709                         default:
2710                                 ret = -ENODEV;
2711                                 break;
2712                         }
2713                 } else {
2714                         ret = nv50_pior_create(connector, dcbe);
2715                 }
2716
2717                 if (ret) {
2718                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2719                                      dcbe->location, dcbe->type,
2720                                      ffs(dcbe->or) - 1, ret);
2721                         ret = 0;
2722                 }
2723         }
2724
2725         /* cull any connectors we created that don't have an encoder */
2726         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2727                 if (connector->encoder_ids[0])
2728                         continue;
2729
2730                 NV_WARN(drm, "%s has no encoders, removing\n",
2731                         connector->name);
2732                 connector->funcs->destroy(connector);
2733         }
2734
2735 out:
2736         if (ret)
2737                 nv50_display_destroy(dev);
2738         return ret;
2739 }