2 * Copyright 2011 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/dma-mapping.h>
28 #include <drm/drm_crtc_helper.h>
30 #include "nouveau_drm.h"
31 #include "nouveau_dma.h"
32 #include "nouveau_gem.h"
33 #include "nouveau_connector.h"
34 #include "nouveau_encoder.h"
35 #include "nouveau_crtc.h"
36 #include "nouveau_fence.h"
37 #include "nv50_display.h"
39 #include <core/client.h>
40 #include <core/gpuobj.h>
41 #include <core/class.h>
43 #include <subdev/timer.h>
44 #include <subdev/bar.h>
45 #include <subdev/fb.h>
46 #include <subdev/i2c.h>
50 #define EVO_MASTER (0x00)
51 #define EVO_FLIP(c) (0x01 + (c))
52 #define EVO_OVLY(c) (0x05 + (c))
53 #define EVO_OIMM(c) (0x09 + (c))
54 #define EVO_CURS(c) (0x0d + (c))
56 /* offsets in shared sync bo of various structures */
57 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
58 #define EVO_MAST_NTFY EVO_SYNC( 0, 0x00)
59 #define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00)
60 #define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10)
62 #define EVO_CORE_HANDLE (0xd1500000)
63 #define EVO_CHAN_HANDLE(t,i) (0xd15c0000 | (((t) & 0x00ff) << 8) | (i))
64 #define EVO_CHAN_OCLASS(t,c) ((nv_hclass(c) & 0xff00) | ((t) & 0x00ff))
65 #define EVO_PUSH_HANDLE(t,i) (0xd15b0000 | (i) | \
66 (((NV50_DISP_##t##_CLASS) & 0x00ff) << 8))
68 /******************************************************************************
70 *****************************************************************************/
73 struct nouveau_object *user;
78 nv50_chan_create(struct nouveau_object *core, u32 bclass, u8 head,
79 void *data, u32 size, struct nv50_chan *chan)
81 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
82 const u32 oclass = EVO_CHAN_OCLASS(bclass, core);
83 const u32 handle = EVO_CHAN_HANDLE(bclass, head);
86 ret = nouveau_object_new(client, EVO_CORE_HANDLE, handle,
87 oclass, data, size, &chan->user);
91 chan->handle = handle;
96 nv50_chan_destroy(struct nouveau_object *core, struct nv50_chan *chan)
98 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
100 nouveau_object_del(client, EVO_CORE_HANDLE, chan->handle);
103 /******************************************************************************
105 *****************************************************************************/
108 struct nv50_chan base;
112 nv50_pioc_destroy(struct nouveau_object *core, struct nv50_pioc *pioc)
114 nv50_chan_destroy(core, &pioc->base);
118 nv50_pioc_create(struct nouveau_object *core, u32 bclass, u8 head,
119 void *data, u32 size, struct nv50_pioc *pioc)
121 return nv50_chan_create(core, bclass, head, data, size, &pioc->base);
124 /******************************************************************************
126 *****************************************************************************/
129 struct nv50_chan base;
133 /* Protects against concurrent pushbuf access to this channel, lock is
134 * grabbed by evo_wait (if the pushbuf reservation is successful) and
135 * dropped again by evo_kick. */
140 nv50_dmac_destroy(struct nouveau_object *core, struct nv50_dmac *dmac)
143 struct pci_dev *pdev = nv_device(core)->pdev;
144 pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle);
147 nv50_chan_destroy(core, &dmac->base);
151 nv50_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
153 struct nouveau_fb *pfb = nouveau_fb(core);
154 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
155 struct nouveau_object *object;
156 int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
157 NV_DMA_IN_MEMORY_CLASS,
158 &(struct nv_dma_class) {
159 .flags = NV_DMA_TARGET_VRAM |
162 .limit = pfb->ram->size - 1,
163 .conf0 = NV50_DMA_CONF0_ENABLE |
164 NV50_DMA_CONF0_PART_256,
165 }, sizeof(struct nv_dma_class), &object);
169 ret = nouveau_object_new(client, parent, NvEvoFB16,
170 NV_DMA_IN_MEMORY_CLASS,
171 &(struct nv_dma_class) {
172 .flags = NV_DMA_TARGET_VRAM |
175 .limit = pfb->ram->size - 1,
176 .conf0 = NV50_DMA_CONF0_ENABLE | 0x70 |
177 NV50_DMA_CONF0_PART_256,
178 }, sizeof(struct nv_dma_class), &object);
182 ret = nouveau_object_new(client, parent, NvEvoFB32,
183 NV_DMA_IN_MEMORY_CLASS,
184 &(struct nv_dma_class) {
185 .flags = NV_DMA_TARGET_VRAM |
188 .limit = pfb->ram->size - 1,
189 .conf0 = NV50_DMA_CONF0_ENABLE | 0x7a |
190 NV50_DMA_CONF0_PART_256,
191 }, sizeof(struct nv_dma_class), &object);
196 nvc0_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
198 struct nouveau_fb *pfb = nouveau_fb(core);
199 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
200 struct nouveau_object *object;
201 int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
202 NV_DMA_IN_MEMORY_CLASS,
203 &(struct nv_dma_class) {
204 .flags = NV_DMA_TARGET_VRAM |
207 .limit = pfb->ram->size - 1,
208 .conf0 = NVC0_DMA_CONF0_ENABLE,
209 }, sizeof(struct nv_dma_class), &object);
213 ret = nouveau_object_new(client, parent, NvEvoFB16,
214 NV_DMA_IN_MEMORY_CLASS,
215 &(struct nv_dma_class) {
216 .flags = NV_DMA_TARGET_VRAM |
219 .limit = pfb->ram->size - 1,
220 .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe,
221 }, sizeof(struct nv_dma_class), &object);
225 ret = nouveau_object_new(client, parent, NvEvoFB32,
226 NV_DMA_IN_MEMORY_CLASS,
227 &(struct nv_dma_class) {
228 .flags = NV_DMA_TARGET_VRAM |
231 .limit = pfb->ram->size - 1,
232 .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe,
233 }, sizeof(struct nv_dma_class), &object);
238 nvd0_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
240 struct nouveau_fb *pfb = nouveau_fb(core);
241 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
242 struct nouveau_object *object;
243 int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
244 NV_DMA_IN_MEMORY_CLASS,
245 &(struct nv_dma_class) {
246 .flags = NV_DMA_TARGET_VRAM |
249 .limit = pfb->ram->size - 1,
250 .conf0 = NVD0_DMA_CONF0_ENABLE |
251 NVD0_DMA_CONF0_PAGE_LP,
252 }, sizeof(struct nv_dma_class), &object);
256 ret = nouveau_object_new(client, parent, NvEvoFB32,
257 NV_DMA_IN_MEMORY_CLASS,
258 &(struct nv_dma_class) {
259 .flags = NV_DMA_TARGET_VRAM |
262 .limit = pfb->ram->size - 1,
263 .conf0 = NVD0_DMA_CONF0_ENABLE | 0xfe |
264 NVD0_DMA_CONF0_PAGE_LP,
265 }, sizeof(struct nv_dma_class), &object);
270 nv50_dmac_create(struct nouveau_object *core, u32 bclass, u8 head,
271 void *data, u32 size, u64 syncbuf,
272 struct nv50_dmac *dmac)
274 struct nouveau_fb *pfb = nouveau_fb(core);
275 struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
276 struct nouveau_object *object;
277 u32 pushbuf = *(u32 *)data;
280 mutex_init(&dmac->lock);
282 dmac->ptr = pci_alloc_consistent(nv_device(core)->pdev, PAGE_SIZE,
287 ret = nouveau_object_new(client, NVDRM_DEVICE, pushbuf,
288 NV_DMA_FROM_MEMORY_CLASS,
289 &(struct nv_dma_class) {
290 .flags = NV_DMA_TARGET_PCI_US |
292 .start = dmac->handle + 0x0000,
293 .limit = dmac->handle + 0x0fff,
294 }, sizeof(struct nv_dma_class), &object);
298 ret = nv50_chan_create(core, bclass, head, data, size, &dmac->base);
302 ret = nouveau_object_new(client, dmac->base.handle, NvEvoSync,
303 NV_DMA_IN_MEMORY_CLASS,
304 &(struct nv_dma_class) {
305 .flags = NV_DMA_TARGET_VRAM |
307 .start = syncbuf + 0x0000,
308 .limit = syncbuf + 0x0fff,
309 }, sizeof(struct nv_dma_class), &object);
313 ret = nouveau_object_new(client, dmac->base.handle, NvEvoVRAM,
314 NV_DMA_IN_MEMORY_CLASS,
315 &(struct nv_dma_class) {
316 .flags = NV_DMA_TARGET_VRAM |
319 .limit = pfb->ram->size - 1,
320 }, sizeof(struct nv_dma_class), &object);
324 if (nv_device(core)->card_type < NV_C0)
325 ret = nv50_dmac_create_fbdma(core, dmac->base.handle);
327 if (nv_device(core)->card_type < NV_D0)
328 ret = nvc0_dmac_create_fbdma(core, dmac->base.handle);
330 ret = nvd0_dmac_create_fbdma(core, dmac->base.handle);
335 struct nv50_dmac base;
339 struct nv50_pioc base;
343 struct nv50_dmac base;
349 struct nv50_dmac base;
353 struct nv50_pioc base;
357 struct nouveau_crtc base;
358 struct nouveau_bo *image;
359 struct nv50_curs curs;
360 struct nv50_sync sync;
361 struct nv50_ovly ovly;
362 struct nv50_oimm oimm;
365 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
366 #define nv50_curs(c) (&nv50_head(c)->curs)
367 #define nv50_sync(c) (&nv50_head(c)->sync)
368 #define nv50_ovly(c) (&nv50_head(c)->ovly)
369 #define nv50_oimm(c) (&nv50_head(c)->oimm)
370 #define nv50_chan(c) (&(c)->base.base)
371 #define nv50_vers(c) nv_mclass(nv50_chan(c)->user)
374 struct nouveau_object *core;
375 struct nv50_mast mast;
379 struct nouveau_bo *sync;
382 static struct nv50_disp *
383 nv50_disp(struct drm_device *dev)
385 return nouveau_display(dev)->priv;
388 #define nv50_mast(d) (&nv50_disp(d)->mast)
390 static struct drm_crtc *
391 nv50_display_crtc_get(struct drm_encoder *encoder)
393 return nouveau_encoder(encoder)->crtc;
396 /******************************************************************************
397 * EVO channel helpers
398 *****************************************************************************/
400 evo_wait(void *evoc, int nr)
402 struct nv50_dmac *dmac = evoc;
403 u32 put = nv_ro32(dmac->base.user, 0x0000) / 4;
405 mutex_lock(&dmac->lock);
406 if (put + nr >= (PAGE_SIZE / 4) - 8) {
407 dmac->ptr[put] = 0x20000000;
409 nv_wo32(dmac->base.user, 0x0000, 0x00000000);
410 if (!nv_wait(dmac->base.user, 0x0004, ~0, 0x00000000)) {
411 mutex_unlock(&dmac->lock);
412 NV_ERROR(dmac->base.user, "channel stalled\n");
419 return dmac->ptr + put;
423 evo_kick(u32 *push, void *evoc)
425 struct nv50_dmac *dmac = evoc;
426 nv_wo32(dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
427 mutex_unlock(&dmac->lock);
430 #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
431 #define evo_data(p,d) *((p)++) = (d)
434 evo_sync_wait(void *data)
436 if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000)
443 evo_sync(struct drm_device *dev)
445 struct nouveau_device *device = nouveau_dev(dev);
446 struct nv50_disp *disp = nv50_disp(dev);
447 struct nv50_mast *mast = nv50_mast(dev);
448 u32 *push = evo_wait(mast, 8);
450 nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
451 evo_mthd(push, 0x0084, 1);
452 evo_data(push, 0x80000000 | EVO_MAST_NTFY);
453 evo_mthd(push, 0x0080, 2);
454 evo_data(push, 0x00000000);
455 evo_data(push, 0x00000000);
456 evo_kick(push, mast);
457 if (nv_wait_cb(device, evo_sync_wait, disp->sync))
464 /******************************************************************************
465 * Page flipping channel
466 *****************************************************************************/
468 nv50_display_crtc_sema(struct drm_device *dev, int crtc)
470 return nv50_disp(dev)->sync;
473 struct nv50_display_flip {
474 struct nv50_disp *disp;
475 struct nv50_sync *chan;
479 nv50_display_flip_wait(void *data)
481 struct nv50_display_flip *flip = data;
482 if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) ==
490 nv50_display_flip_stop(struct drm_crtc *crtc)
492 struct nouveau_device *device = nouveau_dev(crtc->dev);
493 struct nv50_display_flip flip = {
494 .disp = nv50_disp(crtc->dev),
495 .chan = nv50_sync(crtc),
499 push = evo_wait(flip.chan, 8);
501 evo_mthd(push, 0x0084, 1);
502 evo_data(push, 0x00000000);
503 evo_mthd(push, 0x0094, 1);
504 evo_data(push, 0x00000000);
505 evo_mthd(push, 0x00c0, 1);
506 evo_data(push, 0x00000000);
507 evo_mthd(push, 0x0080, 1);
508 evo_data(push, 0x00000000);
509 evo_kick(push, flip.chan);
512 nv_wait_cb(device, nv50_display_flip_wait, &flip);
516 nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
517 struct nouveau_channel *chan, u32 swap_interval)
519 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
520 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
521 struct nv50_head *head = nv50_head(crtc);
522 struct nv50_sync *sync = nv50_sync(crtc);
527 if (swap_interval == 0)
528 swap_interval |= 0x100;
532 push = evo_wait(sync, 128);
533 if (unlikely(push == NULL))
536 if (chan && nv_mclass(chan->object) < NV84_CHANNEL_IND_CLASS) {
537 ret = RING_SPACE(chan, 8);
541 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
542 OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
543 OUT_RING (chan, sync->addr ^ 0x10);
544 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
545 OUT_RING (chan, sync->data + 1);
546 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
547 OUT_RING (chan, sync->addr);
548 OUT_RING (chan, sync->data);
550 if (chan && nv_mclass(chan->object) < NVC0_CHANNEL_IND_CLASS) {
551 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
552 ret = RING_SPACE(chan, 12);
556 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
557 OUT_RING (chan, chan->vram);
558 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
559 OUT_RING (chan, upper_32_bits(addr ^ 0x10));
560 OUT_RING (chan, lower_32_bits(addr ^ 0x10));
561 OUT_RING (chan, sync->data + 1);
562 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
563 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
564 OUT_RING (chan, upper_32_bits(addr));
565 OUT_RING (chan, lower_32_bits(addr));
566 OUT_RING (chan, sync->data);
567 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL);
570 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
571 ret = RING_SPACE(chan, 10);
575 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
576 OUT_RING (chan, upper_32_bits(addr ^ 0x10));
577 OUT_RING (chan, lower_32_bits(addr ^ 0x10));
578 OUT_RING (chan, sync->data + 1);
579 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG |
580 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
581 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
582 OUT_RING (chan, upper_32_bits(addr));
583 OUT_RING (chan, lower_32_bits(addr));
584 OUT_RING (chan, sync->data);
585 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL |
586 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
596 evo_mthd(push, 0x0100, 1);
597 evo_data(push, 0xfffe0000);
598 evo_mthd(push, 0x0084, 1);
599 evo_data(push, swap_interval);
600 if (!(swap_interval & 0x00000100)) {
601 evo_mthd(push, 0x00e0, 1);
602 evo_data(push, 0x40000000);
604 evo_mthd(push, 0x0088, 4);
605 evo_data(push, sync->addr);
606 evo_data(push, sync->data++);
607 evo_data(push, sync->data);
608 evo_data(push, NvEvoSync);
609 evo_mthd(push, 0x00a0, 2);
610 evo_data(push, 0x00000000);
611 evo_data(push, 0x00000000);
612 evo_mthd(push, 0x00c0, 1);
613 evo_data(push, nv_fb->r_dma);
614 evo_mthd(push, 0x0110, 2);
615 evo_data(push, 0x00000000);
616 evo_data(push, 0x00000000);
617 if (nv50_vers(sync) < NVD0_DISP_SYNC_CLASS) {
618 evo_mthd(push, 0x0800, 5);
619 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
621 evo_data(push, (fb->height << 16) | fb->width);
622 evo_data(push, nv_fb->r_pitch);
623 evo_data(push, nv_fb->r_format);
625 evo_mthd(push, 0x0400, 5);
626 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
628 evo_data(push, (fb->height << 16) | fb->width);
629 evo_data(push, nv_fb->r_pitch);
630 evo_data(push, nv_fb->r_format);
632 evo_mthd(push, 0x0080, 1);
633 evo_data(push, 0x00000000);
634 evo_kick(push, sync);
636 nouveau_bo_ref(nv_fb->nvbo, &head->image);
640 /******************************************************************************
642 *****************************************************************************/
644 nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
646 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
647 struct nouveau_connector *nv_connector;
648 struct drm_connector *connector;
649 u32 *push, mode = 0x00;
651 nv_connector = nouveau_crtc_connector_get(nv_crtc);
652 connector = &nv_connector->base;
653 if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
654 if (nv_crtc->base.primary->fb->depth > connector->display_info.bpc * 3)
655 mode = DITHERING_MODE_DYNAMIC2X2;
657 mode = nv_connector->dithering_mode;
660 if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
661 if (connector->display_info.bpc >= 8)
662 mode |= DITHERING_DEPTH_8BPC;
664 mode |= nv_connector->dithering_depth;
667 push = evo_wait(mast, 4);
669 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
670 evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1);
671 evo_data(push, mode);
673 if (nv50_vers(mast) < NVE0_DISP_MAST_CLASS) {
674 evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1);
675 evo_data(push, mode);
677 evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1);
678 evo_data(push, mode);
682 evo_mthd(push, 0x0080, 1);
683 evo_data(push, 0x00000000);
685 evo_kick(push, mast);
692 nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
694 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
695 struct drm_display_mode *omode, *umode = &nv_crtc->base.mode;
696 struct drm_crtc *crtc = &nv_crtc->base;
697 struct nouveau_connector *nv_connector;
698 int mode = DRM_MODE_SCALE_NONE;
701 /* start off at the resolution we programmed the crtc for, this
702 * effectively handles NONE/FULL scaling
704 nv_connector = nouveau_crtc_connector_get(nv_crtc);
705 if (nv_connector && nv_connector->native_mode)
706 mode = nv_connector->scaling_mode;
708 if (mode != DRM_MODE_SCALE_NONE)
709 omode = nv_connector->native_mode;
713 oX = omode->hdisplay;
714 oY = omode->vdisplay;
715 if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
718 /* add overscan compensation if necessary, will keep the aspect
719 * ratio the same as the backend mode unless overridden by the
720 * user setting both hborder and vborder properties.
722 if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
723 (nv_connector->underscan == UNDERSCAN_AUTO &&
724 nv_connector->edid &&
725 drm_detect_hdmi_monitor(nv_connector->edid)))) {
726 u32 bX = nv_connector->underscan_hborder;
727 u32 bY = nv_connector->underscan_vborder;
728 u32 aspect = (oY << 19) / oX;
732 if (bY) oY -= (bY * 2);
733 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
735 oX -= (oX >> 4) + 32;
736 if (bY) oY -= (bY * 2);
737 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
741 /* handle CENTER/ASPECT scaling, taking into account the areas
742 * removed already for overscan compensation
745 case DRM_MODE_SCALE_CENTER:
746 oX = min((u32)umode->hdisplay, oX);
747 oY = min((u32)umode->vdisplay, oY);
749 case DRM_MODE_SCALE_ASPECT:
751 u32 aspect = (umode->hdisplay << 19) / umode->vdisplay;
752 oX = ((oY * aspect) + (aspect / 2)) >> 19;
754 u32 aspect = (umode->vdisplay << 19) / umode->hdisplay;
755 oY = ((oX * aspect) + (aspect / 2)) >> 19;
762 push = evo_wait(mast, 8);
764 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
765 /*XXX: SCALE_CTRL_ACTIVE??? */
766 evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2);
767 evo_data(push, (oY << 16) | oX);
768 evo_data(push, (oY << 16) | oX);
769 evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1);
770 evo_data(push, 0x00000000);
771 evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1);
772 evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
774 evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
775 evo_data(push, (oY << 16) | oX);
776 evo_data(push, (oY << 16) | oX);
777 evo_data(push, (oY << 16) | oX);
778 evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
779 evo_data(push, 0x00000000);
780 evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
781 evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
784 evo_kick(push, mast);
787 nv50_display_flip_stop(crtc);
788 nv50_display_flip_next(crtc, crtc->primary->fb,
797 nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
799 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
803 adj = (nv_crtc->color_vibrance > 0) ? 50 : 0;
804 vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff;
805 hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff;
807 push = evo_wait(mast, 16);
809 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
810 evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1);
811 evo_data(push, (hue << 20) | (vib << 8));
813 evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1);
814 evo_data(push, (hue << 20) | (vib << 8));
818 evo_mthd(push, 0x0080, 1);
819 evo_data(push, 0x00000000);
821 evo_kick(push, mast);
828 nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
829 int x, int y, bool update)
831 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
832 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
835 push = evo_wait(mast, 16);
837 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
838 evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1);
839 evo_data(push, nvfb->nvbo->bo.offset >> 8);
840 evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3);
841 evo_data(push, (fb->height << 16) | fb->width);
842 evo_data(push, nvfb->r_pitch);
843 evo_data(push, nvfb->r_format);
844 evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1);
845 evo_data(push, (y << 16) | x);
846 if (nv50_vers(mast) > NV50_DISP_MAST_CLASS) {
847 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
848 evo_data(push, nvfb->r_dma);
851 evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
852 evo_data(push, nvfb->nvbo->bo.offset >> 8);
853 evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
854 evo_data(push, (fb->height << 16) | fb->width);
855 evo_data(push, nvfb->r_pitch);
856 evo_data(push, nvfb->r_format);
857 evo_data(push, nvfb->r_dma);
858 evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
859 evo_data(push, (y << 16) | x);
863 evo_mthd(push, 0x0080, 1);
864 evo_data(push, 0x00000000);
866 evo_kick(push, mast);
869 nv_crtc->fb.tile_flags = nvfb->r_dma;
874 nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc)
876 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
877 u32 *push = evo_wait(mast, 16);
879 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
880 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
881 evo_data(push, 0x85000000);
882 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
884 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
885 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
886 evo_data(push, 0x85000000);
887 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
888 evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
889 evo_data(push, NvEvoVRAM);
891 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
892 evo_data(push, 0x85000000);
893 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
894 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
895 evo_data(push, NvEvoVRAM);
897 evo_kick(push, mast);
902 nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc)
904 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
905 u32 *push = evo_wait(mast, 16);
907 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
908 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
909 evo_data(push, 0x05000000);
911 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
912 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
913 evo_data(push, 0x05000000);
914 evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
915 evo_data(push, 0x00000000);
917 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
918 evo_data(push, 0x05000000);
919 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
920 evo_data(push, 0x00000000);
922 evo_kick(push, mast);
927 nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update)
929 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
932 nv50_crtc_cursor_show(nv_crtc);
934 nv50_crtc_cursor_hide(nv_crtc);
937 u32 *push = evo_wait(mast, 2);
939 evo_mthd(push, 0x0080, 1);
940 evo_data(push, 0x00000000);
941 evo_kick(push, mast);
947 nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
952 nv50_crtc_prepare(struct drm_crtc *crtc)
954 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
955 struct nv50_mast *mast = nv50_mast(crtc->dev);
958 nv50_display_flip_stop(crtc);
960 push = evo_wait(mast, 2);
962 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
963 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
964 evo_data(push, 0x00000000);
965 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
966 evo_data(push, 0x40000000);
968 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
969 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
970 evo_data(push, 0x00000000);
971 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
972 evo_data(push, 0x40000000);
973 evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
974 evo_data(push, 0x00000000);
976 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
977 evo_data(push, 0x00000000);
978 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
979 evo_data(push, 0x03000000);
980 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
981 evo_data(push, 0x00000000);
984 evo_kick(push, mast);
987 nv50_crtc_cursor_show_hide(nv_crtc, false, false);
991 nv50_crtc_commit(struct drm_crtc *crtc)
993 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
994 struct nv50_mast *mast = nv50_mast(crtc->dev);
997 push = evo_wait(mast, 32);
999 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
1000 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1001 evo_data(push, NvEvoVRAM_LP);
1002 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1003 evo_data(push, 0xc0000000);
1004 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1006 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1007 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1008 evo_data(push, nv_crtc->fb.tile_flags);
1009 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1010 evo_data(push, 0xc0000000);
1011 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1012 evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
1013 evo_data(push, NvEvoVRAM);
1015 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
1016 evo_data(push, nv_crtc->fb.tile_flags);
1017 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
1018 evo_data(push, 0x83000000);
1019 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1020 evo_data(push, 0x00000000);
1021 evo_data(push, 0x00000000);
1022 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
1023 evo_data(push, NvEvoVRAM);
1024 evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
1025 evo_data(push, 0xffffff00);
1028 evo_kick(push, mast);
1031 nv50_crtc_cursor_show_hide(nv_crtc, nv_crtc->cursor.visible, true);
1032 nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
1036 nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1037 struct drm_display_mode *adjusted_mode)
1039 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
1044 nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
1046 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb);
1047 struct nv50_head *head = nv50_head(crtc);
1050 ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM);
1053 nouveau_bo_unpin(head->image);
1054 nouveau_bo_ref(nvfb->nvbo, &head->image);
1061 nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
1062 struct drm_display_mode *mode, int x, int y,
1063 struct drm_framebuffer *old_fb)
1065 struct nv50_mast *mast = nv50_mast(crtc->dev);
1066 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1067 struct nouveau_connector *nv_connector;
1068 u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
1069 u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
1070 u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
1071 u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
1072 u32 vblan2e = 0, vblan2s = 1;
1076 hactive = mode->htotal;
1077 hsynce = mode->hsync_end - mode->hsync_start - 1;
1078 hbackp = mode->htotal - mode->hsync_end;
1079 hblanke = hsynce + hbackp;
1080 hfrontp = mode->hsync_start - mode->hdisplay;
1081 hblanks = mode->htotal - hfrontp - 1;
1083 vactive = mode->vtotal * vscan / ilace;
1084 vsynce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
1085 vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace;
1086 vblanke = vsynce + vbackp;
1087 vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
1088 vblanks = vactive - vfrontp - 1;
1089 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1090 vblan2e = vactive + vsynce + vbackp;
1091 vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
1092 vactive = (vactive * 2) + 1;
1095 ret = nv50_crtc_swap_fbs(crtc, old_fb);
1099 push = evo_wait(mast, 64);
1101 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1102 evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2);
1103 evo_data(push, 0x00800000 | mode->clock);
1104 evo_data(push, (ilace == 2) ? 2 : 0);
1105 evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6);
1106 evo_data(push, 0x00000000);
1107 evo_data(push, (vactive << 16) | hactive);
1108 evo_data(push, ( vsynce << 16) | hsynce);
1109 evo_data(push, (vblanke << 16) | hblanke);
1110 evo_data(push, (vblanks << 16) | hblanks);
1111 evo_data(push, (vblan2e << 16) | vblan2s);
1112 evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1);
1113 evo_data(push, 0x00000000);
1114 evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2);
1115 evo_data(push, 0x00000311);
1116 evo_data(push, 0x00000100);
1118 evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6);
1119 evo_data(push, 0x00000000);
1120 evo_data(push, (vactive << 16) | hactive);
1121 evo_data(push, ( vsynce << 16) | hsynce);
1122 evo_data(push, (vblanke << 16) | hblanke);
1123 evo_data(push, (vblanks << 16) | hblanks);
1124 evo_data(push, (vblan2e << 16) | vblan2s);
1125 evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
1126 evo_data(push, 0x00000000); /* ??? */
1127 evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
1128 evo_data(push, mode->clock * 1000);
1129 evo_data(push, 0x00200000); /* ??? */
1130 evo_data(push, mode->clock * 1000);
1131 evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
1132 evo_data(push, 0x00000311);
1133 evo_data(push, 0x00000100);
1136 evo_kick(push, mast);
1139 nv_connector = nouveau_crtc_connector_get(nv_crtc);
1140 nv50_crtc_set_dither(nv_crtc, false);
1141 nv50_crtc_set_scale(nv_crtc, false);
1142 nv50_crtc_set_color_vibrance(nv_crtc, false);
1143 nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, false);
1148 nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
1149 struct drm_framebuffer *old_fb)
1151 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
1152 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1155 if (!crtc->primary->fb) {
1156 NV_DEBUG(drm, "No FB bound\n");
1160 ret = nv50_crtc_swap_fbs(crtc, old_fb);
1164 nv50_display_flip_stop(crtc);
1165 nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, true);
1166 nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
1171 nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
1172 struct drm_framebuffer *fb, int x, int y,
1173 enum mode_set_atomic state)
1175 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1176 nv50_display_flip_stop(crtc);
1177 nv50_crtc_set_image(nv_crtc, fb, x, y, true);
1182 nv50_crtc_lut_load(struct drm_crtc *crtc)
1184 struct nv50_disp *disp = nv50_disp(crtc->dev);
1185 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1186 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
1189 for (i = 0; i < 256; i++) {
1190 u16 r = nv_crtc->lut.r[i] >> 2;
1191 u16 g = nv_crtc->lut.g[i] >> 2;
1192 u16 b = nv_crtc->lut.b[i] >> 2;
1194 if (nv_mclass(disp->core) < NVD0_DISP_CLASS) {
1195 writew(r + 0x0000, lut + (i * 0x08) + 0);
1196 writew(g + 0x0000, lut + (i * 0x08) + 2);
1197 writew(b + 0x0000, lut + (i * 0x08) + 4);
1199 writew(r + 0x6000, lut + (i * 0x20) + 0);
1200 writew(g + 0x6000, lut + (i * 0x20) + 2);
1201 writew(b + 0x6000, lut + (i * 0x20) + 4);
1207 nv50_crtc_disable(struct drm_crtc *crtc)
1209 struct nv50_head *head = nv50_head(crtc);
1211 nouveau_bo_unpin(head->image);
1212 nouveau_bo_ref(NULL, &head->image);
1216 nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
1217 uint32_t handle, uint32_t width, uint32_t height)
1219 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1220 struct drm_device *dev = crtc->dev;
1221 struct drm_gem_object *gem;
1222 struct nouveau_bo *nvbo;
1223 bool visible = (handle != 0);
1227 if (width != 64 || height != 64)
1230 gem = drm_gem_object_lookup(dev, file_priv, handle);
1233 nvbo = nouveau_gem_object(gem);
1235 ret = nouveau_bo_map(nvbo);
1237 for (i = 0; i < 64 * 64; i++) {
1238 u32 v = nouveau_bo_rd32(nvbo, i);
1239 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v);
1241 nouveau_bo_unmap(nvbo);
1244 drm_gem_object_unreference_unlocked(gem);
1247 if (visible != nv_crtc->cursor.visible) {
1248 nv50_crtc_cursor_show_hide(nv_crtc, visible, true);
1249 nv_crtc->cursor.visible = visible;
1256 nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1258 struct nv50_curs *curs = nv50_curs(crtc);
1259 struct nv50_chan *chan = nv50_chan(curs);
1260 nv_wo32(chan->user, 0x0084, (y << 16) | (x & 0xffff));
1261 nv_wo32(chan->user, 0x0080, 0x00000000);
1266 nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
1267 uint32_t start, uint32_t size)
1269 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1270 u32 end = min_t(u32, start + size, 256);
1273 for (i = start; i < end; i++) {
1274 nv_crtc->lut.r[i] = r[i];
1275 nv_crtc->lut.g[i] = g[i];
1276 nv_crtc->lut.b[i] = b[i];
1279 nv50_crtc_lut_load(crtc);
1283 nv50_crtc_destroy(struct drm_crtc *crtc)
1285 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1286 struct nv50_disp *disp = nv50_disp(crtc->dev);
1287 struct nv50_head *head = nv50_head(crtc);
1289 nv50_dmac_destroy(disp->core, &head->ovly.base);
1290 nv50_pioc_destroy(disp->core, &head->oimm.base);
1291 nv50_dmac_destroy(disp->core, &head->sync.base);
1292 nv50_pioc_destroy(disp->core, &head->curs.base);
1294 /*XXX: this shouldn't be necessary, but the core doesn't call
1295 * disconnect() during the cleanup paths
1298 nouveau_bo_unpin(head->image);
1299 nouveau_bo_ref(NULL, &head->image);
1301 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
1302 if (nv_crtc->cursor.nvbo)
1303 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1304 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
1306 nouveau_bo_unmap(nv_crtc->lut.nvbo);
1307 if (nv_crtc->lut.nvbo)
1308 nouveau_bo_unpin(nv_crtc->lut.nvbo);
1309 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
1311 drm_crtc_cleanup(crtc);
1315 static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = {
1316 .dpms = nv50_crtc_dpms,
1317 .prepare = nv50_crtc_prepare,
1318 .commit = nv50_crtc_commit,
1319 .mode_fixup = nv50_crtc_mode_fixup,
1320 .mode_set = nv50_crtc_mode_set,
1321 .mode_set_base = nv50_crtc_mode_set_base,
1322 .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
1323 .load_lut = nv50_crtc_lut_load,
1324 .disable = nv50_crtc_disable,
1327 static const struct drm_crtc_funcs nv50_crtc_func = {
1328 .cursor_set = nv50_crtc_cursor_set,
1329 .cursor_move = nv50_crtc_cursor_move,
1330 .gamma_set = nv50_crtc_gamma_set,
1331 .set_config = nouveau_crtc_set_config,
1332 .destroy = nv50_crtc_destroy,
1333 .page_flip = nouveau_crtc_page_flip,
1337 nv50_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
1342 nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
1347 nv50_crtc_create(struct drm_device *dev, struct nouveau_object *core, int index)
1349 struct nv50_disp *disp = nv50_disp(dev);
1350 struct nv50_head *head;
1351 struct drm_crtc *crtc;
1354 head = kzalloc(sizeof(*head), GFP_KERNEL);
1358 head->base.index = index;
1359 head->base.set_dither = nv50_crtc_set_dither;
1360 head->base.set_scale = nv50_crtc_set_scale;
1361 head->base.set_color_vibrance = nv50_crtc_set_color_vibrance;
1362 head->base.color_vibrance = 50;
1363 head->base.vibrant_hue = 0;
1364 head->base.cursor.set_offset = nv50_cursor_set_offset;
1365 head->base.cursor.set_pos = nv50_cursor_set_pos;
1366 for (i = 0; i < 256; i++) {
1367 head->base.lut.r[i] = i << 8;
1368 head->base.lut.g[i] = i << 8;
1369 head->base.lut.b[i] = i << 8;
1372 crtc = &head->base.base;
1373 drm_crtc_init(dev, crtc, &nv50_crtc_func);
1374 drm_crtc_helper_add(crtc, &nv50_crtc_hfunc);
1375 drm_mode_crtc_set_gamma_size(crtc, 256);
1377 ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
1378 0, 0x0000, NULL, &head->base.lut.nvbo);
1380 ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM);
1382 ret = nouveau_bo_map(head->base.lut.nvbo);
1384 nouveau_bo_unpin(head->base.lut.nvbo);
1387 nouveau_bo_ref(NULL, &head->base.lut.nvbo);
1393 nv50_crtc_lut_load(crtc);
1395 /* allocate cursor resources */
1396 ret = nv50_pioc_create(disp->core, NV50_DISP_CURS_CLASS, index,
1397 &(struct nv50_display_curs_class) {
1399 }, sizeof(struct nv50_display_curs_class),
1404 ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM,
1405 0, 0x0000, NULL, &head->base.cursor.nvbo);
1407 ret = nouveau_bo_pin(head->base.cursor.nvbo, TTM_PL_FLAG_VRAM);
1409 ret = nouveau_bo_map(head->base.cursor.nvbo);
1411 nouveau_bo_unpin(head->base.lut.nvbo);
1414 nouveau_bo_ref(NULL, &head->base.cursor.nvbo);
1420 /* allocate page flip / sync resources */
1421 ret = nv50_dmac_create(disp->core, NV50_DISP_SYNC_CLASS, index,
1422 &(struct nv50_display_sync_class) {
1423 .pushbuf = EVO_PUSH_HANDLE(SYNC, index),
1425 }, sizeof(struct nv50_display_sync_class),
1426 disp->sync->bo.offset, &head->sync.base);
1430 head->sync.addr = EVO_FLIP_SEM0(index);
1431 head->sync.data = 0x00000000;
1433 /* allocate overlay resources */
1434 ret = nv50_pioc_create(disp->core, NV50_DISP_OIMM_CLASS, index,
1435 &(struct nv50_display_oimm_class) {
1437 }, sizeof(struct nv50_display_oimm_class),
1442 ret = nv50_dmac_create(disp->core, NV50_DISP_OVLY_CLASS, index,
1443 &(struct nv50_display_ovly_class) {
1444 .pushbuf = EVO_PUSH_HANDLE(OVLY, index),
1446 }, sizeof(struct nv50_display_ovly_class),
1447 disp->sync->bo.offset, &head->ovly.base);
1453 nv50_crtc_destroy(crtc);
1457 /******************************************************************************
1459 *****************************************************************************/
1461 nv50_dac_dpms(struct drm_encoder *encoder, int mode)
1463 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1464 struct nv50_disp *disp = nv50_disp(encoder->dev);
1465 int or = nv_encoder->or;
1468 dpms_ctrl = 0x00000000;
1469 if (mode == DRM_MODE_DPMS_STANDBY || mode == DRM_MODE_DPMS_OFF)
1470 dpms_ctrl |= 0x00000001;
1471 if (mode == DRM_MODE_DPMS_SUSPEND || mode == DRM_MODE_DPMS_OFF)
1472 dpms_ctrl |= 0x00000004;
1474 nv_call(disp->core, NV50_DISP_DAC_PWR + or, dpms_ctrl);
1478 nv50_dac_mode_fixup(struct drm_encoder *encoder,
1479 const struct drm_display_mode *mode,
1480 struct drm_display_mode *adjusted_mode)
1482 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1483 struct nouveau_connector *nv_connector;
1485 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1486 if (nv_connector && nv_connector->native_mode) {
1487 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1488 int id = adjusted_mode->base.id;
1489 *adjusted_mode = *nv_connector->native_mode;
1490 adjusted_mode->base.id = id;
1498 nv50_dac_commit(struct drm_encoder *encoder)
1503 nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1504 struct drm_display_mode *adjusted_mode)
1506 struct nv50_mast *mast = nv50_mast(encoder->dev);
1507 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1508 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1511 nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1513 push = evo_wait(mast, 8);
1515 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1516 u32 syncs = 0x00000000;
1518 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1519 syncs |= 0x00000001;
1520 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1521 syncs |= 0x00000002;
1523 evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
1524 evo_data(push, 1 << nv_crtc->index);
1525 evo_data(push, syncs);
1527 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1528 u32 syncs = 0x00000001;
1530 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1531 syncs |= 0x00000008;
1532 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1533 syncs |= 0x00000010;
1535 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1536 magic |= 0x00000001;
1538 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1539 evo_data(push, syncs);
1540 evo_data(push, magic);
1541 evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
1542 evo_data(push, 1 << nv_crtc->index);
1545 evo_kick(push, mast);
1548 nv_encoder->crtc = encoder->crtc;
1552 nv50_dac_disconnect(struct drm_encoder *encoder)
1554 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1555 struct nv50_mast *mast = nv50_mast(encoder->dev);
1556 const int or = nv_encoder->or;
1559 if (nv_encoder->crtc) {
1560 nv50_crtc_prepare(nv_encoder->crtc);
1562 push = evo_wait(mast, 4);
1564 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1565 evo_mthd(push, 0x0400 + (or * 0x080), 1);
1566 evo_data(push, 0x00000000);
1568 evo_mthd(push, 0x0180 + (or * 0x020), 1);
1569 evo_data(push, 0x00000000);
1571 evo_kick(push, mast);
1575 nv_encoder->crtc = NULL;
1578 static enum drm_connector_status
1579 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1581 struct nv50_disp *disp = nv50_disp(encoder->dev);
1582 int ret, or = nouveau_encoder(encoder)->or;
1583 u32 load = nouveau_drm(encoder->dev)->vbios.dactestval;
1587 ret = nv_exec(disp->core, NV50_DISP_DAC_LOAD + or, &load, sizeof(load));
1589 return connector_status_disconnected;
1591 return connector_status_connected;
1595 nv50_dac_destroy(struct drm_encoder *encoder)
1597 drm_encoder_cleanup(encoder);
1601 static const struct drm_encoder_helper_funcs nv50_dac_hfunc = {
1602 .dpms = nv50_dac_dpms,
1603 .mode_fixup = nv50_dac_mode_fixup,
1604 .prepare = nv50_dac_disconnect,
1605 .commit = nv50_dac_commit,
1606 .mode_set = nv50_dac_mode_set,
1607 .disable = nv50_dac_disconnect,
1608 .get_crtc = nv50_display_crtc_get,
1609 .detect = nv50_dac_detect
1612 static const struct drm_encoder_funcs nv50_dac_func = {
1613 .destroy = nv50_dac_destroy,
1617 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
1619 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1620 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
1621 struct nouveau_encoder *nv_encoder;
1622 struct drm_encoder *encoder;
1623 int type = DRM_MODE_ENCODER_DAC;
1625 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1628 nv_encoder->dcb = dcbe;
1629 nv_encoder->or = ffs(dcbe->or) - 1;
1630 nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
1632 encoder = to_drm_encoder(nv_encoder);
1633 encoder->possible_crtcs = dcbe->heads;
1634 encoder->possible_clones = 0;
1635 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type);
1636 drm_encoder_helper_add(encoder, &nv50_dac_hfunc);
1638 drm_mode_connector_attach_encoder(connector, encoder);
1642 /******************************************************************************
1644 *****************************************************************************/
1646 nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1648 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1649 struct nouveau_connector *nv_connector;
1650 struct nv50_disp *disp = nv50_disp(encoder->dev);
1652 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1653 if (!drm_detect_monitor_audio(nv_connector->edid))
1656 drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
1658 nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or,
1659 nv_connector->base.eld,
1660 nv_connector->base.eld[2] * 4);
1664 nv50_audio_disconnect(struct drm_encoder *encoder)
1666 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1667 struct nv50_disp *disp = nv50_disp(encoder->dev);
1669 nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or, NULL, 0);
1672 /******************************************************************************
1674 *****************************************************************************/
1676 nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1678 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1679 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1680 struct nouveau_connector *nv_connector;
1681 struct nv50_disp *disp = nv50_disp(encoder->dev);
1682 const u32 moff = (nv_crtc->index << 3) | nv_encoder->or;
1683 u32 rekey = 56; /* binary driver, and tegra constant */
1686 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1687 if (!drm_detect_hdmi_monitor(nv_connector->edid))
1690 max_ac_packet = mode->htotal - mode->hdisplay;
1691 max_ac_packet -= rekey;
1692 max_ac_packet -= 18; /* constant from tegra */
1693 max_ac_packet /= 32;
1695 nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff,
1696 NV84_DISP_SOR_HDMI_PWR_STATE_ON |
1697 (max_ac_packet << 16) | rekey);
1699 nv50_audio_mode_set(encoder, mode);
1703 nv50_hdmi_disconnect(struct drm_encoder *encoder)
1705 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1706 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1707 struct nv50_disp *disp = nv50_disp(encoder->dev);
1708 const u32 moff = (nv_crtc->index << 3) | nv_encoder->or;
1710 nv50_audio_disconnect(encoder);
1712 nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff, 0x00000000);
1715 /******************************************************************************
1717 *****************************************************************************/
1719 nv50_sor_dpms(struct drm_encoder *encoder, int mode)
1721 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1722 struct drm_device *dev = encoder->dev;
1723 struct nv50_disp *disp = nv50_disp(dev);
1724 struct drm_encoder *partner;
1725 int or = nv_encoder->or;
1727 nv_encoder->last_dpms = mode;
1729 list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
1730 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
1732 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
1735 if (nv_partner != nv_encoder &&
1736 nv_partner->dcb->or == nv_encoder->dcb->or) {
1737 if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
1743 nv_call(disp->core, NV50_DISP_SOR_PWR + or, (mode == DRM_MODE_DPMS_ON));
1747 nv50_sor_mode_fixup(struct drm_encoder *encoder,
1748 const struct drm_display_mode *mode,
1749 struct drm_display_mode *adjusted_mode)
1751 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1752 struct nouveau_connector *nv_connector;
1754 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1755 if (nv_connector && nv_connector->native_mode) {
1756 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1757 int id = adjusted_mode->base.id;
1758 *adjusted_mode = *nv_connector->native_mode;
1759 adjusted_mode->base.id = id;
1767 nv50_sor_disconnect(struct drm_encoder *encoder)
1769 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1770 struct nv50_mast *mast = nv50_mast(encoder->dev);
1771 const int or = nv_encoder->or;
1774 if (nv_encoder->crtc) {
1775 nv50_crtc_prepare(nv_encoder->crtc);
1777 push = evo_wait(mast, 4);
1779 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1780 evo_mthd(push, 0x0600 + (or * 0x40), 1);
1781 evo_data(push, 0x00000000);
1783 evo_mthd(push, 0x0200 + (or * 0x20), 1);
1784 evo_data(push, 0x00000000);
1786 evo_kick(push, mast);
1789 nv50_hdmi_disconnect(encoder);
1792 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1793 nv_encoder->crtc = NULL;
1797 nv50_sor_commit(struct drm_encoder *encoder)
1802 nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1803 struct drm_display_mode *mode)
1805 struct nv50_disp *disp = nv50_disp(encoder->dev);
1806 struct nv50_mast *mast = nv50_mast(encoder->dev);
1807 struct drm_device *dev = encoder->dev;
1808 struct nouveau_drm *drm = nouveau_drm(dev);
1809 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1810 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1811 struct nouveau_connector *nv_connector;
1812 struct nvbios *bios = &drm->vbios;
1813 u32 *push, lvds = 0;
1814 u8 owner = 1 << nv_crtc->index;
1818 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1819 switch (nv_encoder->dcb->type) {
1820 case DCB_OUTPUT_TMDS:
1821 if (nv_encoder->dcb->sorconf.link & 1) {
1822 if (mode->clock < 165000)
1830 nv50_hdmi_mode_set(encoder, mode);
1832 case DCB_OUTPUT_LVDS:
1835 if (bios->fp_no_ddc) {
1836 if (bios->fp.dual_link)
1838 if (bios->fp.if_is_24bit)
1841 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1842 if (((u8 *)nv_connector->edid)[121] == 2)
1845 if (mode->clock >= bios->fp.duallink_transition_clk) {
1849 if (lvds & 0x0100) {
1850 if (bios->fp.strapless_is_24bit & 2)
1853 if (bios->fp.strapless_is_24bit & 1)
1857 if (nv_connector->base.display_info.bpc == 8)
1861 nv_call(disp->core, NV50_DISP_SOR_LVDS_SCRIPT + nv_encoder->or, lvds);
1864 if (nv_connector->base.display_info.bpc == 6) {
1865 nv_encoder->dp.datarate = mode->clock * 18 / 8;
1868 if (nv_connector->base.display_info.bpc == 8) {
1869 nv_encoder->dp.datarate = mode->clock * 24 / 8;
1872 nv_encoder->dp.datarate = mode->clock * 30 / 8;
1876 if (nv_encoder->dcb->sorconf.link & 1)
1886 nv50_sor_dpms(encoder, DRM_MODE_DPMS_ON);
1888 push = evo_wait(nv50_mast(dev), 8);
1890 if (nv50_vers(mast) < NVD0_DISP_CLASS) {
1891 u32 ctrl = (depth << 16) | (proto << 8) | owner;
1892 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1894 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1896 evo_mthd(push, 0x0600 + (nv_encoder->or * 0x040), 1);
1897 evo_data(push, ctrl);
1899 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1900 u32 syncs = 0x00000001;
1902 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1903 syncs |= 0x00000008;
1904 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1905 syncs |= 0x00000010;
1907 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1908 magic |= 0x00000001;
1910 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1911 evo_data(push, syncs | (depth << 6));
1912 evo_data(push, magic);
1913 evo_mthd(push, 0x0200 + (nv_encoder->or * 0x020), 1);
1914 evo_data(push, owner | (proto << 8));
1917 evo_kick(push, mast);
1920 nv_encoder->crtc = encoder->crtc;
1924 nv50_sor_destroy(struct drm_encoder *encoder)
1926 drm_encoder_cleanup(encoder);
1930 static const struct drm_encoder_helper_funcs nv50_sor_hfunc = {
1931 .dpms = nv50_sor_dpms,
1932 .mode_fixup = nv50_sor_mode_fixup,
1933 .prepare = nv50_sor_disconnect,
1934 .commit = nv50_sor_commit,
1935 .mode_set = nv50_sor_mode_set,
1936 .disable = nv50_sor_disconnect,
1937 .get_crtc = nv50_display_crtc_get,
1940 static const struct drm_encoder_funcs nv50_sor_func = {
1941 .destroy = nv50_sor_destroy,
1945 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1947 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1948 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
1949 struct nouveau_encoder *nv_encoder;
1950 struct drm_encoder *encoder;
1953 switch (dcbe->type) {
1954 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1955 case DCB_OUTPUT_TMDS:
1958 type = DRM_MODE_ENCODER_TMDS;
1962 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1965 nv_encoder->dcb = dcbe;
1966 nv_encoder->or = ffs(dcbe->or) - 1;
1967 nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
1968 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1970 encoder = to_drm_encoder(nv_encoder);
1971 encoder->possible_crtcs = dcbe->heads;
1972 encoder->possible_clones = 0;
1973 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type);
1974 drm_encoder_helper_add(encoder, &nv50_sor_hfunc);
1976 drm_mode_connector_attach_encoder(connector, encoder);
1980 /******************************************************************************
1982 *****************************************************************************/
1985 nv50_pior_dpms(struct drm_encoder *encoder, int mode)
1987 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1988 struct nv50_disp *disp = nv50_disp(encoder->dev);
1989 u32 mthd = (nv_encoder->dcb->type << 12) | nv_encoder->or;
1990 u32 ctrl = (mode == DRM_MODE_DPMS_ON);
1991 nv_call(disp->core, NV50_DISP_PIOR_PWR + mthd, ctrl);
1995 nv50_pior_mode_fixup(struct drm_encoder *encoder,
1996 const struct drm_display_mode *mode,
1997 struct drm_display_mode *adjusted_mode)
1999 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2000 struct nouveau_connector *nv_connector;
2002 nv_connector = nouveau_encoder_connector_get(nv_encoder);
2003 if (nv_connector && nv_connector->native_mode) {
2004 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
2005 int id = adjusted_mode->base.id;
2006 *adjusted_mode = *nv_connector->native_mode;
2007 adjusted_mode->base.id = id;
2011 adjusted_mode->clock *= 2;
2016 nv50_pior_commit(struct drm_encoder *encoder)
2021 nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
2022 struct drm_display_mode *adjusted_mode)
2024 struct nv50_mast *mast = nv50_mast(encoder->dev);
2025 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2026 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2027 struct nouveau_connector *nv_connector;
2028 u8 owner = 1 << nv_crtc->index;
2032 nv_connector = nouveau_encoder_connector_get(nv_encoder);
2033 switch (nv_connector->base.display_info.bpc) {
2034 case 10: depth = 0x6; break;
2035 case 8: depth = 0x5; break;
2036 case 6: depth = 0x2; break;
2037 default: depth = 0x0; break;
2040 switch (nv_encoder->dcb->type) {
2041 case DCB_OUTPUT_TMDS:
2050 nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON);
2052 push = evo_wait(mast, 8);
2054 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
2055 u32 ctrl = (depth << 16) | (proto << 8) | owner;
2056 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2058 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2060 evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
2061 evo_data(push, ctrl);
2064 evo_kick(push, mast);
2067 nv_encoder->crtc = encoder->crtc;
2071 nv50_pior_disconnect(struct drm_encoder *encoder)
2073 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2074 struct nv50_mast *mast = nv50_mast(encoder->dev);
2075 const int or = nv_encoder->or;
2078 if (nv_encoder->crtc) {
2079 nv50_crtc_prepare(nv_encoder->crtc);
2081 push = evo_wait(mast, 4);
2083 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
2084 evo_mthd(push, 0x0700 + (or * 0x040), 1);
2085 evo_data(push, 0x00000000);
2087 evo_kick(push, mast);
2091 nv_encoder->crtc = NULL;
2095 nv50_pior_destroy(struct drm_encoder *encoder)
2097 drm_encoder_cleanup(encoder);
2101 static const struct drm_encoder_helper_funcs nv50_pior_hfunc = {
2102 .dpms = nv50_pior_dpms,
2103 .mode_fixup = nv50_pior_mode_fixup,
2104 .prepare = nv50_pior_disconnect,
2105 .commit = nv50_pior_commit,
2106 .mode_set = nv50_pior_mode_set,
2107 .disable = nv50_pior_disconnect,
2108 .get_crtc = nv50_display_crtc_get,
2111 static const struct drm_encoder_funcs nv50_pior_func = {
2112 .destroy = nv50_pior_destroy,
2116 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
2118 struct nouveau_drm *drm = nouveau_drm(connector->dev);
2119 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
2120 struct nouveau_i2c_port *ddc = NULL;
2121 struct nouveau_encoder *nv_encoder;
2122 struct drm_encoder *encoder;
2125 switch (dcbe->type) {
2126 case DCB_OUTPUT_TMDS:
2127 ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTDDC(dcbe->extdev));
2128 type = DRM_MODE_ENCODER_TMDS;
2131 ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(dcbe->extdev));
2132 type = DRM_MODE_ENCODER_TMDS;
2138 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2141 nv_encoder->dcb = dcbe;
2142 nv_encoder->or = ffs(dcbe->or) - 1;
2143 nv_encoder->i2c = ddc;
2145 encoder = to_drm_encoder(nv_encoder);
2146 encoder->possible_crtcs = dcbe->heads;
2147 encoder->possible_clones = 0;
2148 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type);
2149 drm_encoder_helper_add(encoder, &nv50_pior_hfunc);
2151 drm_mode_connector_attach_encoder(connector, encoder);
2155 /******************************************************************************
2157 *****************************************************************************/
2159 nv50_display_fini(struct drm_device *dev)
2164 nv50_display_init(struct drm_device *dev)
2166 struct nv50_disp *disp = nv50_disp(dev);
2167 struct drm_crtc *crtc;
2170 push = evo_wait(nv50_mast(dev), 32);
2174 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2175 struct nv50_sync *sync = nv50_sync(crtc);
2176 nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data);
2179 evo_mthd(push, 0x0088, 1);
2180 evo_data(push, NvEvoSync);
2181 evo_kick(push, nv50_mast(dev));
2186 nv50_display_destroy(struct drm_device *dev)
2188 struct nv50_disp *disp = nv50_disp(dev);
2190 nv50_dmac_destroy(disp->core, &disp->mast.base);
2192 nouveau_bo_unmap(disp->sync);
2194 nouveau_bo_unpin(disp->sync);
2195 nouveau_bo_ref(NULL, &disp->sync);
2197 nouveau_display(dev)->priv = NULL;
2202 nv50_display_create(struct drm_device *dev)
2204 struct nouveau_device *device = nouveau_dev(dev);
2205 struct nouveau_drm *drm = nouveau_drm(dev);
2206 struct dcb_table *dcb = &drm->vbios.dcb;
2207 struct drm_connector *connector, *tmp;
2208 struct nv50_disp *disp;
2209 struct dcb_output *dcbe;
2212 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2216 nouveau_display(dev)->priv = disp;
2217 nouveau_display(dev)->dtor = nv50_display_destroy;
2218 nouveau_display(dev)->init = nv50_display_init;
2219 nouveau_display(dev)->fini = nv50_display_fini;
2220 disp->core = nouveau_display(dev)->core;
2222 /* small shared memory area we use for notifiers and semaphores */
2223 ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2224 0, 0x0000, NULL, &disp->sync);
2226 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM);
2228 ret = nouveau_bo_map(disp->sync);
2230 nouveau_bo_unpin(disp->sync);
2233 nouveau_bo_ref(NULL, &disp->sync);
2239 /* allocate master evo channel */
2240 ret = nv50_dmac_create(disp->core, NV50_DISP_MAST_CLASS, 0,
2241 &(struct nv50_display_mast_class) {
2242 .pushbuf = EVO_PUSH_HANDLE(MAST, 0),
2243 }, sizeof(struct nv50_display_mast_class),
2244 disp->sync->bo.offset, &disp->mast.base);
2248 /* create crtc objects to represent the hw heads */
2249 if (nv_mclass(disp->core) >= NVD0_DISP_CLASS)
2250 crtcs = nv_rd32(device, 0x022448);
2254 for (i = 0; i < crtcs; i++) {
2255 ret = nv50_crtc_create(dev, disp->core, i);
2260 /* create encoder/connector objects based on VBIOS DCB table */
2261 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2262 connector = nouveau_connector_create(dev, dcbe->connector);
2263 if (IS_ERR(connector))
2266 if (dcbe->location == DCB_LOC_ON_CHIP) {
2267 switch (dcbe->type) {
2268 case DCB_OUTPUT_TMDS:
2269 case DCB_OUTPUT_LVDS:
2271 ret = nv50_sor_create(connector, dcbe);
2273 case DCB_OUTPUT_ANALOG:
2274 ret = nv50_dac_create(connector, dcbe);
2281 ret = nv50_pior_create(connector, dcbe);
2285 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2286 dcbe->location, dcbe->type,
2287 ffs(dcbe->or) - 1, ret);
2292 /* cull any connectors we created that don't have an encoder */
2293 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2294 if (connector->encoder_ids[0])
2297 NV_WARN(drm, "%s has no encoders, removing\n",
2298 drm_get_connector_name(connector));
2299 connector->funcs->destroy(connector);
2304 nv50_display_destroy(dev);