drivers/gpu/drm/nouveau/nv50_display.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <linux/dma-mapping.h>
  26
  27 #include <drm/drmP.h>
  28 #include <drm/drm_crtc_helper.h>
  29 #include <drm/drm_plane_helper.h>
  30 #include <drm/drm_dp_helper.h>
  31 #include <drm/drm_fb_helper.h>
  32
  33 #include <nvif/class.h>
  34 #include <nvif/cl0002.h>
  35 #include <nvif/cl5070.h>
  36 #include <nvif/cl507a.h>
  37 #include <nvif/cl507b.h>
  38 #include <nvif/cl507c.h>
  39 #include <nvif/cl507d.h>
  40 #include <nvif/cl507e.h>
  41
  42 #include "nouveau_drv.h"
  43 #include "nouveau_dma.h"
  44 #include "nouveau_gem.h"
  45 #include "nouveau_connector.h"
  46 #include "nouveau_encoder.h"
  47 #include "nouveau_crtc.h"
  48 #include "nouveau_fence.h"
  49 #include "nv50_display.h"
  50
  51 #define EVO_DMA_NR 9
  52
  53 #define EVO_MASTER  (0x00)
  54 #define EVO_FLIP(c) (0x01 + (c))
  55 #define EVO_OVLY(c) (0x05 + (c))
  56 #define EVO_OIMM(c) (0x09 + (c))
  57 #define EVO_CURS(c) (0x0d + (c))
  58
  59 /* offsets in shared sync bo of various structures */
  60 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
  61 #define EVO_MAST_NTFY     EVO_SYNC(      0, 0x00)
  62 #define EVO_FLIP_SEM0(c)  EVO_SYNC((c) + 1, 0x00)
  63 #define EVO_FLIP_SEM1(c)  EVO_SYNC((c) + 1, 0x10)
  64
  65 /******************************************************************************
  66  * EVO channel
  67  *****************************************************************************/
  68
  69 struct nv50_chan {
  70         struct nvif_object user;
  71         struct nvif_device *device;
  72 };
  73
  74 static int
  75 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
  76                  const s32 *oclass, u8 head, void *data, u32 size,
  77                  struct nv50_chan *chan)
  78 {
  79         struct nvif_sclass *sclass;
  80         int ret, i, n;
  81
  82         chan->device = device;
  83
  84         ret = n = nvif_object_sclass_get(disp, &sclass);
  85         if (ret < 0)
  86                 return ret;
  87
  88         while (oclass[0]) {
  89                 for (i = 0; i < n; i++) {
  90                         if (sclass[i].oclass == oclass[0]) {
  91                                 ret = nvif_object_init(disp, 0, oclass[0],
  92                                                        data, size, &chan->user);
  93                                 if (ret == 0)
  94                                         nvif_object_map(&chan->user);
  95                                 nvif_object_sclass_put(&sclass);
  96                                 return ret;
  97                         }
  98                 }
  99                 oclass++;
 100         }
 101
 102         nvif_object_sclass_put(&sclass);
 103         return -ENOSYS;
 104 }
 105
 106 static void
 107 nv50_chan_destroy(struct nv50_chan *chan)
 108 {
 109         nvif_object_fini(&chan->user);
 110 }
 111
 112 /******************************************************************************
 113  * PIO EVO channel
 114  *****************************************************************************/
 115
 116 struct nv50_pioc {
 117         struct nv50_chan base;
 118 };
 119
 120 static void
 121 nv50_pioc_destroy(struct nv50_pioc *pioc)
 122 {
 123         nv50_chan_destroy(&pioc->base);
 124 }
 125
 126 static int
 127 nv50_pioc_create(struct nvif_device *device, struct nvif_object *disp,
 128                  const s32 *oclass, u8 head, void *data, u32 size,
 129                  struct nv50_pioc *pioc)
 130 {
 131         return nv50_chan_create(device, disp, oclass, head, data, size,
 132                                 &pioc->base);
 133 }
 134
 135 /******************************************************************************
 136  * Cursor Immediate
 137  *****************************************************************************/
 138
 139 struct nv50_curs {
 140         struct nv50_pioc base;
 141 };
 142
 143 static int
 144 nv50_curs_create(struct nvif_device *device, struct nvif_object *disp,
 145                  int head, struct nv50_curs *curs)
 146 {
 147         struct nv50_disp_cursor_v0 args = {
 148                 .head = head,
 149         };
 150         static const s32 oclass[] = {
 151                 GK104_DISP_CURSOR,
 152                 GF110_DISP_CURSOR,
 153                 GT214_DISP_CURSOR,
 154                 G82_DISP_CURSOR,
 155                 NV50_DISP_CURSOR,
 156                 0
 157         };
 158
 159         return nv50_pioc_create(device, disp, oclass, head, &args, sizeof(args),
 160                                 &curs->base);
 161 }
 162
 163 /******************************************************************************
 164  * Overlay Immediate
 165  *****************************************************************************/
 166
 167 struct nv50_oimm {
 168         struct nv50_pioc base;
 169 };
 170
 171 static int
 172 nv50_oimm_create(struct nvif_device *device, struct nvif_object *disp,
 173                  int head, struct nv50_oimm *oimm)
 174 {
 175         struct nv50_disp_cursor_v0 args = {
 176                 .head = head,
 177         };
 178         static const s32 oclass[] = {
 179                 GK104_DISP_OVERLAY,
 180                 GF110_DISP_OVERLAY,
 181                 GT214_DISP_OVERLAY,
 182                 G82_DISP_OVERLAY,
 183                 NV50_DISP_OVERLAY,
 184                 0
 185         };
 186
 187         return nv50_pioc_create(device, disp, oclass, head, &args, sizeof(args),
 188                                 &oimm->base);
 189 }
 190
 191 /******************************************************************************
 192  * DMA EVO channel
 193  *****************************************************************************/
 194
 195 struct nv50_dmac {
 196         struct nv50_chan base;
 197         dma_addr_t handle;
 198         u32 *ptr;
 199
 200         struct nvif_object sync;
 201         struct nvif_object vram;
 202
 203         /* Protects against concurrent pushbuf access to this channel, lock is
 204          * grabbed by evo_wait (if the pushbuf reservation is successful) and
 205          * dropped again by evo_kick. */
 206         struct mutex lock;
 207 };
 208
 209 static void
 210 nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp)
 211 {
 212         struct nvif_device *device = dmac->base.device;
 213
 214         nvif_object_fini(&dmac->vram);
 215         nvif_object_fini(&dmac->sync);
 216
 217         nv50_chan_destroy(&dmac->base);
 218
 219         if (dmac->ptr) {
 220                 struct device *dev = nvxx_device(device)->dev;
 221                 dma_free_coherent(dev, PAGE_SIZE, dmac->ptr, dmac->handle);
 222         }
 223 }
 224
 225 static int
 226 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 227                  const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
 228                  struct nv50_dmac *dmac)
 229 {
 230         struct nv50_disp_core_channel_dma_v0 *args = data;
 231         struct nvif_object pushbuf;
 232         int ret;
 233
 234         mutex_init(&dmac->lock);
 235
 236         dmac->ptr = dma_alloc_coherent(nvxx_device(device)->dev, PAGE_SIZE,
 237                                        &dmac->handle, GFP_KERNEL);
 238         if (!dmac->ptr)
 239                 return -ENOMEM;
 240
 241         ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY,
 242                                &(struct nv_dma_v0) {
 243                                         .target = NV_DMA_V0_TARGET_PCI_US,
 244                                         .access = NV_DMA_V0_ACCESS_RD,
 245                                         .start = dmac->handle + 0x0000,
 246                                         .limit = dmac->handle + 0x0fff,
 247                                }, sizeof(struct nv_dma_v0), &pushbuf);
 248         if (ret)
 249                 return ret;
 250
 251         args->pushbuf = nvif_handle(&pushbuf);
 252
 253         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 254                                &dmac->base);
 255         nvif_object_fini(&pushbuf);
 256         if (ret)
 257                 return ret;
 258
 259         ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
 260                                &(struct nv_dma_v0) {
 261                                         .target = NV_DMA_V0_TARGET_VRAM,
 262                                         .access = NV_DMA_V0_ACCESS_RDWR,
 263                                         .start = syncbuf + 0x0000,
 264                                         .limit = syncbuf + 0x0fff,
 265                                }, sizeof(struct nv_dma_v0),
 266                                &dmac->sync);
 267         if (ret)
 268                 return ret;
 269
 270         ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
 271                                &(struct nv_dma_v0) {
 272                                         .target = NV_DMA_V0_TARGET_VRAM,
 273                                         .access = NV_DMA_V0_ACCESS_RDWR,
 274                                         .start = 0,
 275                                         .limit = device->info.ram_user - 1,
 276                                }, sizeof(struct nv_dma_v0),
 277                                &dmac->vram);
 278         if (ret)
 279                 return ret;
 280
 281         return ret;
 282 }
 283
 284 /******************************************************************************
 285  * Core
 286  *****************************************************************************/
 287
 288 struct nv50_mast {
 289         struct nv50_dmac base;
 290 };
 291
 292 static int
 293 nv50_core_create(struct nvif_device *device, struct nvif_object *disp,
 294                  u64 syncbuf, struct nv50_mast *core)
 295 {
 296         struct nv50_disp_core_channel_dma_v0 args = {
 297                 .pushbuf = 0xb0007d00,
 298         };
 299         static const s32 oclass[] = {
 300                 GP100_DISP_CORE_CHANNEL_DMA,
 301                 GM200_DISP_CORE_CHANNEL_DMA,
 302                 GM107_DISP_CORE_CHANNEL_DMA,
 303                 GK110_DISP_CORE_CHANNEL_DMA,
 304                 GK104_DISP_CORE_CHANNEL_DMA,
 305                 GF110_DISP_CORE_CHANNEL_DMA,
 306                 GT214_DISP_CORE_CHANNEL_DMA,
 307                 GT206_DISP_CORE_CHANNEL_DMA,
 308                 GT200_DISP_CORE_CHANNEL_DMA,
 309                 G82_DISP_CORE_CHANNEL_DMA,
 310                 NV50_DISP_CORE_CHANNEL_DMA,
 311                 0
 312         };
 313
 314         return nv50_dmac_create(device, disp, oclass, 0, &args, sizeof(args),
 315                                 syncbuf, &core->base);
 316 }
 317
 318 /******************************************************************************
 319  * Base
 320  *****************************************************************************/
 321
 322 struct nv50_sync {
 323         struct nv50_dmac base;
 324         u32 addr;
 325         u32 data;
 326 };
 327
 328 static int
 329 nv50_base_create(struct nvif_device *device, struct nvif_object *disp,
 330                  int head, u64 syncbuf, struct nv50_sync *base)
 331 {
 332         struct nv50_disp_base_channel_dma_v0 args = {
 333                 .pushbuf = 0xb0007c00 | head,
 334                 .head = head,
 335         };
 336         static const s32 oclass[] = {
 337                 GK110_DISP_BASE_CHANNEL_DMA,
 338                 GK104_DISP_BASE_CHANNEL_DMA,
 339                 GF110_DISP_BASE_CHANNEL_DMA,
 340                 GT214_DISP_BASE_CHANNEL_DMA,
 341                 GT200_DISP_BASE_CHANNEL_DMA,
 342                 G82_DISP_BASE_CHANNEL_DMA,
 343                 NV50_DISP_BASE_CHANNEL_DMA,
 344                 0
 345         };
 346
 347         return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
 348                                 syncbuf, &base->base);
 349 }
 350
 351 /******************************************************************************
 352  * Overlay
 353  *****************************************************************************/
 354
 355 struct nv50_ovly {
 356         struct nv50_dmac base;
 357 };
 358
 359 static int
 360 nv50_ovly_create(struct nvif_device *device, struct nvif_object *disp,
 361                  int head, u64 syncbuf, struct nv50_ovly *ovly)
 362 {
 363         struct nv50_disp_overlay_channel_dma_v0 args = {
 364                 .pushbuf = 0xb0007e00 | head,
 365                 .head = head,
 366         };
 367         static const s32 oclass[] = {
 368                 GK104_DISP_OVERLAY_CONTROL_DMA,
 369                 GF110_DISP_OVERLAY_CONTROL_DMA,
 370                 GT214_DISP_OVERLAY_CHANNEL_DMA,
 371                 GT200_DISP_OVERLAY_CHANNEL_DMA,
 372                 G82_DISP_OVERLAY_CHANNEL_DMA,
 373                 NV50_DISP_OVERLAY_CHANNEL_DMA,
 374                 0
 375         };
 376
 377         return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
 378                                 syncbuf, &ovly->base);
 379 }
 380
 381 struct nv50_head {
 382         struct nouveau_crtc base;
 383         struct nouveau_bo *image;
 384         struct nv50_curs curs;
 385         struct nv50_sync sync;
 386         struct nv50_ovly ovly;
 387         struct nv50_oimm oimm;
 388 };
 389
 390 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
 391 #define nv50_curs(c) (&nv50_head(c)->curs)
 392 #define nv50_sync(c) (&nv50_head(c)->sync)
 393 #define nv50_ovly(c) (&nv50_head(c)->ovly)
 394 #define nv50_oimm(c) (&nv50_head(c)->oimm)
 395 #define nv50_chan(c) (&(c)->base.base)
 396 #define nv50_vers(c) nv50_chan(c)->user.oclass
 397
 398 struct nv50_fbdma {
 399         struct list_head head;
 400         struct nvif_object core;
 401         struct nvif_object base[4];
 402 };
 403
 404 struct nv50_disp {
 405         struct nvif_object *disp;
 406         struct nv50_mast mast;
 407
 408         struct list_head fbdma;
 409
 410         struct nouveau_bo *sync;
 411 };
 412
 413 static struct nv50_disp *
 414 nv50_disp(struct drm_device *dev)
 415 {
 416         return nouveau_display(dev)->priv;
 417 }
 418
 419 #define nv50_mast(d) (&nv50_disp(d)->mast)
 420
 421 static struct drm_crtc *
 422 nv50_display_crtc_get(struct drm_encoder *encoder)
 423 {
 424         return nouveau_encoder(encoder)->crtc;
 425 }
 426
 427 /******************************************************************************
 428  * EVO channel helpers
 429  *****************************************************************************/
 430 static u32 *
 431 evo_wait(void *evoc, int nr)
 432 {
 433         struct nv50_dmac *dmac = evoc;
 434         struct nvif_device *device = dmac->base.device;
 435         u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
 436
 437         mutex_lock(&dmac->lock);
 438         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 439                 dmac->ptr[put] = 0x20000000;
 440
 441                 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
 442                 if (nvif_msec(device, 2000,
 443                         if (!nvif_rd32(&dmac->base.user, 0x0004))
 444                                 break;
 445                 ) < 0) {
 446                         mutex_unlock(&dmac->lock);
 447                         printk(KERN_ERR "nouveau: evo channel stalled\n");
 448                         return NULL;
 449                 }
 450
 451                 put = 0;
 452         }
 453
 454         return dmac->ptr + put;
 455 }
 456
 457 static void
 458 evo_kick(u32 *push, void *evoc)
 459 {
 460         struct nv50_dmac *dmac = evoc;
 461         nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 462         mutex_unlock(&dmac->lock);
 463 }
 464
 465 #if 1
 466 #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
 467 #define evo_data(p,d)   *((p)++) = (d)
 468 #else
 469 #define evo_mthd(p,m,s) do {                                                   \
 470         const u32 _m = (m), _s = (s);                                          \
 471         printk(KERN_ERR "%04x %d %s\n", _m, _s, __func__);                     \
 472         *((p)++) = ((_s << 18) | _m);                                          \
 473 } while(0)
 474 #define evo_data(p,d) do {                                                     \
 475         const u32 _d = (d);                                                    \
 476         printk(KERN_ERR "\t%08x\n", _d);                                       \
 477         *((p)++) = _d;                                                         \
 478 } while(0)
 479 #endif
 480
 481 static bool
 482 evo_sync_wait(void *data)
 483 {
 484         if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000)
 485                 return true;
 486         usleep_range(1, 2);
 487         return false;
 488 }
 489
 490 static int
 491 evo_sync(struct drm_device *dev)
 492 {
 493         struct nvif_device *device = &nouveau_drm(dev)->device;
 494         struct nv50_disp *disp = nv50_disp(dev);
 495         struct nv50_mast *mast = nv50_mast(dev);
 496         u32 *push = evo_wait(mast, 8);
 497         if (push) {
 498                 nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
 499                 evo_mthd(push, 0x0084, 1);
 500                 evo_data(push, 0x80000000 | EVO_MAST_NTFY);
 501                 evo_mthd(push, 0x0080, 2);
 502                 evo_data(push, 0x00000000);
 503                 evo_data(push, 0x00000000);
 504                 evo_kick(push, mast);
 505                 if (nvif_msec(device, 2000,
 506                         if (evo_sync_wait(disp->sync))
 507                                 break;
 508                 ) >= 0)
 509                         return 0;
 510         }
 511
 512         return -EBUSY;
 513 }
 514
 515 /******************************************************************************
 516  * Page flipping channel
 517  *****************************************************************************/
 518 struct nouveau_bo *
 519 nv50_display_crtc_sema(struct drm_device *dev, int crtc)
 520 {
 521         return nv50_disp(dev)->sync;
 522 }
 523
 524 struct nv50_display_flip {
 525         struct nv50_disp *disp;
 526         struct nv50_sync *chan;
 527 };
 528
 529 static bool
 530 nv50_display_flip_wait(void *data)
 531 {
 532         struct nv50_display_flip *flip = data;
 533         if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) ==
 534                                               flip->chan->data)
 535                 return true;
 536         usleep_range(1, 2);
 537         return false;
 538 }
 539
 540 void
 541 nv50_display_flip_stop(struct drm_crtc *crtc)
 542 {
 543         struct nvif_device *device = &nouveau_drm(crtc->dev)->device;
 544         struct nv50_display_flip flip = {
 545                 .disp = nv50_disp(crtc->dev),
 546                 .chan = nv50_sync(crtc),
 547         };
 548         u32 *push;
 549
 550         push = evo_wait(flip.chan, 8);
 551         if (push) {
 552                 evo_mthd(push, 0x0084, 1);
 553                 evo_data(push, 0x00000000);
 554                 evo_mthd(push, 0x0094, 1);
 555                 evo_data(push, 0x00000000);
 556                 evo_mthd(push, 0x00c0, 1);
 557                 evo_data(push, 0x00000000);
 558                 evo_mthd(push, 0x0080, 1);
 559                 evo_data(push, 0x00000000);
 560                 evo_kick(push, flip.chan);
 561         }
 562
 563         nvif_msec(device, 2000,
 564                 if (nv50_display_flip_wait(&flip))
 565                         break;
 566         );
 567 }
 568
 569 int
 570 nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 571                        struct nouveau_channel *chan, u32 swap_interval)
 572 {
 573         struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
 574         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 575         struct nv50_head *head = nv50_head(crtc);
 576         struct nv50_sync *sync = nv50_sync(crtc);
 577         u32 *push;
 578         int ret;
 579
 580         if (crtc->primary->fb->width != fb->width ||
 581             crtc->primary->fb->height != fb->height)
 582                 return -EINVAL;
 583
 584         swap_interval <<= 4;
 585         if (swap_interval == 0)
 586                 swap_interval |= 0x100;
 587         if (chan == NULL)
 588                 evo_sync(crtc->dev);
 589
 590         push = evo_wait(sync, 128);
 591         if (unlikely(push == NULL))
 592                 return -EBUSY;
 593
 594         if (chan && chan->user.oclass < G82_CHANNEL_GPFIFO) {
 595                 ret = RING_SPACE(chan, 8);
 596                 if (ret)
 597                         return ret;
 598
 599                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
 600                 OUT_RING  (chan, NvEvoSema0 + nv_crtc->index);
 601                 OUT_RING  (chan, sync->addr ^ 0x10);
 602                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
 603                 OUT_RING  (chan, sync->data + 1);
 604                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
 605                 OUT_RING  (chan, sync->addr);
 606                 OUT_RING  (chan, sync->data);
 607         } else
 608         if (chan && chan->user.oclass < FERMI_CHANNEL_GPFIFO) {
 609                 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
 610                 ret = RING_SPACE(chan, 12);
 611                 if (ret)
 612                         return ret;
 613
 614                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
 615                 OUT_RING  (chan, chan->vram.handle);
 616                 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 617                 OUT_RING  (chan, upper_32_bits(addr ^ 0x10));
 618                 OUT_RING  (chan, lower_32_bits(addr ^ 0x10));
 619                 OUT_RING  (chan, sync->data + 1);
 620                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
 621                 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 622                 OUT_RING  (chan, upper_32_bits(addr));
 623                 OUT_RING  (chan, lower_32_bits(addr));
 624                 OUT_RING  (chan, sync->data);
 625                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL);
 626         } else
 627         if (chan) {
 628                 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
 629                 ret = RING_SPACE(chan, 10);
 630                 if (ret)
 631                         return ret;
 632
 633                 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 634                 OUT_RING  (chan, upper_32_bits(addr ^ 0x10));
 635                 OUT_RING  (chan, lower_32_bits(addr ^ 0x10));
 636                 OUT_RING  (chan, sync->data + 1);
 637                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG |
 638                                  NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
 639                 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 640                 OUT_RING  (chan, upper_32_bits(addr));
 641                 OUT_RING  (chan, lower_32_bits(addr));
 642                 OUT_RING  (chan, sync->data);
 643                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL |
 644                                  NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
 645         }
 646
 647         if (chan) {
 648                 sync->addr ^= 0x10;
 649                 sync->data++;
 650                 FIRE_RING (chan);
 651         }
 652
 653         /* queue the flip */
 654         evo_mthd(push, 0x0100, 1);
 655         evo_data(push, 0xfffe0000);
 656         evo_mthd(push, 0x0084, 1);
 657         evo_data(push, swap_interval);
 658         if (!(swap_interval & 0x00000100)) {
 659                 evo_mthd(push, 0x00e0, 1);
 660                 evo_data(push, 0x40000000);
 661         }
 662         evo_mthd(push, 0x0088, 4);
 663         evo_data(push, sync->addr);
 664         evo_data(push, sync->data++);
 665         evo_data(push, sync->data);
 666         evo_data(push, sync->base.sync.handle);
 667         evo_mthd(push, 0x00a0, 2);
 668         evo_data(push, 0x00000000);
 669         evo_data(push, 0x00000000);
 670         evo_mthd(push, 0x00c0, 1);
 671         evo_data(push, nv_fb->r_handle);
 672         evo_mthd(push, 0x0110, 2);
 673         evo_data(push, 0x00000000);
 674         evo_data(push, 0x00000000);
 675         if (nv50_vers(sync) < GF110_DISP_BASE_CHANNEL_DMA) {
 676                 evo_mthd(push, 0x0800, 5);
 677                 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
 678                 evo_data(push, 0);
 679                 evo_data(push, (fb->height << 16) | fb->width);
 680                 evo_data(push, nv_fb->r_pitch);
 681                 evo_data(push, nv_fb->r_format);
 682         } else {
 683                 evo_mthd(push, 0x0400, 5);
 684                 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
 685                 evo_data(push, 0);
 686                 evo_data(push, (fb->height << 16) | fb->width);
 687                 evo_data(push, nv_fb->r_pitch);
 688                 evo_data(push, nv_fb->r_format);
 689         }
 690         evo_mthd(push, 0x0080, 1);
 691         evo_data(push, 0x00000000);
 692         evo_kick(push, sync);
 693
 694         nouveau_bo_ref(nv_fb->nvbo, &head->image);
 695         return 0;
 696 }
 697
 698 /******************************************************************************
 699  * CRTC
 700  *****************************************************************************/
 701 static int
 702 nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
 703 {
 704         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 705         struct nouveau_connector *nv_connector;
 706         struct drm_connector *connector;
 707         u32 *push, mode = 0x00;
 708
 709         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 710         connector = &nv_connector->base;
 711         if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
 712                 if (nv_crtc->base.primary->fb->depth > connector->display_info.bpc * 3)
 713                         mode = DITHERING_MODE_DYNAMIC2X2;
 714         } else {
 715                 mode = nv_connector->dithering_mode;
 716         }
 717
 718         if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
 719                 if (connector->display_info.bpc >= 8)
 720                         mode |= DITHERING_DEPTH_8BPC;
 721         } else {
 722                 mode |= nv_connector->dithering_depth;
 723         }
 724
 725         push = evo_wait(mast, 4);
 726         if (push) {
 727                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 728                         evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1);
 729                         evo_data(push, mode);
 730                 } else
 731                 if (nv50_vers(mast) < GK104_DISP_CORE_CHANNEL_DMA) {
 732                         evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1);
 733                         evo_data(push, mode);
 734                 } else {
 735                         evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1);
 736                         evo_data(push, mode);
 737                 }
 738
 739                 if (update) {
 740                         evo_mthd(push, 0x0080, 1);
 741                         evo_data(push, 0x00000000);
 742                 }
 743                 evo_kick(push, mast);
 744         }
 745
 746         return 0;
 747 }
 748
 749 static int
 750 nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
 751 {
 752         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 753         struct drm_display_mode *omode, *umode = &nv_crtc->base.mode;
 754         struct drm_crtc *crtc = &nv_crtc->base;
 755         struct nouveau_connector *nv_connector;
 756         int mode = DRM_MODE_SCALE_NONE;
 757         u32 oX, oY, *push;
 758
 759         /* start off at the resolution we programmed the crtc for, this
 760          * effectively handles NONE/FULL scaling
 761          */
 762         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 763         if (nv_connector && nv_connector->native_mode) {
 764                 mode = nv_connector->scaling_mode;
 765                 if (nv_connector->scaling_full) /* non-EDID LVDS/eDP mode */
 766                         mode = DRM_MODE_SCALE_FULLSCREEN;
 767         }
 768
 769         if (mode != DRM_MODE_SCALE_NONE)
 770                 omode = nv_connector->native_mode;
 771         else
 772                 omode = umode;
 773
 774         oX = omode->hdisplay;
 775         oY = omode->vdisplay;
 776         if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
 777                 oY *= 2;
 778
 779         /* add overscan compensation if necessary, will keep the aspect
 780          * ratio the same as the backend mode unless overridden by the
 781          * user setting both hborder and vborder properties.
 782          */
 783         if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
 784                              (nv_connector->underscan == UNDERSCAN_AUTO &&
 785                               drm_detect_hdmi_monitor(nv_connector->edid)))) {
 786                 u32 bX = nv_connector->underscan_hborder;
 787                 u32 bY = nv_connector->underscan_vborder;
 788                 u32 aspect = (oY << 19) / oX;
 789
 790                 if (bX) {
 791                         oX -= (bX * 2);
 792                         if (bY) oY -= (bY * 2);
 793                         else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
 794                 } else {
 795                         oX -= (oX >> 4) + 32;
 796                         if (bY) oY -= (bY * 2);
 797                         else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
 798                 }
 799         }
 800
 801         /* handle CENTER/ASPECT scaling, taking into account the areas
 802          * removed already for overscan compensation
 803          */
 804         switch (mode) {
 805         case DRM_MODE_SCALE_CENTER:
 806                 oX = min((u32)umode->hdisplay, oX);
 807                 oY = min((u32)umode->vdisplay, oY);
 808                 /* fall-through */
 809         case DRM_MODE_SCALE_ASPECT:
 810                 if (oY < oX) {
 811                         u32 aspect = (umode->hdisplay << 19) / umode->vdisplay;
 812                         oX = ((oY * aspect) + (aspect / 2)) >> 19;
 813                 } else {
 814                         u32 aspect = (umode->vdisplay << 19) / umode->hdisplay;
 815                         oY = ((oX * aspect) + (aspect / 2)) >> 19;
 816                 }
 817                 break;
 818         default:
 819                 break;
 820         }
 821
 822         push = evo_wait(mast, 8);
 823         if (push) {
 824                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 825                         /*XXX: SCALE_CTRL_ACTIVE??? */
 826                         evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2);
 827                         evo_data(push, (oY << 16) | oX);
 828                         evo_data(push, (oY << 16) | oX);
 829                         evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1);
 830                         evo_data(push, 0x00000000);
 831                         evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1);
 832                         evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
 833                 } else {
 834                         evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
 835                         evo_data(push, (oY << 16) | oX);
 836                         evo_data(push, (oY << 16) | oX);
 837                         evo_data(push, (oY << 16) | oX);
 838                         evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
 839                         evo_data(push, 0x00000000);
 840                         evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
 841                         evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
 842                 }
 843
 844                 evo_kick(push, mast);
 845
 846                 if (update) {
 847                         nv50_display_flip_stop(crtc);
 848                         nv50_display_flip_next(crtc, crtc->primary->fb,
 849                                                NULL, 1);
 850                 }
 851         }
 852
 853         return 0;
 854 }
 855
 856 static int
 857 nv50_crtc_set_raster_vblank_dmi(struct nouveau_crtc *nv_crtc, u32 usec)
 858 {
 859         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 860         u32 *push;
 861
 862         push = evo_wait(mast, 8);
 863         if (!push)
 864                 return -ENOMEM;
 865
 866         evo_mthd(push, 0x0828 + (nv_crtc->index * 0x400), 1);
 867         evo_data(push, usec);
 868         evo_kick(push, mast);
 869         return 0;
 870 }
 871
 872 static int
 873 nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
 874 {
 875         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 876         u32 *push, hue, vib;
 877         int adj;
 878
 879         adj = (nv_crtc->color_vibrance > 0) ? 50 : 0;
 880         vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff;
 881         hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff;
 882
 883         push = evo_wait(mast, 16);
 884         if (push) {
 885                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 886                         evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1);
 887                         evo_data(push, (hue << 20) | (vib << 8));
 888                 } else {
 889                         evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1);
 890                         evo_data(push, (hue << 20) | (vib << 8));
 891                 }
 892
 893                 if (update) {
 894                         evo_mthd(push, 0x0080, 1);
 895                         evo_data(push, 0x00000000);
 896                 }
 897                 evo_kick(push, mast);
 898         }
 899
 900         return 0;
 901 }
 902
 903 static int
 904 nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
 905                     int x, int y, bool update)
 906 {
 907         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
 908         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 909         u32 *push;
 910
 911         push = evo_wait(mast, 16);
 912         if (push) {
 913                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 914                         evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1);
 915                         evo_data(push, nvfb->nvbo->bo.offset >> 8);
 916                         evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3);
 917                         evo_data(push, (fb->height << 16) | fb->width);
 918                         evo_data(push, nvfb->r_pitch);
 919                         evo_data(push, nvfb->r_format);
 920                         evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1);
 921                         evo_data(push, (y << 16) | x);
 922                         if (nv50_vers(mast) > NV50_DISP_CORE_CHANNEL_DMA) {
 923                                 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
 924                                 evo_data(push, nvfb->r_handle);
 925                         }
 926                 } else {
 927                         evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
 928                         evo_data(push, nvfb->nvbo->bo.offset >> 8);
 929                         evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
 930                         evo_data(push, (fb->height << 16) | fb->width);
 931                         evo_data(push, nvfb->r_pitch);
 932                         evo_data(push, nvfb->r_format);
 933                         evo_data(push, nvfb->r_handle);
 934                         evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
 935                         evo_data(push, (y << 16) | x);
 936                 }
 937
 938                 if (update) {
 939                         evo_mthd(push, 0x0080, 1);
 940                         evo_data(push, 0x00000000);
 941                 }
 942                 evo_kick(push, mast);
 943         }
 944
 945         nv_crtc->fb.handle = nvfb->r_handle;
 946         return 0;
 947 }
 948
 949 static void
 950 nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc)
 951 {
 952         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 953         u32 *push = evo_wait(mast, 16);
 954         if (push) {
 955                 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
 956                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
 957                         evo_data(push, 0x85000000);
 958                         evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 959                 } else
 960                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 961                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
 962                         evo_data(push, 0x85000000);
 963                         evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 964                         evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
 965                         evo_data(push, mast->base.vram.handle);
 966                 } else {
 967                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
 968                         evo_data(push, 0x85000000);
 969                         evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 970                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 971                         evo_data(push, mast->base.vram.handle);
 972                 }
 973                 evo_kick(push, mast);
 974         }
 975         nv_crtc->cursor.visible = true;
 976 }
 977
 978 static void
 979 nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc)
 980 {
 981         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 982         u32 *push = evo_wait(mast, 16);
 983         if (push) {
 984                 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
 985                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
 986                         evo_data(push, 0x05000000);
 987                 } else
 988                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 989                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
 990                         evo_data(push, 0x05000000);
 991                         evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
 992                         evo_data(push, 0x00000000);
 993                 } else {
 994                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
 995                         evo_data(push, 0x05000000);
 996                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 997                         evo_data(push, 0x00000000);
 998                 }
 999                 evo_kick(push, mast);
1000         }
1001         nv_crtc->cursor.visible = false;
1002 }
1003
1004 static void
1005 nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update)
1006 {
1007         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
1008
1009         if (show && nv_crtc->cursor.nvbo && nv_crtc->base.enabled)
1010                 nv50_crtc_cursor_show(nv_crtc);
1011         else
1012                 nv50_crtc_cursor_hide(nv_crtc);
1013
1014         if (update) {
1015                 u32 *push = evo_wait(mast, 2);
1016                 if (push) {
1017                         evo_mthd(push, 0x0080, 1);
1018                         evo_data(push, 0x00000000);
1019                         evo_kick(push, mast);
1020                 }
1021         }
1022 }
1023
1024 static void
1025 nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
1026 {
1027 }
1028
1029 static void
1030 nv50_crtc_prepare(struct drm_crtc *crtc)
1031 {
1032         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1033         struct nv50_mast *mast = nv50_mast(crtc->dev);
1034         u32 *push;
1035
1036         nv50_display_flip_stop(crtc);
1037
1038         push = evo_wait(mast, 6);
1039         if (push) {
1040                 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
1041                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1042                         evo_data(push, 0x00000000);
1043                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
1044                         evo_data(push, 0x40000000);
1045                 } else
1046                 if (nv50_vers(mast) <  GF110_DISP_CORE_CHANNEL_DMA) {
1047                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1048                         evo_data(push, 0x00000000);
1049                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
1050                         evo_data(push, 0x40000000);
1051                         evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
1052                         evo_data(push, 0x00000000);
1053                 } else {
1054                         evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
1055                         evo_data(push, 0x00000000);
1056                         evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
1057                         evo_data(push, 0x03000000);
1058                         evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
1059                         evo_data(push, 0x00000000);
1060                 }
1061
1062                 evo_kick(push, mast);
1063         }
1064
1065         nv50_crtc_cursor_show_hide(nv_crtc, false, false);
1066 }
1067
1068 static void
1069 nv50_crtc_commit(struct drm_crtc *crtc)
1070 {
1071         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1072         struct nv50_mast *mast = nv50_mast(crtc->dev);
1073         u32 *push;
1074
1075         push = evo_wait(mast, 32);
1076         if (push) {
1077                 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
1078                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1079                         evo_data(push, nv_crtc->fb.handle);
1080                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1081                         evo_data(push, 0xc0000000);
1082                         evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1083                 } else
1084                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1085                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1086                         evo_data(push, nv_crtc->fb.handle);
1087                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1088                         evo_data(push, 0xc0000000);
1089                         evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1090                         evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
1091                         evo_data(push, mast->base.vram.handle);
1092                 } else {
1093                         evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
1094                         evo_data(push, nv_crtc->fb.handle);
1095                         evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
1096                         evo_data(push, 0x83000000);
1097                         evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1098                         evo_data(push, 0x00000000);
1099                         evo_data(push, 0x00000000);
1100                         evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
1101                         evo_data(push, mast->base.vram.handle);
1102                         evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
1103                         evo_data(push, 0xffffff00);
1104                 }
1105
1106                 evo_kick(push, mast);
1107         }
1108
1109         nv50_crtc_cursor_show_hide(nv_crtc, true, true);
1110         nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
1111 }
1112
1113 static bool
1114 nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1115                      struct drm_display_mode *adjusted_mode)
1116 {
1117         drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
1118         return true;
1119 }
1120
1121 static int
1122 nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
1123 {
1124         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb);
1125         struct nv50_head *head = nv50_head(crtc);
1126         int ret;
1127
1128         ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM, true);
1129         if (ret == 0) {
1130                 if (head->image)
1131                         nouveau_bo_unpin(head->image);
1132                 nouveau_bo_ref(nvfb->nvbo, &head->image);
1133         }
1134
1135         return ret;
1136 }
1137
1138 static int
1139 nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
1140                    struct drm_display_mode *mode, int x, int y,
1141                    struct drm_framebuffer *old_fb)
1142 {
1143         struct nv50_mast *mast = nv50_mast(crtc->dev);
1144         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1145         struct nouveau_connector *nv_connector;
1146         u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
1147         u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
1148         u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
1149         u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
1150         u32 vblan2e = 0, vblan2s = 1, vblankus = 0;
1151         u32 *push;
1152         int ret;
1153
1154         hactive = mode->htotal;
1155         hsynce  = mode->hsync_end - mode->hsync_start - 1;
1156         hbackp  = mode->htotal - mode->hsync_end;
1157         hblanke = hsynce + hbackp;
1158         hfrontp = mode->hsync_start - mode->hdisplay;
1159         hblanks = mode->htotal - hfrontp - 1;
1160
1161         vactive = mode->vtotal * vscan / ilace;
1162         vsynce  = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
1163         vbackp  = (mode->vtotal - mode->vsync_end) * vscan / ilace;
1164         vblanke = vsynce + vbackp;
1165         vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
1166         vblanks = vactive - vfrontp - 1;
1167         /* XXX: Safe underestimate, even "0" works */
1168         vblankus = (vactive - mode->vdisplay - 2) * hactive;
1169         vblankus *= 1000;
1170         vblankus /= mode->clock;
1171
1172         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1173                 vblan2e = vactive + vsynce + vbackp;
1174                 vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
1175                 vactive = (vactive * 2) + 1;
1176         }
1177
1178         ret = nv50_crtc_swap_fbs(crtc, old_fb);
1179         if (ret)
1180                 return ret;
1181
1182         push = evo_wait(mast, 64);
1183         if (push) {
1184                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1185                         evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2);
1186                         evo_data(push, 0x00800000 | mode->clock);
1187                         evo_data(push, (ilace == 2) ? 2 : 0);
1188                         evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6);
1189                         evo_data(push, 0x00000000);
1190                         evo_data(push, (vactive << 16) | hactive);
1191                         evo_data(push, ( vsynce << 16) | hsynce);
1192                         evo_data(push, (vblanke << 16) | hblanke);
1193                         evo_data(push, (vblanks << 16) | hblanks);
1194                         evo_data(push, (vblan2e << 16) | vblan2s);
1195                         evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1);
1196                         evo_data(push, 0x00000000);
1197                         evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2);
1198                         evo_data(push, 0x00000311);
1199                         evo_data(push, 0x00000100);
1200                 } else {
1201                         evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6);
1202                         evo_data(push, 0x00000000);
1203                         evo_data(push, (vactive << 16) | hactive);
1204                         evo_data(push, ( vsynce << 16) | hsynce);
1205                         evo_data(push, (vblanke << 16) | hblanke);
1206                         evo_data(push, (vblanks << 16) | hblanks);
1207                         evo_data(push, (vblan2e << 16) | vblan2s);
1208                         evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
1209                         evo_data(push, 0x00000000); /* ??? */
1210                         evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
1211                         evo_data(push, mode->clock * 1000);
1212                         evo_data(push, 0x00200000); /* ??? */
1213                         evo_data(push, mode->clock * 1000);
1214                         evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
1215                         evo_data(push, 0x00000311);
1216                         evo_data(push, 0x00000100);
1217                 }
1218
1219                 evo_kick(push, mast);
1220         }
1221
1222         nv_connector = nouveau_crtc_connector_get(nv_crtc);
1223         nv50_crtc_set_dither(nv_crtc, false);
1224         nv50_crtc_set_scale(nv_crtc, false);
1225
1226         /* G94 only accepts this after setting scale */
1227         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA)
1228                 nv50_crtc_set_raster_vblank_dmi(nv_crtc, vblankus);
1229
1230         nv50_crtc_set_color_vibrance(nv_crtc, false);
1231         nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, false);
1232         return 0;
1233 }
1234
1235 static int
1236 nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
1237                         struct drm_framebuffer *old_fb)
1238 {
1239         struct nouveau_drm *drm = nouveau_drm(crtc->dev);
1240         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1241         int ret;
1242
1243         if (!crtc->primary->fb) {
1244                 NV_DEBUG(drm, "No FB bound\n");
1245                 return 0;
1246         }
1247
1248         ret = nv50_crtc_swap_fbs(crtc, old_fb);
1249         if (ret)
1250                 return ret;
1251
1252         nv50_display_flip_stop(crtc);
1253         nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, true);
1254         nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
1255         return 0;
1256 }
1257
1258 static int
1259 nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
1260                                struct drm_framebuffer *fb, int x, int y,
1261                                enum mode_set_atomic state)
1262 {
1263         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1264         nv50_display_flip_stop(crtc);
1265         nv50_crtc_set_image(nv_crtc, fb, x, y, true);
1266         return 0;
1267 }
1268
1269 static void
1270 nv50_crtc_lut_load(struct drm_crtc *crtc)
1271 {
1272         struct nv50_disp *disp = nv50_disp(crtc->dev);
1273         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1274         void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
1275         int i;
1276
1277         for (i = 0; i < 256; i++) {
1278                 u16 r = nv_crtc->lut.r[i] >> 2;
1279                 u16 g = nv_crtc->lut.g[i] >> 2;
1280                 u16 b = nv_crtc->lut.b[i] >> 2;
1281
1282                 if (disp->disp->oclass < GF110_DISP) {
1283                         writew(r + 0x0000, lut + (i * 0x08) + 0);
1284                         writew(g + 0x0000, lut + (i * 0x08) + 2);
1285                         writew(b + 0x0000, lut + (i * 0x08) + 4);
1286                 } else {
1287                         writew(r + 0x6000, lut + (i * 0x20) + 0);
1288                         writew(g + 0x6000, lut + (i * 0x20) + 2);
1289                         writew(b + 0x6000, lut + (i * 0x20) + 4);
1290                 }
1291         }
1292 }
1293
1294 static void
1295 nv50_crtc_disable(struct drm_crtc *crtc)
1296 {
1297         struct nv50_head *head = nv50_head(crtc);
1298         evo_sync(crtc->dev);
1299         if (head->image)
1300                 nouveau_bo_unpin(head->image);
1301         nouveau_bo_ref(NULL, &head->image);
1302 }
1303
1304 static int
1305 nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
1306                      uint32_t handle, uint32_t width, uint32_t height)
1307 {
1308         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1309         struct drm_gem_object *gem = NULL;
1310         struct nouveau_bo *nvbo = NULL;
1311         int ret = 0;
1312
1313         if (handle) {
1314                 if (width != 64 || height != 64)
1315                         return -EINVAL;
1316
1317                 gem = drm_gem_object_lookup(file_priv, handle);
1318                 if (unlikely(!gem))
1319                         return -ENOENT;
1320                 nvbo = nouveau_gem_object(gem);
1321
1322                 ret = nouveau_bo_pin(nvbo, TTM_PL_FLAG_VRAM, true);
1323         }
1324
1325         if (ret == 0) {
1326                 if (nv_crtc->cursor.nvbo)
1327                         nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1328                 nouveau_bo_ref(nvbo, &nv_crtc->cursor.nvbo);
1329         }
1330         drm_gem_object_unreference_unlocked(gem);
1331
1332         nv50_crtc_cursor_show_hide(nv_crtc, true, true);
1333         return ret;
1334 }
1335
1336 static int
1337 nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1338 {
1339         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1340         struct nv50_curs *curs = nv50_curs(crtc);
1341         struct nv50_chan *chan = nv50_chan(curs);
1342         nvif_wr32(&chan->user, 0x0084, (y << 16) | (x & 0xffff));
1343         nvif_wr32(&chan->user, 0x0080, 0x00000000);
1344
1345         nv_crtc->cursor_saved_x = x;
1346         nv_crtc->cursor_saved_y = y;
1347         return 0;
1348 }
1349
1350 static int
1351 nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
1352                     uint32_t size)
1353 {
1354         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1355         u32 i;
1356
1357         for (i = 0; i < size; i++) {
1358                 nv_crtc->lut.r[i] = r[i];
1359                 nv_crtc->lut.g[i] = g[i];
1360                 nv_crtc->lut.b[i] = b[i];
1361         }
1362
1363         nv50_crtc_lut_load(crtc);
1364
1365         return 0;
1366 }
1367
1368 static void
1369 nv50_crtc_cursor_restore(struct nouveau_crtc *nv_crtc, int x, int y)
1370 {
1371         nv50_crtc_cursor_move(&nv_crtc->base, x, y);
1372
1373         nv50_crtc_cursor_show_hide(nv_crtc, true, true);
1374 }
1375
1376 static void
1377 nv50_crtc_destroy(struct drm_crtc *crtc)
1378 {
1379         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1380         struct nv50_disp *disp = nv50_disp(crtc->dev);
1381         struct nv50_head *head = nv50_head(crtc);
1382         struct nv50_fbdma *fbdma;
1383
1384         list_for_each_entry(fbdma, &disp->fbdma, head) {
1385                 nvif_object_fini(&fbdma->base[nv_crtc->index]);
1386         }
1387
1388         nv50_dmac_destroy(&head->ovly.base, disp->disp);
1389         nv50_pioc_destroy(&head->oimm.base);
1390         nv50_dmac_destroy(&head->sync.base, disp->disp);
1391         nv50_pioc_destroy(&head->curs.base);
1392
1393         /*XXX: this shouldn't be necessary, but the core doesn't call
1394          *     disconnect() during the cleanup paths
1395          */
1396         if (head->image)
1397                 nouveau_bo_unpin(head->image);
1398         nouveau_bo_ref(NULL, &head->image);
1399
1400         /*XXX: ditto */
1401         if (nv_crtc->cursor.nvbo)
1402                 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1403         nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
1404
1405         nouveau_bo_unmap(nv_crtc->lut.nvbo);
1406         if (nv_crtc->lut.nvbo)
1407                 nouveau_bo_unpin(nv_crtc->lut.nvbo);
1408         nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
1409
1410         drm_crtc_cleanup(crtc);
1411         kfree(crtc);
1412 }
1413
1414 static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = {
1415         .dpms = nv50_crtc_dpms,
1416         .prepare = nv50_crtc_prepare,
1417         .commit = nv50_crtc_commit,
1418         .mode_fixup = nv50_crtc_mode_fixup,
1419         .mode_set = nv50_crtc_mode_set,
1420         .mode_set_base = nv50_crtc_mode_set_base,
1421         .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
1422         .load_lut = nv50_crtc_lut_load,
1423         .disable = nv50_crtc_disable,
1424 };
1425
1426 static const struct drm_crtc_funcs nv50_crtc_func = {
1427         .cursor_set = nv50_crtc_cursor_set,
1428         .cursor_move = nv50_crtc_cursor_move,
1429         .gamma_set = nv50_crtc_gamma_set,
1430         .set_config = nouveau_crtc_set_config,
1431         .destroy = nv50_crtc_destroy,
1432         .page_flip = nouveau_crtc_page_flip,
1433 };
1434
1435 static int
1436 nv50_crtc_create(struct drm_device *dev, int index)
1437 {
1438         struct nouveau_drm *drm = nouveau_drm(dev);
1439         struct nvif_device *device = &drm->device;
1440         struct nv50_disp *disp = nv50_disp(dev);
1441         struct nv50_head *head;
1442         struct drm_crtc *crtc;
1443         int ret, i;
1444
1445         head = kzalloc(sizeof(*head), GFP_KERNEL);
1446         if (!head)
1447                 return -ENOMEM;
1448
1449         head->base.index = index;
1450         head->base.set_dither = nv50_crtc_set_dither;
1451         head->base.set_scale = nv50_crtc_set_scale;
1452         head->base.set_color_vibrance = nv50_crtc_set_color_vibrance;
1453         head->base.color_vibrance = 50;
1454         head->base.vibrant_hue = 0;
1455         head->base.cursor.set_pos = nv50_crtc_cursor_restore;
1456         for (i = 0; i < 256; i++) {
1457                 head->base.lut.r[i] = i << 8;
1458                 head->base.lut.g[i] = i << 8;
1459                 head->base.lut.b[i] = i << 8;
1460         }
1461
1462         crtc = &head->base.base;
1463         drm_crtc_init(dev, crtc, &nv50_crtc_func);
1464         drm_crtc_helper_add(crtc, &nv50_crtc_hfunc);
1465         drm_mode_crtc_set_gamma_size(crtc, 256);
1466
1467         ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
1468                              0, 0x0000, NULL, NULL, &head->base.lut.nvbo);
1469         if (!ret) {
1470                 ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM, true);
1471                 if (!ret) {
1472                         ret = nouveau_bo_map(head->base.lut.nvbo);
1473                         if (ret)
1474                                 nouveau_bo_unpin(head->base.lut.nvbo);
1475                 }
1476                 if (ret)
1477                         nouveau_bo_ref(NULL, &head->base.lut.nvbo);
1478         }
1479
1480         if (ret)
1481                 goto out;
1482
1483         /* allocate cursor resources */
1484         ret = nv50_curs_create(device, disp->disp, index, &head->curs);
1485         if (ret)
1486                 goto out;
1487
1488         /* allocate page flip / sync resources */
1489         ret = nv50_base_create(device, disp->disp, index, disp->sync->bo.offset,
1490                                &head->sync);
1491         if (ret)
1492                 goto out;
1493
1494         head->sync.addr = EVO_FLIP_SEM0(index);
1495         head->sync.data = 0x00000000;
1496
1497         /* allocate overlay resources */
1498         ret = nv50_oimm_create(device, disp->disp, index, &head->oimm);
1499         if (ret)
1500                 goto out;
1501
1502         ret = nv50_ovly_create(device, disp->disp, index, disp->sync->bo.offset,
1503                                &head->ovly);
1504         if (ret)
1505                 goto out;
1506
1507 out:
1508         if (ret)
1509                 nv50_crtc_destroy(crtc);
1510         return ret;
1511 }
1512
1513 /******************************************************************************
1514  * Encoder helpers
1515  *****************************************************************************/
1516 static bool
1517 nv50_encoder_mode_fixup(struct drm_encoder *encoder,
1518                         const struct drm_display_mode *mode,
1519                         struct drm_display_mode *adjusted_mode)
1520 {
1521         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1522         struct nouveau_connector *nv_connector;
1523
1524         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1525         if (nv_connector && nv_connector->native_mode) {
1526                 nv_connector->scaling_full = false;
1527                 if (nv_connector->scaling_mode == DRM_MODE_SCALE_NONE) {
1528                         switch (nv_connector->type) {
1529                         case DCB_CONNECTOR_LVDS:
1530                         case DCB_CONNECTOR_LVDS_SPWG:
1531                         case DCB_CONNECTOR_eDP:
1532                                 /* force use of scaler for non-edid modes */
1533                                 if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
1534                                         return true;
1535                                 nv_connector->scaling_full = true;
1536                                 break;
1537                         default:
1538                                 return true;
1539                         }
1540                 }
1541
1542                 drm_mode_copy(adjusted_mode, nv_connector->native_mode);
1543         }
1544
1545         return true;
1546 }
1547
1548 /******************************************************************************
1549  * DAC
1550  *****************************************************************************/
1551 static void
1552 nv50_dac_dpms(struct drm_encoder *encoder, int mode)
1553 {
1554         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1555         struct nv50_disp *disp = nv50_disp(encoder->dev);
1556         struct {
1557                 struct nv50_disp_mthd_v1 base;
1558                 struct nv50_disp_dac_pwr_v0 pwr;
1559         } args = {
1560                 .base.version = 1,
1561                 .base.method = NV50_DISP_MTHD_V1_DAC_PWR,
1562                 .base.hasht  = nv_encoder->dcb->hasht,
1563                 .base.hashm  = nv_encoder->dcb->hashm,
1564                 .pwr.state = 1,
1565                 .pwr.data  = 1,
1566                 .pwr.vsync = (mode != DRM_MODE_DPMS_SUSPEND &&
1567                               mode != DRM_MODE_DPMS_OFF),
1568                 .pwr.hsync = (mode != DRM_MODE_DPMS_STANDBY &&
1569                               mode != DRM_MODE_DPMS_OFF),
1570         };
1571
1572         nvif_mthd(disp->disp, 0, &args, sizeof(args));
1573 }
1574
1575 static void
1576 nv50_dac_commit(struct drm_encoder *encoder)
1577 {
1578 }
1579
1580 static void
1581 nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1582                   struct drm_display_mode *adjusted_mode)
1583 {
1584         struct nv50_mast *mast = nv50_mast(encoder->dev);
1585         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1586         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1587         u32 *push;
1588
1589         nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1590
1591         push = evo_wait(mast, 8);
1592         if (push) {
1593                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1594                         u32 syncs = 0x00000000;
1595
1596                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1597                                 syncs |= 0x00000001;
1598                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1599                                 syncs |= 0x00000002;
1600
1601                         evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
1602                         evo_data(push, 1 << nv_crtc->index);
1603                         evo_data(push, syncs);
1604                 } else {
1605                         u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1606                         u32 syncs = 0x00000001;
1607
1608                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1609                                 syncs |= 0x00000008;
1610                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1611                                 syncs |= 0x00000010;
1612
1613                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1614                                 magic |= 0x00000001;
1615
1616                         evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1617                         evo_data(push, syncs);
1618                         evo_data(push, magic);
1619                         evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
1620                         evo_data(push, 1 << nv_crtc->index);
1621                 }
1622
1623                 evo_kick(push, mast);
1624         }
1625
1626         nv_encoder->crtc = encoder->crtc;
1627 }
1628
1629 static void
1630 nv50_dac_disconnect(struct drm_encoder *encoder)
1631 {
1632         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1633         struct nv50_mast *mast = nv50_mast(encoder->dev);
1634         const int or = nv_encoder->or;
1635         u32 *push;
1636
1637         if (nv_encoder->crtc) {
1638                 nv50_crtc_prepare(nv_encoder->crtc);
1639
1640                 push = evo_wait(mast, 4);
1641                 if (push) {
1642                         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1643                                 evo_mthd(push, 0x0400 + (or * 0x080), 1);
1644                                 evo_data(push, 0x00000000);
1645                         } else {
1646                                 evo_mthd(push, 0x0180 + (or * 0x020), 1);
1647                                 evo_data(push, 0x00000000);
1648                         }
1649                         evo_kick(push, mast);
1650                 }
1651         }
1652
1653         nv_encoder->crtc = NULL;
1654 }
1655
1656 static enum drm_connector_status
1657 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1658 {
1659         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1660         struct nv50_disp *disp = nv50_disp(encoder->dev);
1661         struct {
1662                 struct nv50_disp_mthd_v1 base;
1663                 struct nv50_disp_dac_load_v0 load;
1664         } args = {
1665                 .base.version = 1,
1666                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
1667                 .base.hasht  = nv_encoder->dcb->hasht,
1668                 .base.hashm  = nv_encoder->dcb->hashm,
1669         };
1670         int ret;
1671
1672         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
1673         if (args.load.data == 0)
1674                 args.load.data = 340;
1675
1676         ret = nvif_mthd(disp->disp, 0, &args, sizeof(args));
1677         if (ret || !args.load.load)
1678                 return connector_status_disconnected;
1679
1680         return connector_status_connected;
1681 }
1682
1683 static void
1684 nv50_dac_destroy(struct drm_encoder *encoder)
1685 {
1686         drm_encoder_cleanup(encoder);
1687         kfree(encoder);
1688 }
1689
1690 static const struct drm_encoder_helper_funcs nv50_dac_hfunc = {
1691         .dpms = nv50_dac_dpms,
1692         .mode_fixup = nv50_encoder_mode_fixup,
1693         .prepare = nv50_dac_disconnect,
1694         .commit = nv50_dac_commit,
1695         .mode_set = nv50_dac_mode_set,
1696         .disable = nv50_dac_disconnect,
1697         .get_crtc = nv50_display_crtc_get,
1698         .detect = nv50_dac_detect
1699 };
1700
1701 static const struct drm_encoder_funcs nv50_dac_func = {
1702         .destroy = nv50_dac_destroy,
1703 };
1704
1705 static int
1706 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
1707 {
1708         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1709         struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
1710         struct nvkm_i2c_bus *bus;
1711         struct nouveau_encoder *nv_encoder;
1712         struct drm_encoder *encoder;
1713         int type = DRM_MODE_ENCODER_DAC;
1714
1715         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1716         if (!nv_encoder)
1717                 return -ENOMEM;
1718         nv_encoder->dcb = dcbe;
1719         nv_encoder->or = ffs(dcbe->or) - 1;
1720
1721         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1722         if (bus)
1723                 nv_encoder->i2c = &bus->i2c;
1724
1725         encoder = to_drm_encoder(nv_encoder);
1726         encoder->possible_crtcs = dcbe->heads;
1727         encoder->possible_clones = 0;
1728         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type, NULL);
1729         drm_encoder_helper_add(encoder, &nv50_dac_hfunc);
1730
1731         drm_mode_connector_attach_encoder(connector, encoder);
1732         return 0;
1733 }
1734
1735 /******************************************************************************
1736  * Audio
1737  *****************************************************************************/
1738 static void
1739 nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1740 {
1741         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1742         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1743         struct nouveau_connector *nv_connector;
1744         struct nv50_disp *disp = nv50_disp(encoder->dev);
1745         struct __packed {
1746                 struct {
1747                         struct nv50_disp_mthd_v1 mthd;
1748                         struct nv50_disp_sor_hda_eld_v0 eld;
1749                 } base;
1750                 u8 data[sizeof(nv_connector->base.eld)];
1751         } args = {
1752                 .base.mthd.version = 1,
1753                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
1754                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
1755                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
1756                                      (0x0100 << nv_crtc->index),
1757         };
1758
1759         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1760         if (!drm_detect_monitor_audio(nv_connector->edid))
1761                 return;
1762
1763         drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
1764         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
1765
1766         nvif_mthd(disp->disp, 0, &args,
1767                   sizeof(args.base) + drm_eld_size(args.data));
1768 }
1769
1770 static void
1771 nv50_audio_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
1772 {
1773         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1774         struct nv50_disp *disp = nv50_disp(encoder->dev);
1775         struct {
1776                 struct nv50_disp_mthd_v1 base;
1777                 struct nv50_disp_sor_hda_eld_v0 eld;
1778         } args = {
1779                 .base.version = 1,
1780                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
1781                 .base.hasht   = nv_encoder->dcb->hasht,
1782                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
1783                                 (0x0100 << nv_crtc->index),
1784         };
1785
1786         nvif_mthd(disp->disp, 0, &args, sizeof(args));
1787 }
1788
1789 /******************************************************************************
1790  * HDMI
1791  *****************************************************************************/
1792 static void
1793 nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1794 {
1795         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1796         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1797         struct nv50_disp *disp = nv50_disp(encoder->dev);
1798         struct {
1799                 struct nv50_disp_mthd_v1 base;
1800                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
1801         } args = {
1802                 .base.version = 1,
1803                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
1804                 .base.hasht  = nv_encoder->dcb->hasht,
1805                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
1806                                (0x0100 << nv_crtc->index),
1807                 .pwr.state = 1,
1808                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
1809         };
1810         struct nouveau_connector *nv_connector;
1811         u32 max_ac_packet;
1812
1813         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1814         if (!drm_detect_hdmi_monitor(nv_connector->edid))
1815                 return;
1816
1817         max_ac_packet  = mode->htotal - mode->hdisplay;
1818         max_ac_packet -= args.pwr.rekey;
1819         max_ac_packet -= 18; /* constant from tegra */
1820         args.pwr.max_ac_packet = max_ac_packet / 32;
1821
1822         nvif_mthd(disp->disp, 0, &args, sizeof(args));
1823         nv50_audio_mode_set(encoder, mode);
1824 }
1825
1826 static void
1827 nv50_hdmi_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
1828 {
1829         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1830         struct nv50_disp *disp = nv50_disp(encoder->dev);
1831         struct {
1832                 struct nv50_disp_mthd_v1 base;
1833                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
1834         } args = {
1835                 .base.version = 1,
1836                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
1837                 .base.hasht  = nv_encoder->dcb->hasht,
1838                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
1839                                (0x0100 << nv_crtc->index),
1840         };
1841
1842         nvif_mthd(disp->disp, 0, &args, sizeof(args));
1843 }
1844
1845 /******************************************************************************
1846  * SOR
1847  *****************************************************************************/
1848 static void
1849 nv50_sor_dpms(struct drm_encoder *encoder, int mode)
1850 {
1851         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1852         struct nv50_disp *disp = nv50_disp(encoder->dev);
1853         struct {
1854                 struct nv50_disp_mthd_v1 base;
1855                 struct nv50_disp_sor_pwr_v0 pwr;
1856         } args = {
1857                 .base.version = 1,
1858                 .base.method = NV50_DISP_MTHD_V1_SOR_PWR,
1859                 .base.hasht  = nv_encoder->dcb->hasht,
1860                 .base.hashm  = nv_encoder->dcb->hashm,
1861                 .pwr.state = mode == DRM_MODE_DPMS_ON,
1862         };
1863         struct {
1864                 struct nv50_disp_mthd_v1 base;
1865                 struct nv50_disp_sor_dp_pwr_v0 pwr;
1866         } link = {
1867                 .base.version = 1,
1868                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_PWR,
1869                 .base.hasht  = nv_encoder->dcb->hasht,
1870                 .base.hashm  = nv_encoder->dcb->hashm,
1871                 .pwr.state = mode == DRM_MODE_DPMS_ON,
1872         };
1873         struct drm_device *dev = encoder->dev;
1874         struct drm_encoder *partner;
1875
1876         nv_encoder->last_dpms = mode;
1877
1878         list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
1879                 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
1880
1881                 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
1882                         continue;
1883
1884                 if (nv_partner != nv_encoder &&
1885                     nv_partner->dcb->or == nv_encoder->dcb->or) {
1886                         if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
1887                                 return;
1888                         break;
1889                 }
1890         }
1891
1892         if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
1893                 args.pwr.state = 1;
1894                 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1895                 nvif_mthd(disp->disp, 0, &link, sizeof(link));
1896         } else {
1897                 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1898         }
1899 }
1900
1901 static void
1902 nv50_sor_ctrl(struct nouveau_encoder *nv_encoder, u32 mask, u32 data)
1903 {
1904         struct nv50_mast *mast = nv50_mast(nv_encoder->base.base.dev);
1905         u32 temp = (nv_encoder->ctrl & ~mask) | (data & mask), *push;
1906         if (temp != nv_encoder->ctrl && (push = evo_wait(mast, 2))) {
1907                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1908                         evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1);
1909                         evo_data(push, (nv_encoder->ctrl = temp));
1910                 } else {
1911                         evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
1912                         evo_data(push, (nv_encoder->ctrl = temp));
1913                 }
1914                 evo_kick(push, mast);
1915         }
1916 }
1917
1918 static void
1919 nv50_sor_disconnect(struct drm_encoder *encoder)
1920 {
1921         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1922         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1923
1924         nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1925         nv_encoder->crtc = NULL;
1926
1927         if (nv_crtc) {
1928                 nv50_crtc_prepare(&nv_crtc->base);
1929                 nv50_sor_ctrl(nv_encoder, 1 << nv_crtc->index, 0);
1930                 nv50_audio_disconnect(encoder, nv_crtc);
1931                 nv50_hdmi_disconnect(&nv_encoder->base.base, nv_crtc);
1932         }
1933 }
1934
1935 static void
1936 nv50_sor_commit(struct drm_encoder *encoder)
1937 {
1938 }
1939
1940 static void
1941 nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1942                   struct drm_display_mode *mode)
1943 {
1944         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1945         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1946         struct {
1947                 struct nv50_disp_mthd_v1 base;
1948                 struct nv50_disp_sor_lvds_script_v0 lvds;
1949         } lvds = {
1950                 .base.version = 1,
1951                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1952                 .base.hasht   = nv_encoder->dcb->hasht,
1953                 .base.hashm   = nv_encoder->dcb->hashm,
1954         };
1955         struct nv50_disp *disp = nv50_disp(encoder->dev);
1956         struct nv50_mast *mast = nv50_mast(encoder->dev);
1957         struct drm_device *dev = encoder->dev;
1958         struct nouveau_drm *drm = nouveau_drm(dev);
1959         struct nouveau_connector *nv_connector;
1960         struct nvbios *bios = &drm->vbios;
1961         u32 mask, ctrl;
1962         u8 owner = 1 << nv_crtc->index;
1963         u8 proto = 0xf;
1964         u8 depth = 0x0;
1965
1966         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1967         nv_encoder->crtc = encoder->crtc;
1968
1969         switch (nv_encoder->dcb->type) {
1970         case DCB_OUTPUT_TMDS:
1971                 if (nv_encoder->dcb->sorconf.link & 1) {
1972                         proto = 0x1;
1973                         /* Only enable dual-link if:
1974                          *  - Need to (i.e. rate > 165MHz)
1975                          *  - DCB says we can
1976                          *  - Not an HDMI monitor, since there's no dual-link
1977                          *    on HDMI.
1978                          */
1979                         if (mode->clock >= 165000 &&
1980                             nv_encoder->dcb->duallink_possible &&
1981                             !drm_detect_hdmi_monitor(nv_connector->edid))
1982                                 proto |= 0x4;
1983                 } else {
1984                         proto = 0x2;
1985                 }
1986
1987                 nv50_hdmi_mode_set(&nv_encoder->base.base, mode);
1988                 break;
1989         case DCB_OUTPUT_LVDS:
1990                 proto = 0x0;
1991
1992                 if (bios->fp_no_ddc) {
1993                         if (bios->fp.dual_link)
1994                                 lvds.lvds.script |= 0x0100;
1995                         if (bios->fp.if_is_24bit)
1996                                 lvds.lvds.script |= 0x0200;
1997                 } else {
1998                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1999                                 if (((u8 *)nv_connector->edid)[121] == 2)
2000                                         lvds.lvds.script |= 0x0100;
2001                         } else
2002                         if (mode->clock >= bios->fp.duallink_transition_clk) {
2003                                 lvds.lvds.script |= 0x0100;
2004                         }
2005
2006                         if (lvds.lvds.script & 0x0100) {
2007                                 if (bios->fp.strapless_is_24bit & 2)
2008                                         lvds.lvds.script |= 0x0200;
2009                         } else {
2010                                 if (bios->fp.strapless_is_24bit & 1)
2011                                         lvds.lvds.script |= 0x0200;
2012                         }
2013
2014                         if (nv_connector->base.display_info.bpc == 8)
2015                                 lvds.lvds.script |= 0x0200;
2016                 }
2017
2018                 nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds));
2019                 break;
2020         case DCB_OUTPUT_DP:
2021                 if (nv_connector->base.display_info.bpc == 6) {
2022                         nv_encoder->dp.datarate = mode->clock * 18 / 8;
2023                         depth = 0x2;
2024                 } else
2025                 if (nv_connector->base.display_info.bpc == 8) {
2026                         nv_encoder->dp.datarate = mode->clock * 24 / 8;
2027                         depth = 0x5;
2028                 } else {
2029                         nv_encoder->dp.datarate = mode->clock * 30 / 8;
2030                         depth = 0x6;
2031                 }
2032
2033                 if (nv_encoder->dcb->sorconf.link & 1)
2034                         proto = 0x8;
2035                 else
2036                         proto = 0x9;
2037                 nv50_audio_mode_set(encoder, mode);
2038                 break;
2039         default:
2040                 BUG_ON(1);
2041                 break;
2042         }
2043
2044         nv50_sor_dpms(&nv_encoder->base.base, DRM_MODE_DPMS_ON);
2045
2046         if (nv50_vers(mast) >= GF110_DISP) {
2047                 u32 *push = evo_wait(mast, 3);
2048                 if (push) {
2049                         u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
2050                         u32 syncs = 0x00000001;
2051
2052                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2053                                 syncs |= 0x00000008;
2054                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2055                                 syncs |= 0x00000010;
2056
2057                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2058                                 magic |= 0x00000001;
2059
2060                         evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
2061                         evo_data(push, syncs | (depth << 6));
2062                         evo_data(push, magic);
2063                         evo_kick(push, mast);
2064                 }
2065
2066                 ctrl = proto << 8;
2067                 mask = 0x00000f00;
2068         } else {
2069                 ctrl = (depth << 16) | (proto << 8);
2070                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2071                         ctrl |= 0x00001000;
2072                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2073                         ctrl |= 0x00002000;
2074                 mask = 0x000f3f00;
2075         }
2076
2077         nv50_sor_ctrl(nv_encoder, mask | owner, ctrl | owner);
2078 }
2079
2080 static void
2081 nv50_sor_destroy(struct drm_encoder *encoder)
2082 {
2083         drm_encoder_cleanup(encoder);
2084         kfree(encoder);
2085 }
2086
2087 static const struct drm_encoder_helper_funcs nv50_sor_hfunc = {
2088         .dpms = nv50_sor_dpms,
2089         .mode_fixup = nv50_encoder_mode_fixup,
2090         .prepare = nv50_sor_disconnect,
2091         .commit = nv50_sor_commit,
2092         .mode_set = nv50_sor_mode_set,
2093         .disable = nv50_sor_disconnect,
2094         .get_crtc = nv50_display_crtc_get,
2095 };
2096
2097 static const struct drm_encoder_funcs nv50_sor_func = {
2098         .destroy = nv50_sor_destroy,
2099 };
2100
2101 static int
2102 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
2103 {
2104         struct nouveau_drm *drm = nouveau_drm(connector->dev);
2105         struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
2106         struct nouveau_encoder *nv_encoder;
2107         struct drm_encoder *encoder;
2108         int type;
2109
2110         switch (dcbe->type) {
2111         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
2112         case DCB_OUTPUT_TMDS:
2113         case DCB_OUTPUT_DP:
2114         default:
2115                 type = DRM_MODE_ENCODER_TMDS;
2116                 break;
2117         }
2118
2119         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2120         if (!nv_encoder)
2121                 return -ENOMEM;
2122         nv_encoder->dcb = dcbe;
2123         nv_encoder->or = ffs(dcbe->or) - 1;
2124         nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
2125
2126         if (dcbe->type == DCB_OUTPUT_DP) {
2127                 struct nvkm_i2c_aux *aux =
2128                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
2129                 if (aux) {
2130                         nv_encoder->i2c = &aux->i2c;
2131                         nv_encoder->aux = aux;
2132                 }
2133         } else {
2134                 struct nvkm_i2c_bus *bus =
2135                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
2136                 if (bus)
2137                         nv_encoder->i2c = &bus->i2c;
2138         }
2139
2140         encoder = to_drm_encoder(nv_encoder);
2141         encoder->possible_crtcs = dcbe->heads;
2142         encoder->possible_clones = 0;
2143         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type, NULL);
2144         drm_encoder_helper_add(encoder, &nv50_sor_hfunc);
2145
2146         drm_mode_connector_attach_encoder(connector, encoder);
2147         return 0;
2148 }
2149
2150 /******************************************************************************
2151  * PIOR
2152  *****************************************************************************/
2153
2154 static void
2155 nv50_pior_dpms(struct drm_encoder *encoder, int mode)
2156 {
2157         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2158         struct nv50_disp *disp = nv50_disp(encoder->dev);
2159         struct {
2160                 struct nv50_disp_mthd_v1 base;
2161                 struct nv50_disp_pior_pwr_v0 pwr;
2162         } args = {
2163                 .base.version = 1,
2164                 .base.method = NV50_DISP_MTHD_V1_PIOR_PWR,
2165                 .base.hasht  = nv_encoder->dcb->hasht,
2166                 .base.hashm  = nv_encoder->dcb->hashm,
2167                 .pwr.state = mode == DRM_MODE_DPMS_ON,
2168                 .pwr.type = nv_encoder->dcb->type,
2169         };
2170
2171         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2172 }
2173
2174 static bool
2175 nv50_pior_mode_fixup(struct drm_encoder *encoder,
2176                      const struct drm_display_mode *mode,
2177                      struct drm_display_mode *adjusted_mode)
2178 {
2179         if (!nv50_encoder_mode_fixup(encoder, mode, adjusted_mode))
2180                 return false;
2181         adjusted_mode->clock *= 2;
2182         return true;
2183 }
2184
2185 static void
2186 nv50_pior_commit(struct drm_encoder *encoder)
2187 {
2188 }
2189
2190 static void
2191 nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
2192                    struct drm_display_mode *adjusted_mode)
2193 {
2194         struct nv50_mast *mast = nv50_mast(encoder->dev);
2195         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2196         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2197         struct nouveau_connector *nv_connector;
2198         u8 owner = 1 << nv_crtc->index;
2199         u8 proto, depth;
2200         u32 *push;
2201
2202         nv_connector = nouveau_encoder_connector_get(nv_encoder);
2203         switch (nv_connector->base.display_info.bpc) {
2204         case 10: depth = 0x6; break;
2205         case  8: depth = 0x5; break;
2206         case  6: depth = 0x2; break;
2207         default: depth = 0x0; break;
2208         }
2209
2210         switch (nv_encoder->dcb->type) {
2211         case DCB_OUTPUT_TMDS:
2212         case DCB_OUTPUT_DP:
2213                 proto = 0x0;
2214                 break;
2215         default:
2216                 BUG_ON(1);
2217                 break;
2218         }
2219
2220         nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON);
2221
2222         push = evo_wait(mast, 8);
2223         if (push) {
2224                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2225                         u32 ctrl = (depth << 16) | (proto << 8) | owner;
2226                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2227                                 ctrl |= 0x00001000;
2228                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2229                                 ctrl |= 0x00002000;
2230                         evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
2231                         evo_data(push, ctrl);
2232                 }
2233
2234                 evo_kick(push, mast);
2235         }
2236
2237         nv_encoder->crtc = encoder->crtc;
2238 }
2239
2240 static void
2241 nv50_pior_disconnect(struct drm_encoder *encoder)
2242 {
2243         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2244         struct nv50_mast *mast = nv50_mast(encoder->dev);
2245         const int or = nv_encoder->or;
2246         u32 *push;
2247
2248         if (nv_encoder->crtc) {
2249                 nv50_crtc_prepare(nv_encoder->crtc);
2250
2251                 push = evo_wait(mast, 4);
2252                 if (push) {
2253                         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2254                                 evo_mthd(push, 0x0700 + (or * 0x040), 1);
2255                                 evo_data(push, 0x00000000);
2256                         }
2257                         evo_kick(push, mast);
2258                 }
2259         }
2260
2261         nv_encoder->crtc = NULL;
2262 }
2263
2264 static void
2265 nv50_pior_destroy(struct drm_encoder *encoder)
2266 {
2267         drm_encoder_cleanup(encoder);
2268         kfree(encoder);
2269 }
2270
2271 static const struct drm_encoder_helper_funcs nv50_pior_hfunc = {
2272         .dpms = nv50_pior_dpms,
2273         .mode_fixup = nv50_pior_mode_fixup,
2274         .prepare = nv50_pior_disconnect,
2275         .commit = nv50_pior_commit,
2276         .mode_set = nv50_pior_mode_set,
2277         .disable = nv50_pior_disconnect,
2278         .get_crtc = nv50_display_crtc_get,
2279 };
2280
2281 static const struct drm_encoder_funcs nv50_pior_func = {
2282         .destroy = nv50_pior_destroy,
2283 };
2284
2285 static int
2286 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
2287 {
2288         struct nouveau_drm *drm = nouveau_drm(connector->dev);
2289         struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
2290         struct nvkm_i2c_bus *bus = NULL;
2291         struct nvkm_i2c_aux *aux = NULL;
2292         struct i2c_adapter *ddc;
2293         struct nouveau_encoder *nv_encoder;
2294         struct drm_encoder *encoder;
2295         int type;
2296
2297         switch (dcbe->type) {
2298         case DCB_OUTPUT_TMDS:
2299                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
2300                 ddc  = bus ? &bus->i2c : NULL;
2301                 type = DRM_MODE_ENCODER_TMDS;
2302                 break;
2303         case DCB_OUTPUT_DP:
2304                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
2305                 ddc  = aux ? &aux->i2c : NULL;
2306                 type = DRM_MODE_ENCODER_TMDS;
2307                 break;
2308         default:
2309                 return -ENODEV;
2310         }
2311
2312         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2313         if (!nv_encoder)
2314                 return -ENOMEM;
2315         nv_encoder->dcb = dcbe;
2316         nv_encoder->or = ffs(dcbe->or) - 1;
2317         nv_encoder->i2c = ddc;
2318         nv_encoder->aux = aux;
2319
2320         encoder = to_drm_encoder(nv_encoder);
2321         encoder->possible_crtcs = dcbe->heads;
2322         encoder->possible_clones = 0;
2323         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type, NULL);
2324         drm_encoder_helper_add(encoder, &nv50_pior_hfunc);
2325
2326         drm_mode_connector_attach_encoder(connector, encoder);
2327         return 0;
2328 }
2329
2330 /******************************************************************************
2331  * Framebuffer
2332  *****************************************************************************/
2333
2334 static void
2335 nv50_fbdma_fini(struct nv50_fbdma *fbdma)
2336 {
2337         int i;
2338         for (i = 0; i < ARRAY_SIZE(fbdma->base); i++)
2339                 nvif_object_fini(&fbdma->base[i]);
2340         nvif_object_fini(&fbdma->core);
2341         list_del(&fbdma->head);
2342         kfree(fbdma);
2343 }
2344
2345 static int
2346 nv50_fbdma_init(struct drm_device *dev, u32 name, u64 offset, u64 length, u8 kind)
2347 {
2348         struct nouveau_drm *drm = nouveau_drm(dev);
2349         struct nv50_disp *disp = nv50_disp(dev);
2350         struct nv50_mast *mast = nv50_mast(dev);
2351         struct __attribute__ ((packed)) {
2352                 struct nv_dma_v0 base;
2353                 union {
2354                         struct nv50_dma_v0 nv50;
2355                         struct gf100_dma_v0 gf100;
2356                         struct gf119_dma_v0 gf119;
2357                 };
2358         } args = {};
2359         struct nv50_fbdma *fbdma;
2360         struct drm_crtc *crtc;
2361         u32 size = sizeof(args.base);
2362         int ret;
2363
2364         list_for_each_entry(fbdma, &disp->fbdma, head) {
2365                 if (fbdma->core.handle == name)
2366                         return 0;
2367         }
2368
2369         fbdma = kzalloc(sizeof(*fbdma), GFP_KERNEL);
2370         if (!fbdma)
2371                 return -ENOMEM;
2372         list_add(&fbdma->head, &disp->fbdma);
2373
2374         args.base.target = NV_DMA_V0_TARGET_VRAM;
2375         args.base.access = NV_DMA_V0_ACCESS_RDWR;
2376         args.base.start = offset;
2377         args.base.limit = offset + length - 1;
2378
2379         if (drm->device.info.chipset < 0x80) {
2380                 args.nv50.part = NV50_DMA_V0_PART_256;
2381                 size += sizeof(args.nv50);
2382         } else
2383         if (drm->device.info.chipset < 0xc0) {
2384                 args.nv50.part = NV50_DMA_V0_PART_256;
2385                 args.nv50.kind = kind;
2386                 size += sizeof(args.nv50);
2387         } else
2388         if (drm->device.info.chipset < 0xd0) {
2389                 args.gf100.kind = kind;
2390                 size += sizeof(args.gf100);
2391         } else {
2392                 args.gf119.page = GF119_DMA_V0_PAGE_LP;
2393                 args.gf119.kind = kind;
2394                 size += sizeof(args.gf119);
2395         }
2396
2397         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2398                 struct nv50_head *head = nv50_head(crtc);
2399                 int ret = nvif_object_init(&head->sync.base.base.user, name,
2400                                            NV_DMA_IN_MEMORY, &args, size,
2401                                            &fbdma->base[head->base.index]);
2402                 if (ret) {
2403                         nv50_fbdma_fini(fbdma);
2404                         return ret;
2405                 }
2406         }
2407
2408         ret = nvif_object_init(&mast->base.base.user, name, NV_DMA_IN_MEMORY,
2409                                &args, size, &fbdma->core);
2410         if (ret) {
2411                 nv50_fbdma_fini(fbdma);
2412                 return ret;
2413         }
2414
2415         return 0;
2416 }
2417
2418 static void
2419 nv50_fb_dtor(struct drm_framebuffer *fb)
2420 {
2421 }
2422
2423 static int
2424 nv50_fb_ctor(struct drm_framebuffer *fb)
2425 {
2426         struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
2427         struct nouveau_drm *drm = nouveau_drm(fb->dev);
2428         struct nouveau_bo *nvbo = nv_fb->nvbo;
2429         struct nv50_disp *disp = nv50_disp(fb->dev);
2430         u8 kind = nouveau_bo_tile_layout(nvbo) >> 8;
2431         u8 tile = nvbo->tile_mode;
2432
2433         if (drm->device.info.chipset >= 0xc0)
2434                 tile >>= 4; /* yep.. */
2435
2436         switch (fb->depth) {
2437         case  8: nv_fb->r_format = 0x1e00; break;
2438         case 15: nv_fb->r_format = 0xe900; break;
2439         case 16: nv_fb->r_format = 0xe800; break;
2440         case 24:
2441         case 32: nv_fb->r_format = 0xcf00; break;
2442         case 30: nv_fb->r_format = 0xd100; break;
2443         default:
2444                  NV_ERROR(drm, "unknown depth %d\n", fb->depth);
2445                  return -EINVAL;
2446         }
2447
2448         if (disp->disp->oclass < G82_DISP) {
2449                 nv_fb->r_pitch   = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2450                                             (fb->pitches[0] | 0x00100000);
2451                 nv_fb->r_format |= kind << 16;
2452         } else
2453         if (disp->disp->oclass < GF110_DISP) {
2454                 nv_fb->r_pitch  = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2455                                            (fb->pitches[0] | 0x00100000);
2456         } else {
2457                 nv_fb->r_pitch  = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2458                                            (fb->pitches[0] | 0x01000000);
2459         }
2460         nv_fb->r_handle = 0xffff0000 | kind;
2461
2462         return nv50_fbdma_init(fb->dev, nv_fb->r_handle, 0,
2463                                drm->device.info.ram_user, kind);
2464 }
2465
2466 /******************************************************************************
2467  * Init
2468  *****************************************************************************/
2469
2470 void
2471 nv50_display_fini(struct drm_device *dev)
2472 {
2473 }
2474
2475 int
2476 nv50_display_init(struct drm_device *dev)
2477 {
2478         struct nv50_disp *disp = nv50_disp(dev);
2479         struct drm_crtc *crtc;
2480         u32 *push;
2481
2482         push = evo_wait(nv50_mast(dev), 32);
2483         if (!push)
2484                 return -EBUSY;
2485
2486         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2487                 struct nv50_sync *sync = nv50_sync(crtc);
2488
2489                 nv50_crtc_lut_load(crtc);
2490                 nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data);
2491         }
2492
2493         evo_mthd(push, 0x0088, 1);
2494         evo_data(push, nv50_mast(dev)->base.sync.handle);
2495         evo_kick(push, nv50_mast(dev));
2496         return 0;
2497 }
2498
2499 void
2500 nv50_display_destroy(struct drm_device *dev)
2501 {
2502         struct nv50_disp *disp = nv50_disp(dev);
2503         struct nv50_fbdma *fbdma, *fbtmp;
2504
2505         list_for_each_entry_safe(fbdma, fbtmp, &disp->fbdma, head) {
2506                 nv50_fbdma_fini(fbdma);
2507         }
2508
2509         nv50_dmac_destroy(&disp->mast.base, disp->disp);
2510
2511         nouveau_bo_unmap(disp->sync);
2512         if (disp->sync)
2513                 nouveau_bo_unpin(disp->sync);
2514         nouveau_bo_ref(NULL, &disp->sync);
2515
2516         nouveau_display(dev)->priv = NULL;
2517         kfree(disp);
2518 }
2519
2520 int
2521 nv50_display_create(struct drm_device *dev)
2522 {
2523         struct nvif_device *device = &nouveau_drm(dev)->device;
2524         struct nouveau_drm *drm = nouveau_drm(dev);
2525         struct dcb_table *dcb = &drm->vbios.dcb;
2526         struct drm_connector *connector, *tmp;
2527         struct nv50_disp *disp;
2528         struct dcb_output *dcbe;
2529         int crtcs, ret, i;
2530
2531         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2532         if (!disp)
2533                 return -ENOMEM;
2534         INIT_LIST_HEAD(&disp->fbdma);
2535
2536         nouveau_display(dev)->priv = disp;
2537         nouveau_display(dev)->dtor = nv50_display_destroy;
2538         nouveau_display(dev)->init = nv50_display_init;
2539         nouveau_display(dev)->fini = nv50_display_fini;
2540         nouveau_display(dev)->fb_ctor = nv50_fb_ctor;
2541         nouveau_display(dev)->fb_dtor = nv50_fb_dtor;
2542         disp->disp = &nouveau_display(dev)->disp;
2543
2544         /* small shared memory area we use for notifiers and semaphores */
2545         ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2546                              0, 0x0000, NULL, NULL, &disp->sync);
2547         if (!ret) {
2548                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2549                 if (!ret) {
2550                         ret = nouveau_bo_map(disp->sync);
2551                         if (ret)
2552                                 nouveau_bo_unpin(disp->sync);
2553                 }
2554                 if (ret)
2555                         nouveau_bo_ref(NULL, &disp->sync);
2556         }
2557
2558         if (ret)
2559                 goto out;
2560
2561         /* allocate master evo channel */
2562         ret = nv50_core_create(device, disp->disp, disp->sync->bo.offset,
2563                               &disp->mast);
2564         if (ret)
2565                 goto out;
2566
2567         /* create crtc objects to represent the hw heads */
2568         if (disp->disp->oclass >= GF110_DISP)
2569                 crtcs = nvif_rd32(&device->object, 0x022448);
2570         else
2571                 crtcs = 2;
2572
2573         for (i = 0; i < crtcs; i++) {
2574                 ret = nv50_crtc_create(dev, i);
2575                 if (ret)
2576                         goto out;
2577         }
2578
2579         /* create encoder/connector objects based on VBIOS DCB table */
2580         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2581                 connector = nouveau_connector_create(dev, dcbe->connector);
2582                 if (IS_ERR(connector))
2583                         continue;
2584
2585                 if (dcbe->location == DCB_LOC_ON_CHIP) {
2586                         switch (dcbe->type) {
2587                         case DCB_OUTPUT_TMDS:
2588                         case DCB_OUTPUT_LVDS:
2589                         case DCB_OUTPUT_DP:
2590                                 ret = nv50_sor_create(connector, dcbe);
2591                                 break;
2592                         case DCB_OUTPUT_ANALOG:
2593                                 ret = nv50_dac_create(connector, dcbe);
2594                                 break;
2595                         default:
2596                                 ret = -ENODEV;
2597                                 break;
2598                         }
2599                 } else {
2600                         ret = nv50_pior_create(connector, dcbe);
2601                 }
2602
2603                 if (ret) {
2604                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2605                                      dcbe->location, dcbe->type,
2606                                      ffs(dcbe->or) - 1, ret);
2607                         ret = 0;
2608                 }
2609         }
2610
2611         /* cull any connectors we created that don't have an encoder */
2612         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2613                 if (connector->encoder_ids[0])
2614                         continue;
2615
2616                 NV_WARN(drm, "%s has no encoders, removing\n",
2617                         connector->name);
2618                 connector->funcs->destroy(connector);
2619         }
2620
2621 out:
2622         if (ret)
2623                 nv50_display_destroy(dev);
2624         return ret;
2625 }