2 * Copyright 2010 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "nouveau_drv.h"
28 #include "nouveau_dma.h"
29 #include "nouveau_ramht.h"
32 nv50_evo_channel_del(struct nouveau_channel **pevo)
34 struct drm_nouveau_private *dev_priv;
35 struct nouveau_channel *evo = *pevo;
41 dev_priv = evo->dev->dev_private;
42 dev_priv->evo_alloc &= ~(1 << evo->id);
44 nouveau_gpuobj_channel_takedown(evo);
45 nouveau_bo_unmap(evo->pushbuf_bo);
46 nouveau_bo_ref(NULL, &evo->pushbuf_bo);
55 nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 class, u32 name,
56 u32 tile_flags, u32 magic_flags, u32 offset, u32 limit)
58 struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
59 struct drm_device *dev = evo->dev;
60 struct nouveau_gpuobj *obj = NULL;
63 ret = nouveau_gpuobj_new(dev, dev_priv->evo, 6*4, 32, 0, &obj);
66 obj->engine = NVOBJ_ENGINE_DISPLAY;
68 nv_wo32(obj, 0, (tile_flags << 22) | (magic_flags << 16) | class);
69 nv_wo32(obj, 4, limit);
70 nv_wo32(obj, 8, offset);
71 nv_wo32(obj, 12, 0x00000000);
72 nv_wo32(obj, 16, 0x00000000);
73 if (dev_priv->card_type < NV_C0)
74 nv_wo32(obj, 20, 0x00010000);
76 nv_wo32(obj, 20, 0x00020000);
77 dev_priv->engine.instmem.flush(dev);
79 ret = nouveau_ramht_insert(evo, name, obj);
80 nouveau_gpuobj_ref(NULL, &obj);
89 nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pevo)
91 struct drm_nouveau_private *dev_priv = dev->dev_private;
92 struct nouveau_channel *evo;
95 evo = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
100 for (evo->id = 0; evo->id < 5; evo->id++) {
101 if (dev_priv->evo_alloc & (1 << evo->id))
104 dev_priv->evo_alloc |= (1 << evo->id);
117 ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0,
118 false, true, &evo->pushbuf_bo);
120 ret = nouveau_bo_pin(evo->pushbuf_bo, TTM_PL_FLAG_VRAM);
122 NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
123 nv50_evo_channel_del(pevo);
127 ret = nouveau_bo_map(evo->pushbuf_bo);
129 NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
130 nv50_evo_channel_del(pevo);
134 evo->user = ioremap(pci_resource_start(dev->pdev, 0) +
135 NV50_PDISPLAY_USER(evo->id), PAGE_SIZE);
137 NV_ERROR(dev, "Error mapping EVO control regs.\n");
138 nv50_evo_channel_del(pevo);
142 /* bind primary evo channel's ramht to the channel */
143 if (dev_priv->evo && evo != dev_priv->evo)
144 nouveau_ramht_ref(dev_priv->evo->ramht, &evo->ramht, NULL);
150 nv50_evo_channel_init(struct nouveau_channel *evo)
152 struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
153 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
154 struct drm_device *dev = evo->dev;
155 int id = evo->id, ret, i;
159 /* taken from nv bug #12637, attempts to un-wedge the hw if it's
160 * stuck in some unspecified state
162 start = ptimer->read(dev);
163 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x2b00);
164 while ((tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id))) & 0x1e0000) {
165 if ((tmp & 0x9f0000) == 0x20000)
166 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x800000);
168 if ((tmp & 0x3f0000) == 0x30000)
169 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x200000);
171 if (ptimer->read(dev) - start > 1000000000ULL) {
172 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) != 0\n");
173 NV_ERROR(dev, "0x610200 = 0x%08x\n", tmp);
178 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x1000b03);
179 if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id),
180 0x40000000, 0x40000000)) {
181 NV_ERROR(dev, "timeout: (0x610200 & 0x40000000) == 0x40000000\n");
182 NV_ERROR(dev, "0x610200 = 0x%08x\n",
183 nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)));
187 /* initialise fifo */
188 nv_wr32(dev, NV50_PDISPLAY_EVO_DMA_CB(id),
189 ((evo->pushbuf_bo->bo.mem.start << PAGE_SHIFT) >> 8) |
190 NV50_PDISPLAY_EVO_DMA_CB_LOCATION_VRAM |
191 NV50_PDISPLAY_EVO_DMA_CB_VALID);
192 nv_wr32(dev, NV50_PDISPLAY_EVO_UNK2(id), 0x00010000);
193 nv_wr32(dev, NV50_PDISPLAY_EVO_HASH_TAG(id), id);
194 if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x80000000, 0x00000000)) {
195 NV_ERROR(dev, "timeout: (0x610200 & 0x80000000) == 0\n");
196 NV_ERROR(dev, "0x610200 = 0x%08x\n",
197 nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)));
200 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id),
201 (nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)) & ~0x00000003) |
202 NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
203 nv_wr32(dev, NV50_PDISPLAY_USER_PUT(id), 0);
204 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x01000003 |
205 NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
207 /* enable error reporting on the channel */
208 nv_mask(dev, 0x610028, 0x00000000, 0x00010001 << id);
210 evo->dma.max = (4096/4) - 2;
212 evo->dma.cur = evo->dma.put;
213 evo->dma.free = evo->dma.max - evo->dma.cur;
215 ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
219 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
226 nv50_evo_channel_fini(struct nouveau_channel *evo)
228 struct drm_device *dev = evo->dev;
230 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(evo->id), 0);
231 if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(evo->id), 0x1e0000, 0)) {
232 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) == 0\n");
233 NV_ERROR(dev, "0x610200 = 0x%08x\n",
234 nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(evo->id)));
239 nv50_evo_create(struct drm_device *dev)
241 struct drm_nouveau_private *dev_priv = dev->dev_private;
242 struct nouveau_gpuobj *ramht = NULL;
243 struct nouveau_channel *evo;
246 /* create primary evo channel, the one we use for modesetting
249 ret = nv50_evo_channel_new(dev, &dev_priv->evo);
254 /* setup object management on it, any other evo channel will
255 * use this also as there's no per-channel support on the
258 ret = nouveau_gpuobj_new(dev, NULL, 32768, 0x1000,
259 NVOBJ_FLAG_ZERO_ALLOC, &evo->ramin);
261 NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
262 nv50_evo_channel_del(&dev_priv->evo);
266 ret = drm_mm_init(&evo->ramin_heap, 0, 32768);
268 NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
269 nv50_evo_channel_del(&dev_priv->evo);
273 ret = nouveau_gpuobj_new(dev, evo, 4096, 16, 0, &ramht);
275 NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
276 nv50_evo_channel_del(&dev_priv->evo);
280 ret = nouveau_ramht_new(dev, ramht, &evo->ramht);
281 nouveau_gpuobj_ref(NULL, &ramht);
283 nv50_evo_channel_del(&dev_priv->evo);
287 /* create some default objects for the scanout memtypes we support */
288 if (dev_priv->chipset != 0x50) {
289 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB16, 0x70, 0x19,
292 nv50_evo_channel_del(&dev_priv->evo);
297 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB32, 0x7a, 0x19,
300 nv50_evo_channel_del(&dev_priv->evo);
305 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM, 0, 0x19,
306 0, dev_priv->vram_size);
308 nv50_evo_channel_del(&dev_priv->evo);
316 nv50_evo_init(struct drm_device *dev)
318 struct drm_nouveau_private *dev_priv = dev->dev_private;
321 if (!dev_priv->evo) {
322 ret = nv50_evo_create(dev);
327 return nv50_evo_channel_init(dev_priv->evo);
331 nv50_evo_fini(struct drm_device *dev)
333 struct drm_nouveau_private *dev_priv = dev->dev_private;
336 nv50_evo_channel_fini(dev_priv->evo);
337 nv50_evo_channel_del(&dev_priv->evo);