3 #include "nouveau_drv.h"
4 #include "nouveau_drm.h"
7 struct page *r100c08_page;
12 nv50_fb_create(struct drm_device *dev)
14 struct drm_nouveau_private *dev_priv = dev->dev_private;
15 struct nv50_fb_priv *priv;
17 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
21 priv->r100c08_page = alloc_page(GFP_KERNEL | __GFP_ZERO);
22 if (!priv->r100c08_page) {
27 priv->r100c08 = pci_map_page(dev->pdev, priv->r100c08_page, 0,
28 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
29 if (pci_dma_mapping_error(dev->pdev, priv->r100c08)) {
30 __free_page(priv->r100c08_page);
35 dev_priv->engine.fb.priv = priv;
40 nv50_fb_init(struct drm_device *dev)
42 struct drm_nouveau_private *dev_priv = dev->dev_private;
43 struct nv50_fb_priv *priv;
46 if (!dev_priv->engine.fb.priv) {
47 ret = nv50_fb_create(dev);
51 priv = dev_priv->engine.fb.priv;
53 /* Not a clue what this is exactly. Without pointing it at a
54 * scratch page, VRAM->GART blits with M2MF (as in DDX DFS)
55 * cause IOMMU "read from address 0" errors (rh#561267)
57 nv_wr32(dev, 0x100c08, priv->r100c08 >> 8);
59 /* This is needed to get meaningful information from 100c90
60 * on traps. No idea what these values mean exactly. */
61 switch (dev_priv->chipset) {
63 nv_wr32(dev, 0x100c90, 0x000707ff);
68 nv_wr32(dev, 0x100c90, 0x000d0fff);
71 nv_wr32(dev, 0x100c90, 0x089d1fff);
74 nv_wr32(dev, 0x100c90, 0x001d07ff);
82 nv50_fb_takedown(struct drm_device *dev)
84 struct drm_nouveau_private *dev_priv = dev->dev_private;
85 struct nv50_fb_priv *priv;
87 priv = dev_priv->engine.fb.priv;
90 dev_priv->engine.fb.priv = NULL;
92 pci_unmap_page(dev->pdev, priv->r100c08, PAGE_SIZE,
93 PCI_DMA_BIDIRECTIONAL);
94 __free_page(priv->r100c08_page);
99 nv50_fb_vm_trap(struct drm_device *dev, int display, const char *name)
101 struct drm_nouveau_private *dev_priv = dev->dev_private;
103 u32 trap[6], idx, chinst;
106 idx = nv_rd32(dev, 0x100c90);
107 if (!(idx & 0x80000000))
111 for (i = 0; i < 6; i++) {
112 nv_wr32(dev, 0x100c90, idx | i << 24);
113 trap[i] = nv_rd32(dev, 0x100c94);
115 nv_wr32(dev, 0x100c90, idx | 0x80000000);
120 chinst = (trap[2] << 16) | trap[1];
122 spin_lock_irqsave(&dev_priv->channels.lock, flags);
123 for (ch = 0; ch < dev_priv->engine.fifo.channels; ch++) {
124 struct nouveau_channel *chan = dev_priv->channels.ptr[ch];
126 if (!chan || !chan->ramin)
129 if (chinst == chan->ramin->vinst >> 12)
132 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
134 NV_INFO(dev, "%s - VM: Trapped %s at %02x%04x%04x status %08x "
135 "channel %d (0x%08x)\n",
136 name, (trap[5] & 0x100 ? "read" : "write"),
137 trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff,
138 trap[0], ch, chinst);