drivers/gpu/drm/nouveau/nv50_fifo.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30 #include "nouveau_ramht.h"
  31
  32 static void
  33 nv50_fifo_playlist_update(struct drm_device *dev)
  34 {
  35         struct drm_nouveau_private *dev_priv = dev->dev_private;
  36         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
  37         struct nouveau_gpuobj *cur;
  38         int i, nr;
  39
  40         NV_DEBUG(dev, "\n");
  41
  42         cur = pfifo->playlist[pfifo->cur_playlist];
  43         pfifo->cur_playlist = !pfifo->cur_playlist;
  44
  45         /* We never schedule channel 0 or 127 */
  46         for (i = 1, nr = 0; i < 127; i++) {
  47                 if (dev_priv->channels.ptr[i] &&
  48                     dev_priv->channels.ptr[i]->ramfc) {
  49                         nv_wo32(cur, (nr * 4), i);
  50                         nr++;
  51                 }
  52         }
  53         dev_priv->engine.instmem.flush(dev);
  54
  55         nv_wr32(dev, 0x32f4, cur->vinst >> 12);
  56         nv_wr32(dev, 0x32ec, nr);
  57         nv_wr32(dev, 0x2500, 0x101);
  58 }
  59
  60 static void
  61 nv50_fifo_channel_enable(struct drm_device *dev, int channel)
  62 {
  63         struct drm_nouveau_private *dev_priv = dev->dev_private;
  64         struct nouveau_channel *chan = dev_priv->channels.ptr[channel];
  65         uint32_t inst;
  66
  67         NV_DEBUG(dev, "ch%d\n", channel);
  68
  69         if (dev_priv->chipset == 0x50)
  70                 inst = chan->ramfc->vinst >> 12;
  71         else
  72                 inst = chan->ramfc->vinst >> 8;
  73
  74         nv_wr32(dev, NV50_PFIFO_CTX_TABLE(channel), inst |
  75                      NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED);
  76 }
  77
  78 static void
  79 nv50_fifo_channel_disable(struct drm_device *dev, int channel)
  80 {
  81         struct drm_nouveau_private *dev_priv = dev->dev_private;
  82         uint32_t inst;
  83
  84         NV_DEBUG(dev, "ch%d\n", channel);
  85
  86         if (dev_priv->chipset == 0x50)
  87                 inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80;
  88         else
  89                 inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84;
  90         nv_wr32(dev, NV50_PFIFO_CTX_TABLE(channel), inst);
  91 }
  92
  93 static void
  94 nv50_fifo_init_reset(struct drm_device *dev)
  95 {
  96         uint32_t pmc_e = NV_PMC_ENABLE_PFIFO;
  97
  98         NV_DEBUG(dev, "\n");
  99
 100         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & ~pmc_e);
 101         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |  pmc_e);
 102 }
 103
 104 static void
 105 nv50_fifo_init_intr(struct drm_device *dev)
 106 {
 107         NV_DEBUG(dev, "\n");
 108
 109         nv_wr32(dev, NV03_PFIFO_INTR_0, 0xFFFFFFFF);
 110         nv_wr32(dev, NV03_PFIFO_INTR_EN_0, 0xFFFFFFFF);
 111 }
 112
 113 static void
 114 nv50_fifo_init_context_table(struct drm_device *dev)
 115 {
 116         struct drm_nouveau_private *dev_priv = dev->dev_private;
 117         int i;
 118
 119         NV_DEBUG(dev, "\n");
 120
 121         for (i = 0; i < NV50_PFIFO_CTX_TABLE__SIZE; i++) {
 122                 if (dev_priv->channels.ptr[i])
 123                         nv50_fifo_channel_enable(dev, i);
 124                 else
 125                         nv50_fifo_channel_disable(dev, i);
 126         }
 127
 128         nv50_fifo_playlist_update(dev);
 129 }
 130
 131 static void
 132 nv50_fifo_init_regs__nv(struct drm_device *dev)
 133 {
 134         NV_DEBUG(dev, "\n");
 135
 136         nv_wr32(dev, 0x250c, 0x6f3cfc34);
 137 }
 138
 139 static void
 140 nv50_fifo_init_regs(struct drm_device *dev)
 141 {
 142         NV_DEBUG(dev, "\n");
 143
 144         nv_wr32(dev, 0x2500, 0);
 145         nv_wr32(dev, 0x3250, 0);
 146         nv_wr32(dev, 0x3220, 0);
 147         nv_wr32(dev, 0x3204, 0);
 148         nv_wr32(dev, 0x3210, 0);
 149         nv_wr32(dev, 0x3270, 0);
 150
 151         /* Enable dummy channels setup by nv50_instmem.c */
 152         nv50_fifo_channel_enable(dev, 0);
 153         nv50_fifo_channel_enable(dev, 127);
 154 }
 155
 156 int
 157 nv50_fifo_init(struct drm_device *dev)
 158 {
 159         struct drm_nouveau_private *dev_priv = dev->dev_private;
 160         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 161         int ret;
 162
 163         NV_DEBUG(dev, "\n");
 164
 165         if (pfifo->playlist[0]) {
 166                 pfifo->cur_playlist = !pfifo->cur_playlist;
 167                 goto just_reset;
 168         }
 169
 170         ret = nouveau_gpuobj_new(dev, NULL, 128*4, 0x1000,
 171                                  NVOBJ_FLAG_ZERO_ALLOC,
 172                                  &pfifo->playlist[0]);
 173         if (ret) {
 174                 NV_ERROR(dev, "error creating playlist 0: %d\n", ret);
 175                 return ret;
 176         }
 177
 178         ret = nouveau_gpuobj_new(dev, NULL, 128*4, 0x1000,
 179                                  NVOBJ_FLAG_ZERO_ALLOC,
 180                                  &pfifo->playlist[1]);
 181         if (ret) {
 182                 nouveau_gpuobj_ref(NULL, &pfifo->playlist[0]);
 183                 NV_ERROR(dev, "error creating playlist 1: %d\n", ret);
 184                 return ret;
 185         }
 186
 187 just_reset:
 188         nv50_fifo_init_reset(dev);
 189         nv50_fifo_init_intr(dev);
 190         nv50_fifo_init_context_table(dev);
 191         nv50_fifo_init_regs__nv(dev);
 192         nv50_fifo_init_regs(dev);
 193         dev_priv->engine.fifo.enable(dev);
 194         dev_priv->engine.fifo.reassign(dev, true);
 195
 196         return 0;
 197 }
 198
 199 void
 200 nv50_fifo_takedown(struct drm_device *dev)
 201 {
 202         struct drm_nouveau_private *dev_priv = dev->dev_private;
 203         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 204
 205         NV_DEBUG(dev, "\n");
 206
 207         if (!pfifo->playlist[0])
 208                 return;
 209
 210         nouveau_gpuobj_ref(NULL, &pfifo->playlist[0]);
 211         nouveau_gpuobj_ref(NULL, &pfifo->playlist[1]);
 212 }
 213
 214 int
 215 nv50_fifo_channel_id(struct drm_device *dev)
 216 {
 217         return nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) &
 218                         NV50_PFIFO_CACHE1_PUSH1_CHID_MASK;
 219 }
 220
 221 int
 222 nv50_fifo_create_context(struct nouveau_channel *chan)
 223 {
 224         struct drm_device *dev = chan->dev;
 225         struct drm_nouveau_private *dev_priv = dev->dev_private;
 226         struct nouveau_gpuobj *ramfc = NULL;
 227         unsigned long flags;
 228         int ret;
 229
 230         NV_DEBUG(dev, "ch%d\n", chan->id);
 231
 232         if (dev_priv->chipset == 0x50) {
 233                 ret = nouveau_gpuobj_new_fake(dev, chan->ramin->pinst,
 234                                               chan->ramin->vinst, 0x100,
 235                                               NVOBJ_FLAG_ZERO_ALLOC |
 236                                               NVOBJ_FLAG_ZERO_FREE,
 237                                               &chan->ramfc);
 238                 if (ret)
 239                         return ret;
 240
 241                 ret = nouveau_gpuobj_new_fake(dev, chan->ramin->pinst + 0x0400,
 242                                               chan->ramin->vinst + 0x0400,
 243                                               4096, 0, &chan->cache);
 244                 if (ret)
 245                         return ret;
 246         } else {
 247                 ret = nouveau_gpuobj_new(dev, chan, 0x100, 256,
 248                                          NVOBJ_FLAG_ZERO_ALLOC |
 249                                          NVOBJ_FLAG_ZERO_FREE, &chan->ramfc);
 250                 if (ret)
 251                         return ret;
 252
 253                 ret = nouveau_gpuobj_new(dev, chan, 4096, 1024,
 254                                          0, &chan->cache);
 255                 if (ret)
 256                         return ret;
 257         }
 258         ramfc = chan->ramfc;
 259
 260         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 261
 262         nv_wo32(ramfc, 0x48, chan->pushbuf->cinst >> 4);
 263         nv_wo32(ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
 264                              (4 << 24) /* SEARCH_FULL */ |
 265                              (chan->ramht->gpuobj->cinst >> 4));
 266         nv_wo32(ramfc, 0x44, 0x2101ffff);
 267         nv_wo32(ramfc, 0x60, 0x7fffffff);
 268         nv_wo32(ramfc, 0x40, 0x00000000);
 269         nv_wo32(ramfc, 0x7c, 0x30000001);
 270         nv_wo32(ramfc, 0x78, 0x00000000);
 271         nv_wo32(ramfc, 0x3c, 0x403f6078);
 272         nv_wo32(ramfc, 0x50, chan->pushbuf_base + chan->dma.ib_base * 4);
 273         nv_wo32(ramfc, 0x54, drm_order(chan->dma.ib_max + 1) << 16);
 274
 275         if (dev_priv->chipset != 0x50) {
 276                 nv_wo32(chan->ramin, 0, chan->id);
 277                 nv_wo32(chan->ramin, 4, chan->ramfc->vinst >> 8);
 278
 279                 nv_wo32(ramfc, 0x88, chan->cache->vinst >> 10);
 280                 nv_wo32(ramfc, 0x98, chan->ramin->vinst >> 12);
 281         }
 282
 283         dev_priv->engine.instmem.flush(dev);
 284
 285         nv50_fifo_channel_enable(dev, chan->id);
 286         nv50_fifo_playlist_update(dev);
 287         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 288         return 0;
 289 }
 290
 291 void
 292 nv50_fifo_destroy_context(struct nouveau_channel *chan)
 293 {
 294         struct drm_device *dev = chan->dev;
 295         struct drm_nouveau_private *dev_priv = dev->dev_private;
 296         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 297         struct nouveau_gpuobj *ramfc = NULL;
 298         unsigned long flags;
 299
 300         NV_DEBUG(dev, "ch%d\n", chan->id);
 301
 302         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 303         pfifo->reassign(dev, false);
 304
 305         /* Unload the context if it's the currently active one */
 306         if (pfifo->channel_id(dev) == chan->id) {
 307                 pfifo->disable(dev);
 308                 pfifo->unload_context(dev);
 309                 pfifo->enable(dev);
 310         }
 311
 312         /* This will ensure the channel is seen as disabled. */
 313         nouveau_gpuobj_ref(chan->ramfc, &ramfc);
 314         nouveau_gpuobj_ref(NULL, &chan->ramfc);
 315         nv50_fifo_channel_disable(dev, chan->id);
 316
 317         /* Dummy channel, also used on ch 127 */
 318         if (chan->id == 0)
 319                 nv50_fifo_channel_disable(dev, 127);
 320         nv50_fifo_playlist_update(dev);
 321
 322         pfifo->reassign(dev, true);
 323         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 324
 325         /* Free the channel resources */
 326         nouveau_gpuobj_ref(NULL, &ramfc);
 327         nouveau_gpuobj_ref(NULL, &chan->cache);
 328 }
 329
 330 int
 331 nv50_fifo_load_context(struct nouveau_channel *chan)
 332 {
 333         struct drm_device *dev = chan->dev;
 334         struct drm_nouveau_private *dev_priv = dev->dev_private;
 335         struct nouveau_gpuobj *ramfc = chan->ramfc;
 336         struct nouveau_gpuobj *cache = chan->cache;
 337         int ptr, cnt;
 338
 339         NV_DEBUG(dev, "ch%d\n", chan->id);
 340
 341         nv_wr32(dev, 0x3330, nv_ro32(ramfc, 0x00));
 342         nv_wr32(dev, 0x3334, nv_ro32(ramfc, 0x04));
 343         nv_wr32(dev, 0x3240, nv_ro32(ramfc, 0x08));
 344         nv_wr32(dev, 0x3320, nv_ro32(ramfc, 0x0c));
 345         nv_wr32(dev, 0x3244, nv_ro32(ramfc, 0x10));
 346         nv_wr32(dev, 0x3328, nv_ro32(ramfc, 0x14));
 347         nv_wr32(dev, 0x3368, nv_ro32(ramfc, 0x18));
 348         nv_wr32(dev, 0x336c, nv_ro32(ramfc, 0x1c));
 349         nv_wr32(dev, 0x3370, nv_ro32(ramfc, 0x20));
 350         nv_wr32(dev, 0x3374, nv_ro32(ramfc, 0x24));
 351         nv_wr32(dev, 0x3378, nv_ro32(ramfc, 0x28));
 352         nv_wr32(dev, 0x337c, nv_ro32(ramfc, 0x2c));
 353         nv_wr32(dev, 0x3228, nv_ro32(ramfc, 0x30));
 354         nv_wr32(dev, 0x3364, nv_ro32(ramfc, 0x34));
 355         nv_wr32(dev, 0x32a0, nv_ro32(ramfc, 0x38));
 356         nv_wr32(dev, 0x3224, nv_ro32(ramfc, 0x3c));
 357         nv_wr32(dev, 0x324c, nv_ro32(ramfc, 0x40));
 358         nv_wr32(dev, 0x2044, nv_ro32(ramfc, 0x44));
 359         nv_wr32(dev, 0x322c, nv_ro32(ramfc, 0x48));
 360         nv_wr32(dev, 0x3234, nv_ro32(ramfc, 0x4c));
 361         nv_wr32(dev, 0x3340, nv_ro32(ramfc, 0x50));
 362         nv_wr32(dev, 0x3344, nv_ro32(ramfc, 0x54));
 363         nv_wr32(dev, 0x3280, nv_ro32(ramfc, 0x58));
 364         nv_wr32(dev, 0x3254, nv_ro32(ramfc, 0x5c));
 365         nv_wr32(dev, 0x3260, nv_ro32(ramfc, 0x60));
 366         nv_wr32(dev, 0x3264, nv_ro32(ramfc, 0x64));
 367         nv_wr32(dev, 0x3268, nv_ro32(ramfc, 0x68));
 368         nv_wr32(dev, 0x326c, nv_ro32(ramfc, 0x6c));
 369         nv_wr32(dev, 0x32e4, nv_ro32(ramfc, 0x70));
 370         nv_wr32(dev, 0x3248, nv_ro32(ramfc, 0x74));
 371         nv_wr32(dev, 0x2088, nv_ro32(ramfc, 0x78));
 372         nv_wr32(dev, 0x2058, nv_ro32(ramfc, 0x7c));
 373         nv_wr32(dev, 0x2210, nv_ro32(ramfc, 0x80));
 374
 375         cnt = nv_ro32(ramfc, 0x84);
 376         for (ptr = 0; ptr < cnt; ptr++) {
 377                 nv_wr32(dev, NV40_PFIFO_CACHE1_METHOD(ptr),
 378                         nv_ro32(cache, (ptr * 8) + 0));
 379                 nv_wr32(dev, NV40_PFIFO_CACHE1_DATA(ptr),
 380                         nv_ro32(cache, (ptr * 8) + 4));
 381         }
 382         nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, cnt << 2);
 383         nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
 384
 385         /* guessing that all the 0x34xx regs aren't on NV50 */
 386         if (dev_priv->chipset != 0x50) {
 387                 nv_wr32(dev, 0x340c, nv_ro32(ramfc, 0x88));
 388                 nv_wr32(dev, 0x3400, nv_ro32(ramfc, 0x8c));
 389                 nv_wr32(dev, 0x3404, nv_ro32(ramfc, 0x90));
 390                 nv_wr32(dev, 0x3408, nv_ro32(ramfc, 0x94));
 391                 nv_wr32(dev, 0x3410, nv_ro32(ramfc, 0x98));
 392         }
 393
 394         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, chan->id | (1<<16));
 395         return 0;
 396 }
 397
 398 int
 399 nv50_fifo_unload_context(struct drm_device *dev)
 400 {
 401         struct drm_nouveau_private *dev_priv = dev->dev_private;
 402         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 403         struct nouveau_gpuobj *ramfc, *cache;
 404         struct nouveau_channel *chan = NULL;
 405         int chid, get, put, ptr;
 406
 407         NV_DEBUG(dev, "\n");
 408
 409         chid = pfifo->channel_id(dev);
 410         if (chid < 1 || chid >= dev_priv->engine.fifo.channels - 1)
 411                 return 0;
 412
 413         chan = dev_priv->channels.ptr[chid];
 414         if (!chan) {
 415                 NV_ERROR(dev, "Inactive channel on PFIFO: %d\n", chid);
 416                 return -EINVAL;
 417         }
 418         NV_DEBUG(dev, "ch%d\n", chan->id);
 419         ramfc = chan->ramfc;
 420         cache = chan->cache;
 421
 422         nv_wo32(ramfc, 0x00, nv_rd32(dev, 0x3330));
 423         nv_wo32(ramfc, 0x04, nv_rd32(dev, 0x3334));
 424         nv_wo32(ramfc, 0x08, nv_rd32(dev, 0x3240));
 425         nv_wo32(ramfc, 0x0c, nv_rd32(dev, 0x3320));
 426         nv_wo32(ramfc, 0x10, nv_rd32(dev, 0x3244));
 427         nv_wo32(ramfc, 0x14, nv_rd32(dev, 0x3328));
 428         nv_wo32(ramfc, 0x18, nv_rd32(dev, 0x3368));
 429         nv_wo32(ramfc, 0x1c, nv_rd32(dev, 0x336c));
 430         nv_wo32(ramfc, 0x20, nv_rd32(dev, 0x3370));
 431         nv_wo32(ramfc, 0x24, nv_rd32(dev, 0x3374));
 432         nv_wo32(ramfc, 0x28, nv_rd32(dev, 0x3378));
 433         nv_wo32(ramfc, 0x2c, nv_rd32(dev, 0x337c));
 434         nv_wo32(ramfc, 0x30, nv_rd32(dev, 0x3228));
 435         nv_wo32(ramfc, 0x34, nv_rd32(dev, 0x3364));
 436         nv_wo32(ramfc, 0x38, nv_rd32(dev, 0x32a0));
 437         nv_wo32(ramfc, 0x3c, nv_rd32(dev, 0x3224));
 438         nv_wo32(ramfc, 0x40, nv_rd32(dev, 0x324c));
 439         nv_wo32(ramfc, 0x44, nv_rd32(dev, 0x2044));
 440         nv_wo32(ramfc, 0x48, nv_rd32(dev, 0x322c));
 441         nv_wo32(ramfc, 0x4c, nv_rd32(dev, 0x3234));
 442         nv_wo32(ramfc, 0x50, nv_rd32(dev, 0x3340));
 443         nv_wo32(ramfc, 0x54, nv_rd32(dev, 0x3344));
 444         nv_wo32(ramfc, 0x58, nv_rd32(dev, 0x3280));
 445         nv_wo32(ramfc, 0x5c, nv_rd32(dev, 0x3254));
 446         nv_wo32(ramfc, 0x60, nv_rd32(dev, 0x3260));
 447         nv_wo32(ramfc, 0x64, nv_rd32(dev, 0x3264));
 448         nv_wo32(ramfc, 0x68, nv_rd32(dev, 0x3268));
 449         nv_wo32(ramfc, 0x6c, nv_rd32(dev, 0x326c));
 450         nv_wo32(ramfc, 0x70, nv_rd32(dev, 0x32e4));
 451         nv_wo32(ramfc, 0x74, nv_rd32(dev, 0x3248));
 452         nv_wo32(ramfc, 0x78, nv_rd32(dev, 0x2088));
 453         nv_wo32(ramfc, 0x7c, nv_rd32(dev, 0x2058));
 454         nv_wo32(ramfc, 0x80, nv_rd32(dev, 0x2210));
 455
 456         put = (nv_rd32(dev, NV03_PFIFO_CACHE1_PUT) & 0x7ff) >> 2;
 457         get = (nv_rd32(dev, NV03_PFIFO_CACHE1_GET) & 0x7ff) >> 2;
 458         ptr = 0;
 459         while (put != get) {
 460                 nv_wo32(cache, ptr + 0,
 461                         nv_rd32(dev, NV40_PFIFO_CACHE1_METHOD(get)));
 462                 nv_wo32(cache, ptr + 4,
 463                         nv_rd32(dev, NV40_PFIFO_CACHE1_DATA(get)));
 464                 get = (get + 1) & 0x1ff;
 465                 ptr += 8;
 466         }
 467
 468         /* guessing that all the 0x34xx regs aren't on NV50 */
 469         if (dev_priv->chipset != 0x50) {
 470                 nv_wo32(ramfc, 0x84, ptr >> 3);
 471                 nv_wo32(ramfc, 0x88, nv_rd32(dev, 0x340c));
 472                 nv_wo32(ramfc, 0x8c, nv_rd32(dev, 0x3400));
 473                 nv_wo32(ramfc, 0x90, nv_rd32(dev, 0x3404));
 474                 nv_wo32(ramfc, 0x94, nv_rd32(dev, 0x3408));
 475                 nv_wo32(ramfc, 0x98, nv_rd32(dev, 0x3410));
 476         }
 477
 478         dev_priv->engine.instmem.flush(dev);
 479
 480         /*XXX: probably reload ch127 (NULL) state back too */
 481         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, 127);
 482         return 0;
 483 }
 484
 485 void
 486 nv50_fifo_tlb_flush(struct drm_device *dev)
 487 {
 488         nv50_vm_flush(dev, 5);
 489 }