drivers/gpu/drm/nouveau/nv50_fifo.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30 #include "nouveau_ramht.h"
  31
  32 static void
  33 nv50_fifo_playlist_update(struct drm_device *dev)
  34 {
  35         struct drm_nouveau_private *dev_priv = dev->dev_private;
  36         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
  37         struct nouveau_gpuobj *cur;
  38         int i, nr;
  39
  40         NV_DEBUG(dev, "\n");
  41
  42         cur = pfifo->playlist[pfifo->cur_playlist];
  43         pfifo->cur_playlist = !pfifo->cur_playlist;
  44
  45         /* We never schedule channel 0 or 127 */
  46         for (i = 1, nr = 0; i < 127; i++) {
  47                 if (dev_priv->channels.ptr[i] &&
  48                     dev_priv->channels.ptr[i]->ramfc) {
  49                         nv_wo32(cur, (nr * 4), i);
  50                         nr++;
  51                 }
  52         }
  53         dev_priv->engine.instmem.flush(dev);
  54
  55         nv_wr32(dev, 0x32f4, cur->vinst >> 12);
  56         nv_wr32(dev, 0x32ec, nr);
  57         nv_wr32(dev, 0x2500, 0x101);
  58 }
  59
  60 static void
  61 nv50_fifo_channel_enable(struct drm_device *dev, int channel)
  62 {
  63         struct drm_nouveau_private *dev_priv = dev->dev_private;
  64         struct nouveau_channel *chan = dev_priv->channels.ptr[channel];
  65         uint32_t inst;
  66
  67         NV_DEBUG(dev, "ch%d\n", channel);
  68
  69         if (dev_priv->chipset == 0x50)
  70                 inst = chan->ramfc->vinst >> 12;
  71         else
  72                 inst = chan->ramfc->vinst >> 8;
  73
  74         nv_wr32(dev, NV50_PFIFO_CTX_TABLE(channel), inst |
  75                      NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED);
  76 }
  77
  78 static void
  79 nv50_fifo_channel_disable(struct drm_device *dev, int channel)
  80 {
  81         struct drm_nouveau_private *dev_priv = dev->dev_private;
  82         uint32_t inst;
  83
  84         NV_DEBUG(dev, "ch%d\n", channel);
  85
  86         if (dev_priv->chipset == 0x50)
  87                 inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80;
  88         else
  89                 inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84;
  90         nv_wr32(dev, NV50_PFIFO_CTX_TABLE(channel), inst);
  91 }
  92
  93 static void
  94 nv50_fifo_init_reset(struct drm_device *dev)
  95 {
  96         uint32_t pmc_e = NV_PMC_ENABLE_PFIFO;
  97
  98         NV_DEBUG(dev, "\n");
  99
 100         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & ~pmc_e);
 101         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |  pmc_e);
 102 }
 103
 104 static void
 105 nv50_fifo_init_intr(struct drm_device *dev)
 106 {
 107         NV_DEBUG(dev, "\n");
 108
 109         nouveau_irq_register(dev, 8, nv04_fifo_isr);
 110         nv_wr32(dev, NV03_PFIFO_INTR_0, 0xFFFFFFFF);
 111         nv_wr32(dev, NV03_PFIFO_INTR_EN_0, 0xFFFFFFFF);
 112 }
 113
 114 static void
 115 nv50_fifo_init_context_table(struct drm_device *dev)
 116 {
 117         struct drm_nouveau_private *dev_priv = dev->dev_private;
 118         int i;
 119
 120         NV_DEBUG(dev, "\n");
 121
 122         for (i = 0; i < NV50_PFIFO_CTX_TABLE__SIZE; i++) {
 123                 if (dev_priv->channels.ptr[i])
 124                         nv50_fifo_channel_enable(dev, i);
 125                 else
 126                         nv50_fifo_channel_disable(dev, i);
 127         }
 128
 129         nv50_fifo_playlist_update(dev);
 130 }
 131
 132 static void
 133 nv50_fifo_init_regs__nv(struct drm_device *dev)
 134 {
 135         NV_DEBUG(dev, "\n");
 136
 137         nv_wr32(dev, 0x250c, 0x6f3cfc34);
 138 }
 139
 140 static void
 141 nv50_fifo_init_regs(struct drm_device *dev)
 142 {
 143         NV_DEBUG(dev, "\n");
 144
 145         nv_wr32(dev, 0x2500, 0);
 146         nv_wr32(dev, 0x3250, 0);
 147         nv_wr32(dev, 0x3220, 0);
 148         nv_wr32(dev, 0x3204, 0);
 149         nv_wr32(dev, 0x3210, 0);
 150         nv_wr32(dev, 0x3270, 0);
 151
 152         /* Enable dummy channels setup by nv50_instmem.c */
 153         nv50_fifo_channel_enable(dev, 0);
 154         nv50_fifo_channel_enable(dev, 127);
 155 }
 156
 157 int
 158 nv50_fifo_init(struct drm_device *dev)
 159 {
 160         struct drm_nouveau_private *dev_priv = dev->dev_private;
 161         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 162         int ret;
 163
 164         NV_DEBUG(dev, "\n");
 165
 166         if (pfifo->playlist[0]) {
 167                 pfifo->cur_playlist = !pfifo->cur_playlist;
 168                 goto just_reset;
 169         }
 170
 171         ret = nouveau_gpuobj_new(dev, NULL, 128*4, 0x1000,
 172                                  NVOBJ_FLAG_ZERO_ALLOC,
 173                                  &pfifo->playlist[0]);
 174         if (ret) {
 175                 NV_ERROR(dev, "error creating playlist 0: %d\n", ret);
 176                 return ret;
 177         }
 178
 179         ret = nouveau_gpuobj_new(dev, NULL, 128*4, 0x1000,
 180                                  NVOBJ_FLAG_ZERO_ALLOC,
 181                                  &pfifo->playlist[1]);
 182         if (ret) {
 183                 nouveau_gpuobj_ref(NULL, &pfifo->playlist[0]);
 184                 NV_ERROR(dev, "error creating playlist 1: %d\n", ret);
 185                 return ret;
 186         }
 187
 188 just_reset:
 189         nv50_fifo_init_reset(dev);
 190         nv50_fifo_init_intr(dev);
 191         nv50_fifo_init_context_table(dev);
 192         nv50_fifo_init_regs__nv(dev);
 193         nv50_fifo_init_regs(dev);
 194         dev_priv->engine.fifo.enable(dev);
 195         dev_priv->engine.fifo.reassign(dev, true);
 196
 197         return 0;
 198 }
 199
 200 void
 201 nv50_fifo_takedown(struct drm_device *dev)
 202 {
 203         struct drm_nouveau_private *dev_priv = dev->dev_private;
 204         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 205
 206         NV_DEBUG(dev, "\n");
 207
 208         if (!pfifo->playlist[0])
 209                 return;
 210
 211         nv_wr32(dev, 0x2140, 0x00000000);
 212         nouveau_irq_unregister(dev, 8);
 213
 214         nouveau_gpuobj_ref(NULL, &pfifo->playlist[0]);
 215         nouveau_gpuobj_ref(NULL, &pfifo->playlist[1]);
 216 }
 217
 218 int
 219 nv50_fifo_channel_id(struct drm_device *dev)
 220 {
 221         return nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) &
 222                         NV50_PFIFO_CACHE1_PUSH1_CHID_MASK;
 223 }
 224
 225 int
 226 nv50_fifo_create_context(struct nouveau_channel *chan)
 227 {
 228         struct drm_device *dev = chan->dev;
 229         struct drm_nouveau_private *dev_priv = dev->dev_private;
 230         struct nouveau_gpuobj *ramfc = NULL;
 231         unsigned long flags;
 232         int ret;
 233
 234         NV_DEBUG(dev, "ch%d\n", chan->id);
 235
 236         if (dev_priv->chipset == 0x50) {
 237                 ret = nouveau_gpuobj_new_fake(dev, chan->ramin->pinst,
 238                                               chan->ramin->vinst, 0x100,
 239                                               NVOBJ_FLAG_ZERO_ALLOC |
 240                                               NVOBJ_FLAG_ZERO_FREE,
 241                                               &chan->ramfc);
 242                 if (ret)
 243                         return ret;
 244
 245                 ret = nouveau_gpuobj_new_fake(dev, chan->ramin->pinst + 0x0400,
 246                                               chan->ramin->vinst + 0x0400,
 247                                               4096, 0, &chan->cache);
 248                 if (ret)
 249                         return ret;
 250         } else {
 251                 ret = nouveau_gpuobj_new(dev, chan, 0x100, 256,
 252                                          NVOBJ_FLAG_ZERO_ALLOC |
 253                                          NVOBJ_FLAG_ZERO_FREE, &chan->ramfc);
 254                 if (ret)
 255                         return ret;
 256
 257                 ret = nouveau_gpuobj_new(dev, chan, 4096, 1024,
 258                                          0, &chan->cache);
 259                 if (ret)
 260                         return ret;
 261         }
 262         ramfc = chan->ramfc;
 263
 264         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 265
 266         nv_wo32(ramfc, 0x48, chan->pushbuf->cinst >> 4);
 267         nv_wo32(ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
 268                              (4 << 24) /* SEARCH_FULL */ |
 269                              (chan->ramht->gpuobj->cinst >> 4));
 270         nv_wo32(ramfc, 0x44, 0x2101ffff);
 271         nv_wo32(ramfc, 0x60, 0x7fffffff);
 272         nv_wo32(ramfc, 0x40, 0x00000000);
 273         nv_wo32(ramfc, 0x7c, 0x30000001);
 274         nv_wo32(ramfc, 0x78, 0x00000000);
 275         nv_wo32(ramfc, 0x3c, 0x403f6078);
 276         nv_wo32(ramfc, 0x50, chan->pushbuf_base + chan->dma.ib_base * 4);
 277         nv_wo32(ramfc, 0x54, drm_order(chan->dma.ib_max + 1) << 16);
 278
 279         if (dev_priv->chipset != 0x50) {
 280                 nv_wo32(chan->ramin, 0, chan->id);
 281                 nv_wo32(chan->ramin, 4, chan->ramfc->vinst >> 8);
 282
 283                 nv_wo32(ramfc, 0x88, chan->cache->vinst >> 10);
 284                 nv_wo32(ramfc, 0x98, chan->ramin->vinst >> 12);
 285         }
 286
 287         dev_priv->engine.instmem.flush(dev);
 288
 289         nv50_fifo_channel_enable(dev, chan->id);
 290         nv50_fifo_playlist_update(dev);
 291         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 292         return 0;
 293 }
 294
 295 void
 296 nv50_fifo_destroy_context(struct nouveau_channel *chan)
 297 {
 298         struct drm_device *dev = chan->dev;
 299         struct drm_nouveau_private *dev_priv = dev->dev_private;
 300         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 301         struct nouveau_gpuobj *ramfc = NULL;
 302         unsigned long flags;
 303
 304         NV_DEBUG(dev, "ch%d\n", chan->id);
 305
 306         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 307         pfifo->reassign(dev, false);
 308
 309         /* Unload the context if it's the currently active one */
 310         if (pfifo->channel_id(dev) == chan->id) {
 311                 pfifo->disable(dev);
 312                 pfifo->unload_context(dev);
 313                 pfifo->enable(dev);
 314         }
 315
 316         /* This will ensure the channel is seen as disabled. */
 317         nouveau_gpuobj_ref(chan->ramfc, &ramfc);
 318         nouveau_gpuobj_ref(NULL, &chan->ramfc);
 319         nv50_fifo_channel_disable(dev, chan->id);
 320
 321         /* Dummy channel, also used on ch 127 */
 322         if (chan->id == 0)
 323                 nv50_fifo_channel_disable(dev, 127);
 324         nv50_fifo_playlist_update(dev);
 325
 326         pfifo->reassign(dev, true);
 327         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 328
 329         /* Free the channel resources */
 330         nouveau_gpuobj_ref(NULL, &ramfc);
 331         nouveau_gpuobj_ref(NULL, &chan->cache);
 332 }
 333
 334 int
 335 nv50_fifo_load_context(struct nouveau_channel *chan)
 336 {
 337         struct drm_device *dev = chan->dev;
 338         struct drm_nouveau_private *dev_priv = dev->dev_private;
 339         struct nouveau_gpuobj *ramfc = chan->ramfc;
 340         struct nouveau_gpuobj *cache = chan->cache;
 341         int ptr, cnt;
 342
 343         NV_DEBUG(dev, "ch%d\n", chan->id);
 344
 345         nv_wr32(dev, 0x3330, nv_ro32(ramfc, 0x00));
 346         nv_wr32(dev, 0x3334, nv_ro32(ramfc, 0x04));
 347         nv_wr32(dev, 0x3240, nv_ro32(ramfc, 0x08));
 348         nv_wr32(dev, 0x3320, nv_ro32(ramfc, 0x0c));
 349         nv_wr32(dev, 0x3244, nv_ro32(ramfc, 0x10));
 350         nv_wr32(dev, 0x3328, nv_ro32(ramfc, 0x14));
 351         nv_wr32(dev, 0x3368, nv_ro32(ramfc, 0x18));
 352         nv_wr32(dev, 0x336c, nv_ro32(ramfc, 0x1c));
 353         nv_wr32(dev, 0x3370, nv_ro32(ramfc, 0x20));
 354         nv_wr32(dev, 0x3374, nv_ro32(ramfc, 0x24));
 355         nv_wr32(dev, 0x3378, nv_ro32(ramfc, 0x28));
 356         nv_wr32(dev, 0x337c, nv_ro32(ramfc, 0x2c));
 357         nv_wr32(dev, 0x3228, nv_ro32(ramfc, 0x30));
 358         nv_wr32(dev, 0x3364, nv_ro32(ramfc, 0x34));
 359         nv_wr32(dev, 0x32a0, nv_ro32(ramfc, 0x38));
 360         nv_wr32(dev, 0x3224, nv_ro32(ramfc, 0x3c));
 361         nv_wr32(dev, 0x324c, nv_ro32(ramfc, 0x40));
 362         nv_wr32(dev, 0x2044, nv_ro32(ramfc, 0x44));
 363         nv_wr32(dev, 0x322c, nv_ro32(ramfc, 0x48));
 364         nv_wr32(dev, 0x3234, nv_ro32(ramfc, 0x4c));
 365         nv_wr32(dev, 0x3340, nv_ro32(ramfc, 0x50));
 366         nv_wr32(dev, 0x3344, nv_ro32(ramfc, 0x54));
 367         nv_wr32(dev, 0x3280, nv_ro32(ramfc, 0x58));
 368         nv_wr32(dev, 0x3254, nv_ro32(ramfc, 0x5c));
 369         nv_wr32(dev, 0x3260, nv_ro32(ramfc, 0x60));
 370         nv_wr32(dev, 0x3264, nv_ro32(ramfc, 0x64));
 371         nv_wr32(dev, 0x3268, nv_ro32(ramfc, 0x68));
 372         nv_wr32(dev, 0x326c, nv_ro32(ramfc, 0x6c));
 373         nv_wr32(dev, 0x32e4, nv_ro32(ramfc, 0x70));
 374         nv_wr32(dev, 0x3248, nv_ro32(ramfc, 0x74));
 375         nv_wr32(dev, 0x2088, nv_ro32(ramfc, 0x78));
 376         nv_wr32(dev, 0x2058, nv_ro32(ramfc, 0x7c));
 377         nv_wr32(dev, 0x2210, nv_ro32(ramfc, 0x80));
 378
 379         cnt = nv_ro32(ramfc, 0x84);
 380         for (ptr = 0; ptr < cnt; ptr++) {
 381                 nv_wr32(dev, NV40_PFIFO_CACHE1_METHOD(ptr),
 382                         nv_ro32(cache, (ptr * 8) + 0));
 383                 nv_wr32(dev, NV40_PFIFO_CACHE1_DATA(ptr),
 384                         nv_ro32(cache, (ptr * 8) + 4));
 385         }
 386         nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, cnt << 2);
 387         nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
 388
 389         /* guessing that all the 0x34xx regs aren't on NV50 */
 390         if (dev_priv->chipset != 0x50) {
 391                 nv_wr32(dev, 0x340c, nv_ro32(ramfc, 0x88));
 392                 nv_wr32(dev, 0x3400, nv_ro32(ramfc, 0x8c));
 393                 nv_wr32(dev, 0x3404, nv_ro32(ramfc, 0x90));
 394                 nv_wr32(dev, 0x3408, nv_ro32(ramfc, 0x94));
 395                 nv_wr32(dev, 0x3410, nv_ro32(ramfc, 0x98));
 396         }
 397
 398         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, chan->id | (1<<16));
 399         return 0;
 400 }
 401
 402 int
 403 nv50_fifo_unload_context(struct drm_device *dev)
 404 {
 405         struct drm_nouveau_private *dev_priv = dev->dev_private;
 406         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 407         struct nouveau_gpuobj *ramfc, *cache;
 408         struct nouveau_channel *chan = NULL;
 409         int chid, get, put, ptr;
 410
 411         NV_DEBUG(dev, "\n");
 412
 413         chid = pfifo->channel_id(dev);
 414         if (chid < 1 || chid >= dev_priv->engine.fifo.channels - 1)
 415                 return 0;
 416
 417         chan = dev_priv->channels.ptr[chid];
 418         if (!chan) {
 419                 NV_ERROR(dev, "Inactive channel on PFIFO: %d\n", chid);
 420                 return -EINVAL;
 421         }
 422         NV_DEBUG(dev, "ch%d\n", chan->id);
 423         ramfc = chan->ramfc;
 424         cache = chan->cache;
 425
 426         nv_wo32(ramfc, 0x00, nv_rd32(dev, 0x3330));
 427         nv_wo32(ramfc, 0x04, nv_rd32(dev, 0x3334));
 428         nv_wo32(ramfc, 0x08, nv_rd32(dev, 0x3240));
 429         nv_wo32(ramfc, 0x0c, nv_rd32(dev, 0x3320));
 430         nv_wo32(ramfc, 0x10, nv_rd32(dev, 0x3244));
 431         nv_wo32(ramfc, 0x14, nv_rd32(dev, 0x3328));
 432         nv_wo32(ramfc, 0x18, nv_rd32(dev, 0x3368));
 433         nv_wo32(ramfc, 0x1c, nv_rd32(dev, 0x336c));
 434         nv_wo32(ramfc, 0x20, nv_rd32(dev, 0x3370));
 435         nv_wo32(ramfc, 0x24, nv_rd32(dev, 0x3374));
 436         nv_wo32(ramfc, 0x28, nv_rd32(dev, 0x3378));
 437         nv_wo32(ramfc, 0x2c, nv_rd32(dev, 0x337c));
 438         nv_wo32(ramfc, 0x30, nv_rd32(dev, 0x3228));
 439         nv_wo32(ramfc, 0x34, nv_rd32(dev, 0x3364));
 440         nv_wo32(ramfc, 0x38, nv_rd32(dev, 0x32a0));
 441         nv_wo32(ramfc, 0x3c, nv_rd32(dev, 0x3224));
 442         nv_wo32(ramfc, 0x40, nv_rd32(dev, 0x324c));
 443         nv_wo32(ramfc, 0x44, nv_rd32(dev, 0x2044));
 444         nv_wo32(ramfc, 0x48, nv_rd32(dev, 0x322c));
 445         nv_wo32(ramfc, 0x4c, nv_rd32(dev, 0x3234));
 446         nv_wo32(ramfc, 0x50, nv_rd32(dev, 0x3340));
 447         nv_wo32(ramfc, 0x54, nv_rd32(dev, 0x3344));
 448         nv_wo32(ramfc, 0x58, nv_rd32(dev, 0x3280));
 449         nv_wo32(ramfc, 0x5c, nv_rd32(dev, 0x3254));
 450         nv_wo32(ramfc, 0x60, nv_rd32(dev, 0x3260));
 451         nv_wo32(ramfc, 0x64, nv_rd32(dev, 0x3264));
 452         nv_wo32(ramfc, 0x68, nv_rd32(dev, 0x3268));
 453         nv_wo32(ramfc, 0x6c, nv_rd32(dev, 0x326c));
 454         nv_wo32(ramfc, 0x70, nv_rd32(dev, 0x32e4));
 455         nv_wo32(ramfc, 0x74, nv_rd32(dev, 0x3248));
 456         nv_wo32(ramfc, 0x78, nv_rd32(dev, 0x2088));
 457         nv_wo32(ramfc, 0x7c, nv_rd32(dev, 0x2058));
 458         nv_wo32(ramfc, 0x80, nv_rd32(dev, 0x2210));
 459
 460         put = (nv_rd32(dev, NV03_PFIFO_CACHE1_PUT) & 0x7ff) >> 2;
 461         get = (nv_rd32(dev, NV03_PFIFO_CACHE1_GET) & 0x7ff) >> 2;
 462         ptr = 0;
 463         while (put != get) {
 464                 nv_wo32(cache, ptr + 0,
 465                         nv_rd32(dev, NV40_PFIFO_CACHE1_METHOD(get)));
 466                 nv_wo32(cache, ptr + 4,
 467                         nv_rd32(dev, NV40_PFIFO_CACHE1_DATA(get)));
 468                 get = (get + 1) & 0x1ff;
 469                 ptr += 8;
 470         }
 471
 472         /* guessing that all the 0x34xx regs aren't on NV50 */
 473         if (dev_priv->chipset != 0x50) {
 474                 nv_wo32(ramfc, 0x84, ptr >> 3);
 475                 nv_wo32(ramfc, 0x88, nv_rd32(dev, 0x340c));
 476                 nv_wo32(ramfc, 0x8c, nv_rd32(dev, 0x3400));
 477                 nv_wo32(ramfc, 0x90, nv_rd32(dev, 0x3404));
 478                 nv_wo32(ramfc, 0x94, nv_rd32(dev, 0x3408));
 479                 nv_wo32(ramfc, 0x98, nv_rd32(dev, 0x3410));
 480         }
 481
 482         dev_priv->engine.instmem.flush(dev);
 483
 484         /*XXX: probably reload ch127 (NULL) state back too */
 485         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, 127);
 486         return 0;
 487 }
 488
 489 void
 490 nv50_fifo_tlb_flush(struct drm_device *dev)
 491 {
 492         nv50_vm_flush(dev, 5);
 493 }